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Bug # 114
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/*Is true unsafe:*/ /*Number of usage points:2*/ /*Number of usages :2*/ /*Two examples:*/ /*_____________________*/ /*spin_lock(char *"_rf_ps_lock_of_rtl_locks")[1]*/ { return ; } { /*_____________________*/ 566 unsigned char ldvarg18; 567 unsigned int ldvarg11; 568 _Bool ldvarg51; 569 unsigned char ldvarg32; 570 unsigned int ldvarg7; 571 unsigned int ldvarg23; 572 u32 *ldvarg43; 573 enum nl80211_iftype ldvarg42; 574 enum radio_path ldvarg12; 575 u8 *ldvarg56; 576 unsigned int ldvarg50; 577 unsigned char ldvarg46; 578 struct ieee80211_rx_status *ldvarg1; 579 _Bool ldvarg37; 580 unsigned int ldvarg53; 581 unsigned char ldvarg29; 582 u32 *ldvarg44; 583 unsigned int ldvarg24; 584 unsigned int ldvarg35; 585 u8 *ldvarg0; 586 u8 *ldvarg38; 587 unsigned char ldvarg5; 588 _Bool ldvarg33; 589 enum rf_pwrstate ldvarg16; 590 unsigned int ldvarg6; 591 u8 *ldvarg48; 592 unsigned short ldvarg4; 593 unsigned char ldvarg14; 594 u8 *ldvarg34; 595 struct ieee80211_hdr *ldvarg28; 596 struct rtl_stats *ldvarg2; 597 _Bool ldvarg47; 598 unsigned char ldvarg39; 599 _Bool ldvarg20; 600 struct ieee80211_tx_info *ldvarg31; 601 enum led_ctl_mode ldvarg41; 602 unsigned char ldvarg3; 603 _Bool ldvarg49; 604 unsigned char ldvarg57; 605 enum radio_path ldvarg8; 606 unsigned int ldvarg13; 607 unsigned int ldvarg55; 608 unsigned int ldvarg36; 609 unsigned int ldvarg10; 610 u8 *ldvarg40; 611 struct rtl_stats ldvarg9; 612 _Bool ldvarg45; 613 u8 *ldvarg26; 614 struct rtl_tcb_desc *ldvarg27; 615 enum nl80211_channel_type ldvarg15; 616 u8 *ldvarg30; 617 _Bool ldvarg21; 618 unsigned int ldvarg54; 619 u8 *ldvarg17; 620 u8 *ldvarg25; 621 u8 *ldvarg22; 622 int ldvarg19; 623 unsigned char ldvarg52; 624 const struct pci_device_id *ldvarg58; 625 int tmp; 626 int tmp___0; 627 int tmp___1; 628 int tmp___2; 629 int tmp___3; 565 ldv_initialize() { /* Function call is skipped due to function is undefined */} 627 ldv_state_variable_6 = 0; 629 ldv_state_variable_3 = 1; 630 ldv_state_variable_7 = 0; 634 ldv_state_variable_2 = 1; 638 ldv_state_variable_1 = 1; 640 ldv_state_variable_4 = 1; 641 ref_cnt = 0; 642 ldv_state_variable_0 = 1; 643 ldv_state_variable_5 = 0; 644 ldv_58533:; 645 tmp = __VERIFIER_nondet_int() { /* Function call is skipped due to function is undefined */} 645 switch (tmp); 888 tmp___1 = __VERIFIER_nondet_int() { /* Function call is skipped due to function is undefined */} 888 switch (tmp___1); { 2288 struct rtl_priv *rtlpriv; 2289 struct rtl_ps_ctl *ppsc; 2290 enum rf_pwrstate e_rfpowerstate_toset; 2291 enum rf_pwrstate cur_rfstate; 2292 unsigned int u4tmp; 2293 _Bool b_actuallyset; 2294 int tmp; 2295 int tmp___0; 2296 long tmp___1; 2297 int tmp___2; 2298 int tmp___3; 2299 long tmp___4; 2288 struct rtl_priv *__CPAchecker_TMP_0 = (struct rtl_priv *)(hw->priv); 2288 rtlpriv = __CPAchecker_TMP_0; 2289 struct rtl_priv *__CPAchecker_TMP_1 = (struct rtl_priv *)(hw->priv); 2289 ppsc = &(__CPAchecker_TMP_1->psc); 2292 b_actuallyset = 0; 2297 int __CPAchecker_TMP_2 = (int)(ppsc->swrf_processing); { /*Change states for locks spin_lock(char *"_rf_ps_lock_of_rtl_locks")*/ 629 ldv_spin_lock(lock, (char *)"_rf_ps_lock_of_rtl_locks") { /* Function call is skipped due to function is undefined */} } 2301 int __CPAchecker_TMP_3 = (int)(ppsc->rfchange_inprogress); 2305 ppsc->rfchange_inprogress = 1; 2306 ldv_spin_unlock_204(&(rtlpriv->locks.rf_ps_lock)) { /* Function call is skipped due to function is undefined */} return ;; } return ;; }/*Without locks*/ { return ; } { 566 unsigned char ldvarg18; 567 unsigned int ldvarg11; 568 _Bool ldvarg51; 569 unsigned char ldvarg32; 570 unsigned int ldvarg7; 571 unsigned int ldvarg23; 572 u32 *ldvarg43; 573 enum nl80211_iftype ldvarg42; 574 enum radio_path ldvarg12; 575 u8 *ldvarg56; 576 unsigned int ldvarg50; 577 unsigned char ldvarg46; 578 struct ieee80211_rx_status *ldvarg1; 579 _Bool ldvarg37; 580 unsigned int ldvarg53; 581 unsigned char ldvarg29; 582 u32 *ldvarg44; 583 unsigned int ldvarg24; 584 unsigned int ldvarg35; 585 u8 *ldvarg0; 586 u8 *ldvarg38; 587 unsigned char ldvarg5; 588 _Bool ldvarg33; 589 enum rf_pwrstate ldvarg16; 590 unsigned int ldvarg6; 591 u8 *ldvarg48; 592 unsigned short ldvarg4; 593 unsigned char ldvarg14; 594 u8 *ldvarg34; 595 struct ieee80211_hdr *ldvarg28; 596 struct rtl_stats *ldvarg2; 597 _Bool ldvarg47; 598 unsigned char ldvarg39; 599 _Bool ldvarg20; 600 struct ieee80211_tx_info *ldvarg31; 601 enum led_ctl_mode ldvarg41; 602 unsigned char ldvarg3; 603 _Bool ldvarg49; 604 unsigned char ldvarg57; 605 enum radio_path ldvarg8; 606 unsigned int ldvarg13; 607 unsigned int ldvarg55; 608 unsigned int ldvarg36; 609 unsigned int ldvarg10; 610 u8 *ldvarg40; 611 struct rtl_stats ldvarg9; 612 _Bool ldvarg45; 613 u8 *ldvarg26; 614 struct rtl_tcb_desc *ldvarg27; 615 enum nl80211_channel_type ldvarg15; 616 u8 *ldvarg30; 617 _Bool ldvarg21; 618 unsigned int ldvarg54; 619 u8 *ldvarg17; 620 u8 *ldvarg25; 621 u8 *ldvarg22; 622 int ldvarg19; 623 unsigned char ldvarg52; 624 const struct pci_device_id *ldvarg58; 625 int tmp; 626 int tmp___0; 627 int tmp___1; 628 int tmp___2; 629 int tmp___3; 565 ldv_initialize() { /* Function call is skipped due to function is undefined */} 627 ldv_state_variable_6 = 0; 629 ldv_state_variable_3 = 1; 630 ldv_state_variable_7 = 0; 634 ldv_state_variable_2 = 1; 638 ldv_state_variable_1 = 1; 640 ldv_state_variable_4 = 1; 641 ref_cnt = 0; 642 ldv_state_variable_0 = 1; 643 ldv_state_variable_5 = 0; 644 ldv_58533:; 645 tmp = __VERIFIER_nondet_int() { /* Function call is skipped due to function is undefined */} 645 switch (tmp); 888 tmp___1 = __VERIFIER_nondet_int() { /* Function call is skipped due to function is undefined */} 888 switch (tmp___1); { 1781 struct rtl_priv *rtlpriv; 1782 struct rtl_ps_ctl *ppsc; 1783 _Bool fw_current_inpsmode; 1784 _Bool fw_ps_awake; 1781 struct rtl_priv *__CPAchecker_TMP_0 = (struct rtl_priv *)(hw->priv); 1781 rtlpriv = __CPAchecker_TMP_0; 1782 struct rtl_priv *__CPAchecker_TMP_1 = (struct rtl_priv *)(hw->priv); 1782 ppsc = &(__CPAchecker_TMP_1->psc); 1783 fw_current_inpsmode = 0; 1784 fw_ps_awake = 1; 1786 (*(rtlpriv->cfg->ops->get_hw_reg))(hw, 65, (u8 *)(&fw_current_inpsmode)); 1788 (*(rtlpriv->cfg->ops->get_hw_reg))(hw, 86, (u8 *)(&fw_ps_awake)); 1793 unsigned int __CPAchecker_TMP_2 = (unsigned int)(ppsc->rfpwr_state); return ;; } return ;; } | Source code 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../base.h"
28 #include "../pci.h"
29 #include "../core.h"
30 #include "reg.h"
31 #include "def.h"
32 #include "phy.h"
33 #include "dm.h"
34 #include "fw.h"
35 #include "trx.h"
36
37 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
38 0x7f8001fe, /* 0, +6.0dB */
39 0x788001e2, /* 1, +5.5dB */
40 0x71c001c7, /* 2, +5.0dB */
41 0x6b8001ae, /* 3, +4.5dB */
42 0x65400195, /* 4, +4.0dB */
43 0x5fc0017f, /* 5, +3.5dB */
44 0x5a400169, /* 6, +3.0dB */
45 0x55400155, /* 7, +2.5dB */
46 0x50800142, /* 8, +2.0dB */
47 0x4c000130, /* 9, +1.5dB */
48 0x47c0011f, /* 10, +1.0dB */
49 0x43c0010f, /* 11, +0.5dB */
50 0x40000100, /* 12, +0dB */
51 0x3c8000f2, /* 13, -0.5dB */
52 0x390000e4, /* 14, -1.0dB */
53 0x35c000d7, /* 15, -1.5dB */
54 0x32c000cb, /* 16, -2.0dB */
55 0x300000c0, /* 17, -2.5dB */
56 0x2d4000b5, /* 18, -3.0dB */
57 0x2ac000ab, /* 19, -3.5dB */
58 0x288000a2, /* 20, -4.0dB */
59 0x26000098, /* 21, -4.5dB */
60 0x24000090, /* 22, -5.0dB */
61 0x22000088, /* 23, -5.5dB */
62 0x20000080, /* 24, -6.0dB */
63 0x1e400079, /* 25, -6.5dB */
64 0x1c800072, /* 26, -7.0dB */
65 0x1b00006c, /* 27. -7.5dB */
66 0x19800066, /* 28, -8.0dB */
67 0x18000060, /* 29, -8.5dB */
68 0x16c0005b, /* 30, -9.0dB */
69 0x15800056, /* 31, -9.5dB */
70 0x14400051, /* 32, -10.0dB */
71 0x1300004c, /* 33, -10.5dB */
72 0x12000048, /* 34, -11.0dB */
73 0x11000044, /* 35, -11.5dB */
74 0x10000040, /* 36, -12.0dB */
75 0x0f00003c, /* 37, -12.5dB */
76 0x0e400039, /* 38, -13.0dB */
77 0x0d800036, /* 39, -13.5dB */
78 0x0cc00033, /* 40, -14.0dB */
79 0x0c000030, /* 41, -14.5dB */
80 0x0b40002d, /* 42, -15.0dB */
81 };
82
83 static const u8 cck_tbl_ch1_13[CCK_TABLE_SIZE][8] = {
84 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
85 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
86 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
87 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
88 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
89 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
90 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
91 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
92 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
93 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
94 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
95 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
96 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
97 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
98 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
99 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
100 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
101 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
102 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
103 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
104 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
105 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
106 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
107 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
108 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
109 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
110 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
111 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
112 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
113 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
114 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
115 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
116 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
117 };
118
119 static const u8 cck_tbl_ch14[CCK_TABLE_SIZE][8] = {
120 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
121 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
122 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
123 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
124 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
125 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
126 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
127 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
128 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
129 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
130 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
131 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
132 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
133 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
134 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
135 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
136 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
137 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
138 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
139 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
140 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
141 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
142 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
143 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
144 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
145 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
146 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
147 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
148 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
149 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
150 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
151 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
152 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
153 };
154
155 #define CAL_SWING_OFF(_off, _dir, _size, _del) \
156 do { \
157 for (_off = 0; _off < _size; _off++) { \
158 if (_del < thermal_threshold[_dir][_off]) { \
159 if (_off != 0) \
160 _off--; \
161 break; \
162 } \
163 } \
164 if (_off >= _size) \
165 _off = _size - 1; \
166 } while (0)
167
168 static void rtl88e_set_iqk_matrix(struct ieee80211_hw *hw,
169 u8 ofdm_index, u8 rfpath,
170 long iqk_result_x, long iqk_result_y)
171 {
172 long ele_a = 0, ele_d, ele_c = 0, value32;
173
174 ele_d = (ofdmswing_table[ofdm_index] & 0xFFC00000)>>22;
175
176 if (iqk_result_x != 0) {
177 if ((iqk_result_x & 0x00000200) != 0)
178 iqk_result_x = iqk_result_x | 0xFFFFFC00;
179 ele_a = ((iqk_result_x * ele_d)>>8)&0x000003FF;
180
181 if ((iqk_result_y & 0x00000200) != 0)
182 iqk_result_y = iqk_result_y | 0xFFFFFC00;
183 ele_c = ((iqk_result_y * ele_d)>>8)&0x000003FF;
184
185 switch (rfpath) {
186 case RF90_PATH_A:
187 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
188 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
189 MASKDWORD, value32);
190 value32 = (ele_c & 0x000003C0) >> 6;
191 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
192 value32);
193 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
194 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
195 value32);
196 break;
197 case RF90_PATH_B:
198 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
199 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
200 value32);
201 value32 = (ele_c & 0x000003C0) >> 6;
202 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32);
203 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
204 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
205 value32);
206 break;
207 default:
208 break;
209 }
210 } else {
211 switch (rfpath) {
212 case RF90_PATH_A:
213 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
214 MASKDWORD, ofdmswing_table[ofdm_index]);
215 rtl_set_bbreg(hw, ROFDM0_XCTXAFE,
216 MASKH4BITS, 0x00);
217 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
218 BIT(24), 0x00);
219 break;
220 case RF90_PATH_B:
221 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
222 MASKDWORD, ofdmswing_table[ofdm_index]);
223 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
224 MASKH4BITS, 0x00);
225 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
226 BIT(28), 0x00);
227 break;
228 default:
229 break;
230 }
231 }
232 }
233
234 void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
235 u8 type, u8 *pdirection, u32 *poutwrite_val)
236 {
237 struct rtl_priv *rtlpriv = rtl_priv(hw);
238 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
239 u8 pwr_val = 0;
240 u8 cck_base = rtldm->swing_idx_cck_base;
241 u8 cck_val = rtldm->swing_idx_cck;
242 u8 ofdm_base = rtldm->swing_idx_ofdm_base[0];
243 u8 ofdm_val = rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A];
244
245 if (type == 0) {
246 if (ofdm_val <= ofdm_base) {
247 *pdirection = 1;
248 pwr_val = ofdm_base - ofdm_val;
249 } else {
250 *pdirection = 2;
251 pwr_val = ofdm_base - ofdm_val;
252 }
253 } else if (type == 1) {
254 if (cck_val <= cck_base) {
255 *pdirection = 1;
256 pwr_val = cck_base - cck_val;
257 } else {
258 *pdirection = 2;
259 pwr_val = cck_val - cck_base;
260 }
261 }
262
263 if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1))
264 pwr_val = TXPWRTRACK_MAX_IDX;
265
266 *poutwrite_val = pwr_val | (pwr_val << 8) | (pwr_val << 16) |
267 (pwr_val << 24);
268 }
269
270 static void dm_tx_pwr_track_set_pwr(struct ieee80211_hw *hw,
271 enum pwr_track_control_method method,
272 u8 rfpath, u8 channel_mapped_index)
273 {
274 struct rtl_priv *rtlpriv = rtl_priv(hw);
275 struct rtl_phy *rtlphy = &rtlpriv->phy;
276 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
277
278 if (method == TXAGC) {
279 if (rtldm->swing_flag_ofdm ||
280 rtldm->swing_flag_cck) {
281 rtl88e_phy_set_txpower_level(hw,
282 rtlphy->current_channel);
283 rtldm->swing_flag_ofdm = false;
284 rtldm->swing_flag_cck = false;
285 }
286 } else if (method == BBSWING) {
287 if (!rtldm->cck_inch14) {
288 rtl_write_byte(rtlpriv, 0xa22,
289 cck_tbl_ch1_13[rtldm->swing_idx_cck][0]);
290 rtl_write_byte(rtlpriv, 0xa23,
291 cck_tbl_ch1_13[rtldm->swing_idx_cck][1]);
292 rtl_write_byte(rtlpriv, 0xa24,
293 cck_tbl_ch1_13[rtldm->swing_idx_cck][2]);
294 rtl_write_byte(rtlpriv, 0xa25,
295 cck_tbl_ch1_13[rtldm->swing_idx_cck][3]);
296 rtl_write_byte(rtlpriv, 0xa26,
297 cck_tbl_ch1_13[rtldm->swing_idx_cck][4]);
298 rtl_write_byte(rtlpriv, 0xa27,
299 cck_tbl_ch1_13[rtldm->swing_idx_cck][5]);
300 rtl_write_byte(rtlpriv, 0xa28,
301 cck_tbl_ch1_13[rtldm->swing_idx_cck][6]);
302 rtl_write_byte(rtlpriv, 0xa29,
303 cck_tbl_ch1_13[rtldm->swing_idx_cck][7]);
304 } else {
305 rtl_write_byte(rtlpriv, 0xa22,
306 cck_tbl_ch14[rtldm->swing_idx_cck][0]);
307 rtl_write_byte(rtlpriv, 0xa23,
308 cck_tbl_ch14[rtldm->swing_idx_cck][1]);
309 rtl_write_byte(rtlpriv, 0xa24,
310 cck_tbl_ch14[rtldm->swing_idx_cck][2]);
311 rtl_write_byte(rtlpriv, 0xa25,
312 cck_tbl_ch14[rtldm->swing_idx_cck][3]);
313 rtl_write_byte(rtlpriv, 0xa26,
314 cck_tbl_ch14[rtldm->swing_idx_cck][4]);
315 rtl_write_byte(rtlpriv, 0xa27,
316 cck_tbl_ch14[rtldm->swing_idx_cck][5]);
317 rtl_write_byte(rtlpriv, 0xa28,
318 cck_tbl_ch14[rtldm->swing_idx_cck][6]);
319 rtl_write_byte(rtlpriv, 0xa29,
320 cck_tbl_ch14[rtldm->swing_idx_cck][7]);
321 }
322
323 if (rfpath == RF90_PATH_A) {
324 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath],
325 rfpath, rtlphy->iqk_matrix
326 [channel_mapped_index].
327 value[0][0],
328 rtlphy->iqk_matrix
329 [channel_mapped_index].
330 value[0][1]);
331 } else if (rfpath == RF90_PATH_B) {
332 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath],
333 rfpath, rtlphy->iqk_matrix
334 [channel_mapped_index].
335 value[0][4],
336 rtlphy->iqk_matrix
337 [channel_mapped_index].
338 value[0][5]);
339 }
340 } else {
341 return;
342 }
343 }
344
345 static u8 rtl88e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
346 {
347 struct rtl_priv *rtlpriv = rtl_priv(hw);
348 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
349 long rssi_val_min = 0;
350
351 if ((dm_dig->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
352 (dm_dig->cur_sta_cstate == DIG_STA_CONNECT)) {
353 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
354 rssi_val_min =
355 (rtlpriv->dm.entry_min_undec_sm_pwdb >
356 rtlpriv->dm.undec_sm_pwdb) ?
357 rtlpriv->dm.undec_sm_pwdb :
358 rtlpriv->dm.entry_min_undec_sm_pwdb;
359 else
360 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
361 } else if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT ||
362 dm_dig->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) {
363 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
364 } else if (dm_dig->curmultista_cstate ==
365 DIG_MULTISTA_CONNECT) {
366 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
367 }
368
369 return (u8)rssi_val_min;
370 }
371
372 static void rtl88e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
373 {
374 u32 ret_value;
375 struct rtl_priv *rtlpriv = rtl_priv(hw);
376 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
377
378 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1);
379 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1);
380
381 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
382 falsealm_cnt->cnt_fast_fsync_fail = (ret_value&0xffff);
383 falsealm_cnt->cnt_sb_search_fail = ((ret_value&0xffff0000)>>16);
384
385 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
386 falsealm_cnt->cnt_ofdm_cca = (ret_value&0xffff);
387 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
388
389 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
390 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
391 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
392
393 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
394 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
395 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
396 falsealm_cnt->cnt_rate_illegal +
397 falsealm_cnt->cnt_crc8_fail +
398 falsealm_cnt->cnt_mcs_fail +
399 falsealm_cnt->cnt_fast_fsync_fail +
400 falsealm_cnt->cnt_sb_search_fail;
401
402 ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD);
403 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
404 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
405
406 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1);
407 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
408
409 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
410 falsealm_cnt->cnt_cck_fail = ret_value;
411
412 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
413 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
414
415 ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD);
416 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
417 ((ret_value&0xFF00)>>8);
418
419 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_fast_fsync_fail +
420 falsealm_cnt->cnt_sb_search_fail +
421 falsealm_cnt->cnt_parity_fail +
422 falsealm_cnt->cnt_rate_illegal +
423 falsealm_cnt->cnt_crc8_fail +
424 falsealm_cnt->cnt_mcs_fail +
425 falsealm_cnt->cnt_cck_fail);
426 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
427 falsealm_cnt->cnt_cck_cca;
428
429 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1);
430 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0);
431 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1);
432 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0);
433 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
434 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
435 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0);
436 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2);
437 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0);
438 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2);
439
440 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
441 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
442 falsealm_cnt->cnt_parity_fail,
443 falsealm_cnt->cnt_rate_illegal,
444 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
445
446 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
447 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
448 falsealm_cnt->cnt_ofdm_fail,
449 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
450 }
451
452 static void rtl88e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
453 {
454 struct rtl_priv *rtlpriv = rtl_priv(hw);
455 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
456 u8 cur_cck_cca_thresh;
457
458 if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) {
459 dm_dig->rssi_val_min = rtl88e_dm_initial_gain_min_pwdb(hw);
460 if (dm_dig->rssi_val_min > 25) {
461 cur_cck_cca_thresh = 0xcd;
462 } else if ((dm_dig->rssi_val_min <= 25) &&
463 (dm_dig->rssi_val_min > 10)) {
464 cur_cck_cca_thresh = 0x83;
465 } else {
466 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
467 cur_cck_cca_thresh = 0x83;
468 else
469 cur_cck_cca_thresh = 0x40;
470 }
471
472 } else {
473 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
474 cur_cck_cca_thresh = 0x83;
475 else
476 cur_cck_cca_thresh = 0x40;
477 }
478
479 if (dm_dig->cur_cck_cca_thres != cur_cck_cca_thresh)
480 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
481
482 dm_dig->cur_cck_cca_thres = cur_cck_cca_thresh;
483 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
484 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
485 "CCK cca thresh hold =%x\n", dm_dig->cur_cck_cca_thres);
486 }
487
488 static void rtl88e_dm_dig(struct ieee80211_hw *hw)
489 {
490 struct rtl_priv *rtlpriv = rtl_priv(hw);
491 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
492 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
493 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
494 u8 dig_dynamic_min, dig_maxofmin;
495 bool bfirstconnect;
496 u8 dm_dig_max, dm_dig_min;
497 u8 current_igi = dm_dig->cur_igvalue;
498
499 if (rtlpriv->dm.dm_initialgain_enable == false)
500 return;
501 if (dm_dig->dig_enable_flag == false)
502 return;
503 if (mac->act_scanning == true)
504 return;
505
506 if (mac->link_state >= MAC80211_LINKED)
507 dm_dig->cur_sta_cstate = DIG_STA_CONNECT;
508 else
509 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT;
510 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
511 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
512 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT;
513
514 dm_dig_max = DM_DIG_MAX;
515 dm_dig_min = DM_DIG_MIN;
516 dig_maxofmin = DM_DIG_MAX_AP;
517 dig_dynamic_min = dm_dig->dig_min_0;
518 bfirstconnect = ((mac->link_state >= MAC80211_LINKED) ? true : false) &&
519 !dm_dig->media_connect_0;
520
521 dm_dig->rssi_val_min =
522 rtl88e_dm_initial_gain_min_pwdb(hw);
523
524 if (mac->link_state >= MAC80211_LINKED) {
525 if ((dm_dig->rssi_val_min + 20) > dm_dig_max)
526 dm_dig->rx_gain_max = dm_dig_max;
527 else if ((dm_dig->rssi_val_min + 20) < dm_dig_min)
528 dm_dig->rx_gain_max = dm_dig_min;
529 else
530 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 20;
531
532 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
533 dig_dynamic_min = dm_dig->antdiv_rssi_max;
534 } else {
535 if (dm_dig->rssi_val_min < dm_dig_min)
536 dig_dynamic_min = dm_dig_min;
537 else if (dm_dig->rssi_val_min < dig_maxofmin)
538 dig_dynamic_min = dig_maxofmin;
539 else
540 dig_dynamic_min = dm_dig->rssi_val_min;
541 }
542 } else {
543 dm_dig->rx_gain_max = dm_dig_max;
544 dig_dynamic_min = dm_dig_min;
545 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
546 }
547
548 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
549 dm_dig->large_fa_hit++;
550 if (dm_dig->forbidden_igi < current_igi) {
551 dm_dig->forbidden_igi = current_igi;
552 dm_dig->large_fa_hit = 1;
553 }
554
555 if (dm_dig->large_fa_hit >= 3) {
556 if ((dm_dig->forbidden_igi + 1) >
557 dm_dig->rx_gain_max)
558 dm_dig->rx_gain_min =
559 dm_dig->rx_gain_max;
560 else
561 dm_dig->rx_gain_min =
562 dm_dig->forbidden_igi + 1;
563 dm_dig->recover_cnt = 3600;
564 }
565 } else {
566 if (dm_dig->recover_cnt != 0) {
567 dm_dig->recover_cnt--;
568 } else {
569 if (dm_dig->large_fa_hit == 0) {
570 if ((dm_dig->forbidden_igi - 1) <
571 dig_dynamic_min) {
572 dm_dig->forbidden_igi = dig_dynamic_min;
573 dm_dig->rx_gain_min = dig_dynamic_min;
574 } else {
575 dm_dig->forbidden_igi--;
576 dm_dig->rx_gain_min =
577 dm_dig->forbidden_igi + 1;
578 }
579 } else if (dm_dig->large_fa_hit == 3) {
580 dm_dig->large_fa_hit = 0;
581 }
582 }
583 }
584
585 if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) {
586 if (bfirstconnect) {
587 current_igi = dm_dig->rssi_val_min;
588 } else {
589 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
590 current_igi += 2;
591 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
592 current_igi++;
593 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
594 current_igi--;
595 }
596 } else {
597 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
598 current_igi += 2;
599 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
600 current_igi++;
601 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
602 current_igi--;
603 }
604
605 if (current_igi > DM_DIG_FA_UPPER)
606 current_igi = DM_DIG_FA_UPPER;
607 else if (current_igi < DM_DIG_FA_LOWER)
608 current_igi = DM_DIG_FA_LOWER;
609
610 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
611 current_igi = DM_DIG_FA_UPPER;
612
613 dm_dig->cur_igvalue = current_igi;
614 rtl88e_dm_write_dig(hw);
615 dm_dig->media_connect_0 =
616 ((mac->link_state >= MAC80211_LINKED) ? true : false);
617 dm_dig->dig_min_0 = dig_dynamic_min;
618
619 rtl88e_dm_cck_packet_detection_thresh(hw);
620 }
621
622 static void rtl88e_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
623 {
624 struct rtl_priv *rtlpriv = rtl_priv(hw);
625
626 rtlpriv->dm.dynamic_txpower_enable = false;
627
628 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
629 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
630 }
631
632 static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
633 {
634 struct rtl_priv *rtlpriv = rtl_priv(hw);
635 struct rtl_phy *rtlphy = &rtlpriv->phy;
636 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
637 long undec_sm_pwdb;
638
639 if (!rtlpriv->dm.dynamic_txpower_enable)
640 return;
641
642 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
643 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
644 return;
645 }
646
647 if ((mac->link_state < MAC80211_LINKED) &&
648 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
649 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
650 "Not connected to any\n");
651
652 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
653
654 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
655 return;
656 }
657
658 if (mac->link_state >= MAC80211_LINKED) {
659 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
660 undec_sm_pwdb =
661 rtlpriv->dm.entry_min_undec_sm_pwdb;
662 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
663 "AP Client PWDB = 0x%lx\n",
664 undec_sm_pwdb);
665 } else {
666 undec_sm_pwdb =
667 rtlpriv->dm.undec_sm_pwdb;
668 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
669 "STA Default Port PWDB = 0x%lx\n",
670 undec_sm_pwdb);
671 }
672 } else {
673 undec_sm_pwdb =
674 rtlpriv->dm.entry_min_undec_sm_pwdb;
675
676 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
677 "AP Ext Port PWDB = 0x%lx\n",
678 undec_sm_pwdb);
679 }
680
681 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
682 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
683 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
684 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x0)\n");
685 } else if ((undec_sm_pwdb <
686 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
687 (undec_sm_pwdb >=
688 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
689 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
690 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
691 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x10)\n");
692 } else if (undec_sm_pwdb <
693 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
694 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
695 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
696 "TXHIGHPWRLEVEL_NORMAL\n");
697 }
698
699 if ((rtlpriv->dm.dynamic_txhighpower_lvl !=
700 rtlpriv->dm.last_dtp_lvl)) {
701 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
702 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
703 rtlphy->current_channel);
704 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
705 }
706
707 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
708 }
709
710 void rtl88e_dm_write_dig(struct ieee80211_hw *hw)
711 {
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
714
715 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
716 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
717 dm_dig->cur_igvalue, dm_dig->pre_igvalue,
718 dm_dig->back_val);
719
720 if (dm_dig->cur_igvalue > 0x3f)
721 dm_dig->cur_igvalue = 0x3f;
722 if (dm_dig->pre_igvalue != dm_dig->cur_igvalue) {
723 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
724 dm_dig->cur_igvalue);
725
726 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
727 }
728 }
729
730 static void rtl88e_dm_pwdb_monitor(struct ieee80211_hw *hw)
731 {
732 struct rtl_priv *rtlpriv = rtl_priv(hw);
733 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
734 struct rtl_sta_info *drv_priv;
735 static u64 last_record_txok_cnt;
736 static u64 last_record_rxok_cnt;
737 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
738
739 if (rtlhal->oem_id == RT_CID_819X_HP) {
740 u64 cur_txok_cnt = 0;
741 u64 cur_rxok_cnt = 0;
742 cur_txok_cnt = rtlpriv->stats.txbytesunicast -
743 last_record_txok_cnt;
744 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast -
745 last_record_rxok_cnt;
746 last_record_txok_cnt = cur_txok_cnt;
747 last_record_rxok_cnt = cur_rxok_cnt;
748
749 if (cur_rxok_cnt > (cur_txok_cnt * 6))
750 rtl_write_dword(rtlpriv, REG_ARFR0, 0x8f015);
751 else
752 rtl_write_dword(rtlpriv, REG_ARFR0, 0xff015);
753 }
754
755 /* AP & ADHOC & MESH */
756 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
757 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
758 if (drv_priv->rssi_stat.undec_sm_pwdb <
759 tmp_entry_min_pwdb)
760 tmp_entry_min_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
761 if (drv_priv->rssi_stat.undec_sm_pwdb >
762 tmp_entry_max_pwdb)
763 tmp_entry_max_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
764 }
765 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
766
767 /* If associated entry is found */
768 if (tmp_entry_max_pwdb != 0) {
769 rtlpriv->dm.entry_max_undec_sm_pwdb = tmp_entry_max_pwdb;
770 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMaxPWDB = 0x%lx(%ld)\n",
771 tmp_entry_max_pwdb, tmp_entry_max_pwdb);
772 } else {
773 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
774 }
775 /* If associated entry is found */
776 if (tmp_entry_min_pwdb != 0xff) {
777 rtlpriv->dm.entry_min_undec_sm_pwdb = tmp_entry_min_pwdb;
778 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMinPWDB = 0x%lx(%ld)\n",
779 tmp_entry_min_pwdb, tmp_entry_min_pwdb);
780 } else {
781 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
782 }
783 /* Indicate Rx signal strength to FW. */
784 if (rtlpriv->dm.useramask) {
785 u8 h2c_parameter[3] = { 0 };
786
787 h2c_parameter[2] = (u8)(rtlpriv->dm.undec_sm_pwdb & 0xFF);
788 h2c_parameter[0] = 0x20;
789 } else {
790 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb);
791 }
792 }
793
794 void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw)
795 {
796 struct rtl_priv *rtlpriv = rtl_priv(hw);
797
798 rtlpriv->dm.current_turbo_edca = false;
799 rtlpriv->dm.is_any_nonbepkts = false;
800 rtlpriv->dm.is_cur_rdlstate = false;
801 }
802
803 static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw)
804 {
805 struct rtl_priv *rtlpriv = rtl_priv(hw);
806 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
807 static u64 last_txok_cnt;
808 static u64 last_rxok_cnt;
809 static u32 last_bt_edca_ul;
810 static u32 last_bt_edca_dl;
811 u64 cur_txok_cnt = 0;
812 u64 cur_rxok_cnt = 0;
813 u32 edca_be_ul = 0x5ea42b;
814 u32 edca_be_dl = 0x5ea42b;
815 bool bt_change_edca = false;
816
817 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
818 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
819 rtlpriv->dm.current_turbo_edca = false;
820 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
821 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
822 }
823
824 if (rtlpriv->btcoexist.bt_edca_ul != 0) {
825 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
826 bt_change_edca = true;
827 }
828
829 if (rtlpriv->btcoexist.bt_edca_dl != 0) {
830 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
831 bt_change_edca = true;
832 }
833
834 if (mac->link_state != MAC80211_LINKED) {
835 rtlpriv->dm.current_turbo_edca = false;
836 return;
837 }
838 if ((bt_change_edca) ||
839 ((!rtlpriv->dm.is_any_nonbepkts) &&
840 (!rtlpriv->dm.disable_framebursting))) {
841
842 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
843 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
844
845 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
846 if (!rtlpriv->dm.is_cur_rdlstate ||
847 !rtlpriv->dm.current_turbo_edca) {
848 rtl_write_dword(rtlpriv,
849 REG_EDCA_BE_PARAM,
850 edca_be_dl);
851 rtlpriv->dm.is_cur_rdlstate = true;
852 }
853 } else {
854 if (rtlpriv->dm.is_cur_rdlstate ||
855 !rtlpriv->dm.current_turbo_edca) {
856 rtl_write_dword(rtlpriv,
857 REG_EDCA_BE_PARAM,
858 edca_be_ul);
859 rtlpriv->dm.is_cur_rdlstate = false;
860 }
861 }
862 rtlpriv->dm.current_turbo_edca = true;
863 } else {
864 if (rtlpriv->dm.current_turbo_edca) {
865 u8 tmp = AC0_BE;
866
867 rtlpriv->cfg->ops->set_hw_reg(hw,
868 HW_VAR_AC_PARAM,
869 &tmp);
870 rtlpriv->dm.current_turbo_edca = false;
871 }
872 }
873
874 rtlpriv->dm.is_any_nonbepkts = false;
875 last_txok_cnt = rtlpriv->stats.txbytesunicast;
876 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
877 }
878
879 static void dm_txpower_track_cb_therm(struct ieee80211_hw *hw)
880 {
881 struct rtl_priv *rtlpriv = rtl_priv(hw);
882 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
883 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
884 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
885 u8 thermalvalue = 0, delta, delta_lck, delta_iqk, offset;
886 u8 thermalvalue_avg_count = 0;
887 u32 thermalvalue_avg = 0;
888 long ele_d, temp_cck;
889 char ofdm_index[2], cck_index = 0,
890 ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
891 int i = 0;
892 /*bool is2t = false;*/
893
894 u8 ofdm_min_index = 6, rf = 1;
895 /*u8 index_for_channel;*/
896 enum _power_dec_inc {power_dec, power_inc};
897
898 /*0.1 the following TWO tables decide the
899 *final index of OFDM/CCK swing table
900 */
901 char delta_swing_table_idx[2][15] = {
902 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11},
903 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10}
904 };
905 u8 thermal_threshold[2][15] = {
906 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27},
907 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
908 };
909
910 /*Initilization (7 steps in total) */
911 rtlpriv->dm.txpower_trackinginit = true;
912 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
913 "dm_txpower_track_cb_therm\n");
914
915 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER,
916 0xfc00);
917 if (!thermalvalue)
918 return;
919 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
920 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
921 thermalvalue, rtlpriv->dm.thermalvalue,
922 rtlefuse->eeprom_thermalmeter);
923
924 /*1. Query OFDM Default Setting: Path A*/
925 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) &
926 MASKOFDM_D;
927 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
928 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
929 ofdm_index_old[0] = (u8)i;
930 rtldm->swing_idx_ofdm_base[RF90_PATH_A] = (u8)i;
931 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
932 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index = 0x%x\n",
933 ROFDM0_XATXIQIMBALANCE,
934 ele_d, ofdm_index_old[0]);
935 break;
936 }
937 }
938
939 /*2.Query CCK default setting From 0xa24*/
940 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
941 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
942 if (rtlpriv->dm.cck_inch14) {
943 if (memcmp(&temp_cck, &cck_tbl_ch14[i][2], 4) == 0) {
944 cck_index_old = (u8)i;
945 rtldm->swing_idx_cck_base = (u8)i;
946 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
947 DBG_LOUD,
948 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch 14 %d\n",
949 RCCK0_TXFILTER2, temp_cck,
950 cck_index_old,
951 rtlpriv->dm.cck_inch14);
952 break;
953 }
954 } else {
955 if (memcmp(&temp_cck, &cck_tbl_ch1_13[i][2], 4) == 0) {
956 cck_index_old = (u8)i;
957 rtldm->swing_idx_cck_base = (u8)i;
958 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
959 DBG_LOUD,
960 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
961 RCCK0_TXFILTER2, temp_cck,
962 cck_index_old,
963 rtlpriv->dm.cck_inch14);
964 break;
965 }
966 }
967 }
968
969 /*3 Initialize ThermalValues of RFCalibrateInfo*/
970 if (!rtldm->thermalvalue) {
971 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter;
972 rtlpriv->dm.thermalvalue_lck = thermalvalue;
973 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
974 for (i = 0; i < rf; i++)
975 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
976 rtlpriv->dm.cck_index = cck_index_old;
977 }
978
979 /*4 Calculate average thermal meter*/
980 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermalvalue;
981 rtldm->thermalvalue_avg_index++;
982 if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_88E)
983 rtldm->thermalvalue_avg_index = 0;
984
985 for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
986 if (rtldm->thermalvalue_avg[i]) {
987 thermalvalue_avg += rtldm->thermalvalue_avg[i];
988 thermalvalue_avg_count++;
989 }
990 }
991
992 if (thermalvalue_avg_count)
993 thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count);
994
995 /* 5 Calculate delta, delta_LCK, delta_IQK.*/
996 if (rtlhal->reloadtxpowerindex) {
997 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
998 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
999 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1000 rtlhal->reloadtxpowerindex = false;
1001 rtlpriv->dm.done_txpower = false;
1002 } else if (rtlpriv->dm.done_txpower) {
1003 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
1004 (thermalvalue - rtlpriv->dm.thermalvalue) :
1005 (rtlpriv->dm.thermalvalue - thermalvalue);
1006 } else {
1007 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1008 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1009 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1010 }
1011 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
1012 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
1013 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
1014 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
1015 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
1016 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
1017
1018 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1019 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
1020 thermalvalue, rtlpriv->dm.thermalvalue,
1021 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
1022 delta_iqk);
1023 /* 6 If necessary, do LCK.*/
1024 if (delta_lck >= 8) {
1025 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1026 rtl88e_phy_lc_calibrate(hw);
1027 }
1028
1029 /* 7 If necessary, move the index of
1030 * swing table to adjust Tx power.
1031 */
1032 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
1033 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1034 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1035 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1036
1037 /* 7.1 Get the final CCK_index and OFDM_index for each
1038 * swing table.
1039 */
1040 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
1041 CAL_SWING_OFF(offset, power_inc, INDEX_MAPPING_NUM,
1042 delta);
1043 for (i = 0; i < rf; i++)
1044 ofdm_index[i] =
1045 rtldm->ofdm_index[i] +
1046 delta_swing_table_idx[power_inc][offset];
1047 cck_index = rtldm->cck_index +
1048 delta_swing_table_idx[power_inc][offset];
1049 } else {
1050 CAL_SWING_OFF(offset, power_dec, INDEX_MAPPING_NUM,
1051 delta);
1052 for (i = 0; i < rf; i++)
1053 ofdm_index[i] =
1054 rtldm->ofdm_index[i] +
1055 delta_swing_table_idx[power_dec][offset];
1056 cck_index = rtldm->cck_index +
1057 delta_swing_table_idx[power_dec][offset];
1058 }
1059
1060 /* 7.2 Handle boundary conditions of index.*/
1061 for (i = 0; i < rf; i++) {
1062 if (ofdm_index[i] > OFDM_TABLE_SIZE-1)
1063 ofdm_index[i] = OFDM_TABLE_SIZE-1;
1064 else if (rtldm->ofdm_index[i] < ofdm_min_index)
1065 ofdm_index[i] = ofdm_min_index;
1066 }
1067
1068 if (cck_index > CCK_TABLE_SIZE-1)
1069 cck_index = CCK_TABLE_SIZE-1;
1070 else if (cck_index < 0)
1071 cck_index = 0;
1072
1073 /*7.3Configure the Swing Table to adjust Tx Power.*/
1074 if (rtlpriv->dm.txpower_track_control) {
1075 rtldm->done_txpower = true;
1076 rtldm->swing_idx_ofdm[RF90_PATH_A] =
1077 (u8)ofdm_index[RF90_PATH_A];
1078 rtldm->swing_idx_cck = cck_index;
1079 if (rtldm->swing_idx_ofdm_cur !=
1080 rtldm->swing_idx_ofdm[0]) {
1081 rtldm->swing_idx_ofdm_cur =
1082 rtldm->swing_idx_ofdm[0];
1083 rtldm->swing_flag_ofdm = true;
1084 }
1085
1086 if (rtldm->swing_idx_cck_cur != rtldm->swing_idx_cck) {
1087 rtldm->swing_idx_cck_cur = rtldm->swing_idx_cck;
1088 rtldm->swing_flag_cck = true;
1089 }
1090
1091 dm_tx_pwr_track_set_pwr(hw, TXAGC, 0, 0);
1092 }
1093 }
1094
1095 if (delta_iqk >= 8) {
1096 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1097 rtl88e_phy_iq_calibrate(hw, false);
1098 }
1099
1100 if (rtldm->txpower_track_control)
1101 rtldm->thermalvalue = thermalvalue;
1102 rtldm->txpowercount = 0;
1103 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n");
1104 }
1105
1106 static void rtl88e_dm_init_txpower_tracking(struct ieee80211_hw *hw)
1107 {
1108 struct rtl_priv *rtlpriv = rtl_priv(hw);
1109
1110 rtlpriv->dm.txpower_tracking = true;
1111 rtlpriv->dm.txpower_trackinginit = false;
1112 rtlpriv->dm.txpowercount = 0;
1113 rtlpriv->dm.txpower_track_control = true;
1114
1115 rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A] = 12;
1116 rtlpriv->dm.swing_idx_ofdm_cur = 12;
1117 rtlpriv->dm.swing_flag_ofdm = false;
1118 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1119 "rtlpriv->dm.txpower_tracking = %d\n",
1120 rtlpriv->dm.txpower_tracking);
1121 }
1122
1123 void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1124 {
1125 struct rtl_priv *rtlpriv = rtl_priv(hw);
1126
1127 if (!rtlpriv->dm.txpower_tracking)
1128 return;
1129
1130 if (!rtlpriv->dm.tm_trigger) {
1131 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16),
1132 0x03);
1133 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1134 "Trigger 88E Thermal Meter!!\n");
1135 rtlpriv->dm.tm_trigger = 1;
1136 return;
1137 } else {
1138 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1139 "Schedule TxPowerTracking !!\n");
1140 dm_txpower_track_cb_therm(hw);
1141 rtlpriv->dm.tm_trigger = 0;
1142 }
1143 }
1144
1145 void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1146 {
1147 struct rtl_priv *rtlpriv = rtl_priv(hw);
1148 struct rate_adaptive *p_ra = &rtlpriv->ra;
1149
1150 p_ra->ratr_state = DM_RATR_STA_INIT;
1151 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1152
1153 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1154 rtlpriv->dm.useramask = true;
1155 else
1156 rtlpriv->dm.useramask = false;
1157 }
1158
1159 static void rtl88e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1160 {
1161 struct rtl_priv *rtlpriv = rtl_priv(hw);
1162 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1163 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1164 struct rate_adaptive *p_ra = &rtlpriv->ra;
1165 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1166 struct ieee80211_sta *sta = NULL;
1167
1168 if (is_hal_stop(rtlhal)) {
1169 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1170 "driver is going to unload\n");
1171 return;
1172 }
1173
1174 if (!rtlpriv->dm.useramask) {
1175 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1176 "driver does not control rate adaptive mask\n");
1177 return;
1178 }
1179
1180 if (mac->link_state == MAC80211_LINKED &&
1181 mac->opmode == NL80211_IFTYPE_STATION) {
1182 switch (p_ra->pre_ratr_state) {
1183 case DM_RATR_STA_HIGH:
1184 high_rssithresh_for_ra = 50;
1185 low_rssithresh_for_ra = 20;
1186 break;
1187 case DM_RATR_STA_MIDDLE:
1188 high_rssithresh_for_ra = 55;
1189 low_rssithresh_for_ra = 20;
1190 break;
1191 case DM_RATR_STA_LOW:
1192 high_rssithresh_for_ra = 50;
1193 low_rssithresh_for_ra = 25;
1194 break;
1195 default:
1196 high_rssithresh_for_ra = 50;
1197 low_rssithresh_for_ra = 20;
1198 break;
1199 }
1200
1201 if (rtlpriv->dm.undec_sm_pwdb >
1202 (long)high_rssithresh_for_ra)
1203 p_ra->ratr_state = DM_RATR_STA_HIGH;
1204 else if (rtlpriv->dm.undec_sm_pwdb >
1205 (long)low_rssithresh_for_ra)
1206 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1207 else
1208 p_ra->ratr_state = DM_RATR_STA_LOW;
1209
1210 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1211 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1212 "RSSI = %ld\n",
1213 rtlpriv->dm.undec_sm_pwdb);
1214 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1215 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1216 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1217 "PreState = %d, CurState = %d\n",
1218 p_ra->pre_ratr_state, p_ra->ratr_state);
1219
1220 rcu_read_lock();
1221 sta = rtl_find_sta(hw, mac->bssid);
1222 if (sta)
1223 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1224 p_ra->ratr_state);
1225 rcu_read_unlock();
1226
1227 p_ra->pre_ratr_state = p_ra->ratr_state;
1228 }
1229 }
1230 }
1231
1232 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1233 {
1234 struct rtl_priv *rtlpriv = rtl_priv(hw);
1235 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1236
1237 dm_pstable->pre_ccastate = CCA_MAX;
1238 dm_pstable->cur_ccasate = CCA_MAX;
1239 dm_pstable->pre_rfstate = RF_MAX;
1240 dm_pstable->cur_rfstate = RF_MAX;
1241 dm_pstable->rssi_val_min = 0;
1242 }
1243
1244 static void rtl88e_dm_update_rx_idle_ant(struct ieee80211_hw *hw,
1245 u8 ant)
1246 {
1247 struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1249 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1250 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1251 u32 default_ant, optional_ant;
1252
1253 if (pfat_table->rx_idle_ant != ant) {
1254 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1255 "need to update rx idle ant\n");
1256 if (ant == MAIN_ANT) {
1257 default_ant =
1258 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1259 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1260 optional_ant =
1261 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1262 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1263 } else {
1264 default_ant =
1265 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1266 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1267 optional_ant =
1268 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1269 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1270 }
1271
1272 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1273 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1274 BIT(5) | BIT(4) | BIT(3), default_ant);
1275 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1276 BIT(8) | BIT(7) | BIT(6), optional_ant);
1277 rtl_set_bbreg(hw, DM_REG_ANTSEL_CTRL_11N,
1278 BIT(14) | BIT(13) | BIT(12),
1279 default_ant);
1280 rtl_set_bbreg(hw, DM_REG_RESP_TX_11N,
1281 BIT(6) | BIT(7), default_ant);
1282 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1283 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1284 BIT(5) | BIT(4) | BIT(3), default_ant);
1285 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1286 BIT(8) | BIT(7) | BIT(6), optional_ant);
1287 }
1288 }
1289 pfat_table->rx_idle_ant = ant;
1290 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RxIdleAnt %s\n",
1291 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT"));
1292 }
1293
1294 static void rtl88e_dm_update_tx_ant(struct ieee80211_hw *hw,
1295 u8 ant, u32 mac_id)
1296 {
1297 struct rtl_priv *rtlpriv = rtl_priv(hw);
1298 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1299 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1300 u8 target_ant;
1301
1302 if (ant == MAIN_ANT)
1303 target_ant = MAIN_ANT_CG_TRX;
1304 else
1305 target_ant = AUX_ANT_CG_TRX;
1306
1307 pfat_table->antsel_a[mac_id] = target_ant & BIT(0);
1308 pfat_table->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1;
1309 pfat_table->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2;
1310 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "txfrominfo target ant %s\n",
1311 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT"));
1312 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "antsel_tr_mux = 3'b%d%d%d\n",
1313 pfat_table->antsel_c[mac_id],
1314 pfat_table->antsel_b[mac_id],
1315 pfat_table->antsel_a[mac_id]);
1316 }
1317
1318 static void rtl88e_dm_rx_hw_antena_div_init(struct ieee80211_hw *hw)
1319 {
1320 u32 value32;
1321
1322 /*MAC Setting*/
1323 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1324 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N,
1325 MASKDWORD, value32 | (BIT(23) | BIT(25)));
1326 /*Pin Setting*/
1327 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1328 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1329 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1);
1330 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1331 /*OFDM Setting*/
1332 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1333 /*CCK Setting*/
1334 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1335 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1336 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1337 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1338 }
1339
1340 static void rtl88e_dm_trx_hw_antenna_div_init(struct ieee80211_hw *hw)
1341 {
1342 u32 value32;
1343
1344 /*MAC Setting*/
1345 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1346 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD,
1347 value32 | (BIT(23) | BIT(25)));
1348 /*Pin Setting*/
1349 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1350 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1351 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1352 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1353 /*OFDM Setting*/
1354 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1355 /*CCK Setting*/
1356 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1357 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1358 /*TX Setting*/
1359 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
1360 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1361 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1362 }
1363
1364 static void rtl88e_dm_fast_training_init(struct ieee80211_hw *hw)
1365 {
1366 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1367 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1368 u32 ant_combination = 2;
1369 u32 value32, i;
1370
1371 for (i = 0; i < 6; i++) {
1372 pfat_table->bssid[i] = 0;
1373 pfat_table->ant_sum[i] = 0;
1374 pfat_table->ant_cnt[i] = 0;
1375 pfat_table->ant_ave[i] = 0;
1376 }
1377 pfat_table->train_idx = 0;
1378 pfat_table->fat_state = FAT_NORMAL_STATE;
1379
1380 /*MAC Setting*/
1381 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1382 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N,
1383 MASKDWORD, value32 | (BIT(23) | BIT(25)));
1384 value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, MASKDWORD);
1385 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1386 MASKDWORD, value32 | (BIT(16) | BIT(17)));
1387 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1388 MASKLWORD, 0);
1389 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N,
1390 MASKDWORD, 0);
1391
1392 /*Pin Setting*/
1393 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1394 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1395 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1396 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1397
1398 /*OFDM Setting*/
1399 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1400 /*antenna mapping table*/
1401 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1);
1402 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2);
1403
1404 /*TX Setting*/
1405 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1);
1406 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1407 BIT(5) | BIT(4) | BIT(3), 0);
1408 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1409 BIT(8) | BIT(7) | BIT(6), 1);
1410 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1411 BIT(2) | BIT(1) | BIT(0), (ant_combination - 1));
1412
1413 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1414 }
1415
1416 static void rtl88e_dm_antenna_div_init(struct ieee80211_hw *hw)
1417 {
1418 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1419
1420 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1421 rtl88e_dm_rx_hw_antena_div_init(hw);
1422 else if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1423 rtl88e_dm_trx_hw_antenna_div_init(hw);
1424 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1425 rtl88e_dm_fast_training_init(hw);
1426
1427 }
1428
1429 void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
1430 u8 *pdesc, u32 mac_id)
1431 {
1432 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1433 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1434 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1435
1436 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1437 (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)) {
1438 SET_TX_DESC_ANTSEL_A(pdesc, pfat_table->antsel_a[mac_id]);
1439 SET_TX_DESC_ANTSEL_B(pdesc, pfat_table->antsel_b[mac_id]);
1440 SET_TX_DESC_ANTSEL_C(pdesc, pfat_table->antsel_c[mac_id]);
1441 }
1442 }
1443
1444 void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
1445 u8 antsel_tr_mux, u32 mac_id,
1446 u32 rx_pwdb_all)
1447 {
1448 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1449 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1450 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1451
1452 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1453 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
1454 pfat_table->main_ant_sum[mac_id] += rx_pwdb_all;
1455 pfat_table->main_ant_cnt[mac_id]++;
1456 } else {
1457 pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all;
1458 pfat_table->aux_ant_cnt[mac_id]++;
1459 }
1460 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1461 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
1462 pfat_table->main_ant_sum[mac_id] += rx_pwdb_all;
1463 pfat_table->main_ant_cnt[mac_id]++;
1464 } else {
1465 pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all;
1466 pfat_table->aux_ant_cnt[mac_id]++;
1467 }
1468 }
1469 }
1470
1471 static void rtl88e_dm_hw_ant_div(struct ieee80211_hw *hw)
1472 {
1473 struct rtl_priv *rtlpriv = rtl_priv(hw);
1474 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1475 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1476 struct rtl_sta_info *drv_priv;
1477 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1478 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
1479 u32 i, min_rssi = 0xff, ant_div_max_rssi = 0;
1480 u32 max_rssi = 0, local_min_rssi, local_max_rssi;
1481 u32 main_rssi, aux_rssi;
1482 u8 rx_idle_ant = 0, target_ant = 7;
1483
1484 /*for sta its self*/
1485 i = 0;
1486 main_rssi = (pfat_table->main_ant_cnt[i] != 0) ?
1487 (pfat_table->main_ant_sum[i] / pfat_table->main_ant_cnt[i]) : 0;
1488 aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ?
1489 (pfat_table->aux_ant_sum[i] / pfat_table->aux_ant_cnt[i]) : 0;
1490 target_ant = (main_rssi == aux_rssi) ?
1491 pfat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ?
1492 MAIN_ANT : AUX_ANT);
1493 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1494 "main_ant_sum %d main_ant_cnt %d\n",
1495 pfat_table->main_ant_sum[i],
1496 pfat_table->main_ant_cnt[i]);
1497 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1498 "aux_ant_sum %d aux_ant_cnt %d\n",
1499 pfat_table->aux_ant_sum[i], pfat_table->aux_ant_cnt[i]);
1500 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "main_rssi %d aux_rssi%d\n",
1501 main_rssi, aux_rssi);
1502 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
1503 if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40))
1504 ant_div_max_rssi = local_max_rssi;
1505 if (local_max_rssi > max_rssi)
1506 max_rssi = local_max_rssi;
1507
1508 if ((pfat_table->rx_idle_ant == MAIN_ANT) && (main_rssi == 0))
1509 main_rssi = aux_rssi;
1510 else if ((pfat_table->rx_idle_ant == AUX_ANT) && (aux_rssi == 0))
1511 aux_rssi = main_rssi;
1512
1513 local_min_rssi = (main_rssi > aux_rssi) ? aux_rssi : main_rssi;
1514 if (local_min_rssi < min_rssi) {
1515 min_rssi = local_min_rssi;
1516 rx_idle_ant = target_ant;
1517 }
1518 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1519 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1520
1521 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1522 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) {
1523 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1524 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1525 i++;
1526 main_rssi = (pfat_table->main_ant_cnt[i] != 0) ?
1527 (pfat_table->main_ant_sum[i] /
1528 pfat_table->main_ant_cnt[i]) : 0;
1529 aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ?
1530 (pfat_table->aux_ant_sum[i] /
1531 pfat_table->aux_ant_cnt[i]) : 0;
1532 target_ant = (main_rssi == aux_rssi) ?
1533 pfat_table->rx_idle_ant : ((main_rssi >=
1534 aux_rssi) ? MAIN_ANT : AUX_ANT);
1535
1536 local_max_rssi = (main_rssi > aux_rssi) ?
1537 main_rssi : aux_rssi;
1538 if ((local_max_rssi > ant_div_max_rssi) &&
1539 (local_max_rssi < 40))
1540 ant_div_max_rssi = local_max_rssi;
1541 if (local_max_rssi > max_rssi)
1542 max_rssi = local_max_rssi;
1543
1544 if ((pfat_table->rx_idle_ant == MAIN_ANT) &&
1545 (main_rssi == 0))
1546 main_rssi = aux_rssi;
1547 else if ((pfat_table->rx_idle_ant == AUX_ANT) &&
1548 (aux_rssi == 0))
1549 aux_rssi = main_rssi;
1550
1551 local_min_rssi = (main_rssi > aux_rssi) ?
1552 aux_rssi : main_rssi;
1553 if (local_min_rssi < min_rssi) {
1554 min_rssi = local_min_rssi;
1555 rx_idle_ant = target_ant;
1556 }
1557 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1558 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1559 }
1560 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1561 }
1562
1563 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1564 pfat_table->main_ant_sum[i] = 0;
1565 pfat_table->aux_ant_sum[i] = 0;
1566 pfat_table->main_ant_cnt[i] = 0;
1567 pfat_table->aux_ant_cnt[i] = 0;
1568 }
1569
1570 rtl88e_dm_update_rx_idle_ant(hw, rx_idle_ant);
1571
1572 dm_dig->antdiv_rssi_max = ant_div_max_rssi;
1573 dm_dig->rssi_max = max_rssi;
1574 }
1575
1576 static void rtl88e_set_next_mac_address_target(struct ieee80211_hw *hw)
1577 {
1578 struct rtl_priv *rtlpriv = rtl_priv(hw);
1579 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1580 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1581 struct rtl_sta_info *drv_priv;
1582 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1583 u32 value32, i, j = 0;
1584
1585 if (mac->link_state >= MAC80211_LINKED) {
1586 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1587 if ((pfat_table->train_idx + 1) == ASSOCIATE_ENTRY_NUM)
1588 pfat_table->train_idx = 0;
1589 else
1590 pfat_table->train_idx++;
1591
1592 if (pfat_table->train_idx == 0) {
1593 value32 = (mac->mac_addr[5] << 8) |
1594 mac->mac_addr[4];
1595 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1596 MASKLWORD, value32);
1597
1598 value32 = (mac->mac_addr[3] << 24) |
1599 (mac->mac_addr[2] << 16) |
1600 (mac->mac_addr[1] << 8) |
1601 mac->mac_addr[0];
1602 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N,
1603 MASKDWORD, value32);
1604 break;
1605 }
1606
1607 if (rtlpriv->mac80211.opmode !=
1608 NL80211_IFTYPE_STATION) {
1609 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1610 list_for_each_entry(drv_priv,
1611 &rtlpriv->entry_list, list) {
1612 j++;
1613 if (j != pfat_table->train_idx)
1614 continue;
1615
1616 value32 = (drv_priv->mac_addr[5] << 8) |
1617 drv_priv->mac_addr[4];
1618 rtl_set_bbreg(hw,
1619 DM_REG_ANT_TRAIN_PARA2_11N,
1620 MASKLWORD, value32);
1621
1622 value32 = (drv_priv->mac_addr[3] << 24) |
1623 (drv_priv->mac_addr[2] << 16) |
1624 (drv_priv->mac_addr[1] << 8) |
1625 drv_priv->mac_addr[0];
1626 rtl_set_bbreg(hw,
1627 DM_REG_ANT_TRAIN_PARA1_11N,
1628 MASKDWORD, value32);
1629 break;
1630 }
1631 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1632 /*find entry, break*/
1633 if (j == pfat_table->train_idx)
1634 break;
1635 }
1636 }
1637 }
1638 }
1639
1640 static void rtl88e_dm_fast_ant_training(struct ieee80211_hw *hw)
1641 {
1642 struct rtl_priv *rtlpriv = rtl_priv(hw);
1643 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1644 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1645 u32 i, max_rssi = 0;
1646 u8 target_ant = 2;
1647 bool bpkt_filter_match = false;
1648
1649 if (pfat_table->fat_state == FAT_TRAINING_STATE) {
1650 for (i = 0; i < 7; i++) {
1651 if (pfat_table->ant_cnt[i] == 0) {
1652 pfat_table->ant_ave[i] = 0;
1653 } else {
1654 pfat_table->ant_ave[i] =
1655 pfat_table->ant_sum[i] /
1656 pfat_table->ant_cnt[i];
1657 bpkt_filter_match = true;
1658 }
1659
1660 if (pfat_table->ant_ave[i] > max_rssi) {
1661 max_rssi = pfat_table->ant_ave[i];
1662 target_ant = (u8) i;
1663 }
1664 }
1665
1666 if (bpkt_filter_match == false) {
1667 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1668 BIT(16), 0);
1669 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1670 } else {
1671 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1672 BIT(16), 0);
1673 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) |
1674 BIT(7) | BIT(6), target_ant);
1675 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1676 BIT(21), 1);
1677
1678 pfat_table->antsel_a[pfat_table->train_idx] =
1679 target_ant & BIT(0);
1680 pfat_table->antsel_b[pfat_table->train_idx] =
1681 (target_ant & BIT(1)) >> 1;
1682 pfat_table->antsel_c[pfat_table->train_idx] =
1683 (target_ant & BIT(2)) >> 2;
1684
1685 if (target_ant == 0)
1686 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1687 }
1688
1689 for (i = 0; i < 7; i++) {
1690 pfat_table->ant_sum[i] = 0;
1691 pfat_table->ant_cnt[i] = 0;
1692 }
1693
1694 pfat_table->fat_state = FAT_NORMAL_STATE;
1695 return;
1696 }
1697
1698 if (pfat_table->fat_state == FAT_NORMAL_STATE) {
1699 rtl88e_set_next_mac_address_target(hw);
1700
1701 pfat_table->fat_state = FAT_TRAINING_STATE;
1702 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1);
1703 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1704
1705 mod_timer(&rtlpriv->works.fast_antenna_training_timer,
1706 jiffies + MSECS(RTL_WATCH_DOG_TIME));
1707 }
1708 }
1709
1710 void rtl88e_dm_fast_antenna_training_callback(unsigned long data)
1711 {
1712 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1713
1714 rtl88e_dm_fast_ant_training(hw);
1715 }
1716
1717 static void rtl88e_dm_antenna_diversity(struct ieee80211_hw *hw)
1718 {
1719 struct rtl_priv *rtlpriv = rtl_priv(hw);
1720 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1721 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1722 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1723 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1724
1725 if (mac->link_state < MAC80211_LINKED) {
1726 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "No Link\n");
1727 if (pfat_table->becomelinked) {
1728 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1729 "need to turn off HW AntDiv\n");
1730 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1731 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1732 BIT(15), 0);
1733 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1734 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1735 BIT(21), 0);
1736 pfat_table->becomelinked =
1737 (mac->link_state == MAC80211_LINKED) ?
1738 true : false;
1739 }
1740 return;
1741 } else {
1742 if (!pfat_table->becomelinked) {
1743 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1744 "Need to turn on HW AntDiv\n");
1745 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1746 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1747 BIT(15), 1);
1748 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1749 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1750 BIT(21), 1);
1751 pfat_table->becomelinked =
1752 (mac->link_state >= MAC80211_LINKED) ?
1753 true : false;
1754 }
1755 }
1756
1757 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1758 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV))
1759 rtl88e_dm_hw_ant_div(hw);
1760 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1761 rtl88e_dm_fast_ant_training(hw);
1762 }
1763
1764 void rtl88e_dm_init(struct ieee80211_hw *hw)
1765 {
1766 struct rtl_priv *rtlpriv = rtl_priv(hw);
1767 u32 cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
1768
1769 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1770 rtl_dm_diginit(hw, cur_igvalue);
1771 rtl88e_dm_init_dynamic_txpower(hw);
1772 rtl88e_dm_init_edca_turbo(hw);
1773 rtl88e_dm_init_rate_adaptive_mask(hw);
1774 rtl88e_dm_init_txpower_tracking(hw);
1775 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1776 rtl88e_dm_antenna_div_init(hw);
1777 }
1778
1779 void rtl88e_dm_watchdog(struct ieee80211_hw *hw)
1780 {
1781 struct rtl_priv *rtlpriv = rtl_priv(hw);
1782 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1783 bool fw_current_inpsmode = false;
1784 bool fw_ps_awake = true;
1785
1786 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1787 (u8 *)(&fw_current_inpsmode));
1788 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1789 (u8 *)(&fw_ps_awake));
1790 if (ppsc->p2p_ps_info.p2p_ps_mode)
1791 fw_ps_awake = false;
1792
1793 if ((ppsc->rfpwr_state == ERFON) &&
1794 ((!fw_current_inpsmode) && fw_ps_awake) &&
1795 (!ppsc->rfchange_inprogress)) {
1796 rtl88e_dm_pwdb_monitor(hw);
1797 rtl88e_dm_dig(hw);
1798 rtl88e_dm_false_alarm_counter_statistics(hw);
1799 rtl92c_dm_dynamic_txpower(hw);
1800 rtl88e_dm_check_txpower_tracking(hw);
1801 rtl88e_dm_refresh_rate_adaptive_mask(hw);
1802 rtl88e_dm_check_edca_turbo(hw);
1803 rtl88e_dm_antenna_diversity(hw);
1804 }
1805 } 1
2 #include <linux/kernel.h>
3 #include <linux/mutex.h>
4 #include <linux/spinlock.h>
5 #include <linux/errno.h>
6 #include <verifier/rcv.h>
7 #include <linux/list.h>
8
9 /* mutexes */
10 extern int mutex_lock_interruptible(struct mutex *lock);
11 extern int mutex_lock_killable(struct mutex *lock);
12 extern void mutex_lock(struct mutex *lock);
13
14 /* mutex model functions */
15 extern void ldv_mutex_lock(struct mutex *lock, char *sign);
16 extern int ldv_mutex_is_locked(struct mutex *lock, char *sign);
17 extern void ldv_mutex_unlock(struct mutex *lock, char *sign);
18
19
20 /* Spin locks */
21 extern void __ldv_spin_lock(spinlock_t *lock);
22 extern void __ldv_spin_unlock(spinlock_t *lock);
23 extern int __ldv_spin_trylock(spinlock_t *lock);
24 extern void __ldv_spin_unlock_wait(spinlock_t *lock);
25 extern void __ldv_spin_can_lock(spinlock_t *lock);
26 extern int __ldv_atomic_dec_and_lock(spinlock_t *lock);
27
28 /* spin model functions */
29 extern void ldv_spin_lock(spinlock_t *lock, char *sign);
30 extern void ldv_spin_unlock(spinlock_t *lock, char *sign);
31 extern int ldv_spin_is_locked(spinlock_t *lock, char *sign);
32
33 /* Support for list binder functions */
34 static inline struct list_head *ldv_list_get_first(struct list_head *head) {
35 return head->next;
36 }
37
38 static inline int ldv_list_is_stop(struct list_head *pos, struct list_head *head) {
39 return pos==head;
40 }
41
42 static inline struct list_head *ldv_list_get_next(struct list_head *pos) {
43 return pos->next;
44 }
45
46 #include <linux/mutex.h>
47 #include <linux/slab.h>
48 #include <verifier/rcv.h>
49 #include <linux/timer.h>
50 #include <linux/gfp.h>
51 extern struct timer_list * ldv_timer_list_4;
52 extern int ldv_timer_1_3;
53 extern int pci_counter;
54 extern struct timer_list * ldv_timer_list_2_0;
55 extern struct timer_list * ldv_timer_list_3;
56 extern int ldv_timer_2_1;
57 extern int ldv_state_variable_0;
58 extern int ldv_state_variable_5;
59 extern int ldv_timer_state_3 = 0;
60 extern int ldv_timer_2_2;
61 extern int ldv_timer_2_3;
62 extern int ldv_timer_1_0;
63 extern struct pci_dev *rtl88ee_driver_group1;
64 extern int ldv_timer_state_4 = 0;
65 extern int ref_cnt;
66 extern int ldv_state_variable_1;
67 extern int ldv_state_variable_7;
68 extern struct timer_list * ldv_timer_list_1_3;
69 extern struct sk_buff *rtl8188ee_hal_ops_group0;
70 extern struct timer_list * ldv_timer_list_1_1;
71 extern struct timer_list * ldv_timer_list_2_1;
72 extern struct ieee80211_hw *rtl8188ee_hal_ops_group1;
73 extern struct timer_list * ldv_timer_list_1_0;
74 extern int ldv_state_variable_6;
75 extern int ldv_timer_1_2;
76 extern int ldv_timer_2_0;
77 extern struct ieee80211_sta *rtl8188ee_hal_ops_group2;
78 extern int ldv_timer_1_1;
79 extern int ldv_state_variable_2;
80 extern struct timer_list * ldv_timer_list_1_2;
81 extern int LDV_IN_INTERRUPT = 1;
82 extern struct device *rtlwifi_pm_ops_group1;
83 extern struct mutex fs_mutex;
84 extern int ldv_state_variable_3;
85 extern struct timer_list * ldv_timer_list_2_3;
86 extern struct mutex ar_mutex;
87 extern struct timer_list * ldv_timer_list_2_2;
88 extern int ldv_state_variable_4;
89 extern void ldv_pci_driver_5(void);
90 extern void choose_timer_2(void);
91 extern int reg_timer_2(struct timer_list * timer, void (*function)(unsigned long), unsigned long data);
92 extern void activate_pending_timer_2(struct timer_list * timer, unsigned long data, int pending_flag);
93 extern void choose_timer_3(struct timer_list * timer);
94 extern void activate_pending_timer_4(struct timer_list * timer, unsigned long data, int pending_flag);
95 extern void activate_pending_timer_1(struct timer_list * timer, unsigned long data, int pending_flag);
96 extern void choose_timer_4(struct timer_list * timer);
97 extern void timer_init_2(void);
98 extern void timer_init_1(void);
99 extern void disable_suitable_timer_3(struct timer_list * timer);
100 extern void disable_suitable_timer_4(struct timer_list * timer);
101 extern void ldv_dev_pm_ops_6(void);
102 extern int reg_timer_1(struct timer_list * timer, void (*function)(unsigned long), unsigned long data);
103 extern int reg_timer_4(struct timer_list * timer);
104 extern void disable_suitable_timer_2(struct timer_list * timer);
105 extern void disable_suitable_timer_1(struct timer_list * timer);
106 extern void activate_suitable_timer_1(struct timer_list * timer, unsigned long data);
107 extern void activate_pending_timer_3(struct timer_list * timer, unsigned long data, int pending_flag);
108 extern int evil_hack_fs_lock(void);
109 extern int __VERIFIER_nondet_int(void);
110 extern int reg_timer_3(struct timer_list * timer);
111 extern void ldv_initialyze_rtl_hal_ops_7(void);
112 extern void choose_timer_1(void);
113 extern void ldv_timer_1(int state, struct timer_list * timer);
114 extern void activate_suitable_timer_2(struct timer_list * timer, unsigned long data);
115 extern int evil_hack_ar_lock(void);
116 extern void ldv_timer_2(int state, struct timer_list * timer);
117 #line 1 "/work/ldvuser/andrianov/work/current--X--drivers/net/wireless/--X--defaultlinux-4.5-rc7--X--races--X--cpachecker/linux-4.5-rc7/csd_deg_dscv/376/dscv_tempdir/dscv/ri/races/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c"
118 /******************************************************************************
119 *
120 * Copyright(c) 2009-2013 Realtek Corporation.
121 *
122 * This program is free software; you can redistribute it and/or modify it
123 * under the terms of version 2 of the GNU General Public License as
124 * published by the Free Software Foundation.
125 *
126 * This program is distributed in the hope that it will be useful, but WITHOUT
127 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
128 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
129 * more details.
130 *
131 * The full GNU General Public License is included in this distribution in the
132 * file called LICENSE.
133 *
134 * Contact Information:
135 * wlanfae <wlanfae@realtek.com>
136 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
137 * Hsinchu 300, Taiwan.
138 *
139 * Larry Finger <Larry.Finger@lwfinger.net>
140 *
141 *****************************************************************************/
142
143 #include "../wifi.h"
144 #include "../base.h"
145 #include "../pci.h"
146 #include "../core.h"
147 #include "reg.h"
148 #include "def.h"
149 #include "phy.h"
150 #include "dm.h"
151 #include "fw.h"
152 #include "trx.h"
153
154 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
155 0x7f8001fe, /* 0, +6.0dB */
156 0x788001e2, /* 1, +5.5dB */
157 0x71c001c7, /* 2, +5.0dB */
158 0x6b8001ae, /* 3, +4.5dB */
159 0x65400195, /* 4, +4.0dB */
160 0x5fc0017f, /* 5, +3.5dB */
161 0x5a400169, /* 6, +3.0dB */
162 0x55400155, /* 7, +2.5dB */
163 0x50800142, /* 8, +2.0dB */
164 0x4c000130, /* 9, +1.5dB */
165 0x47c0011f, /* 10, +1.0dB */
166 0x43c0010f, /* 11, +0.5dB */
167 0x40000100, /* 12, +0dB */
168 0x3c8000f2, /* 13, -0.5dB */
169 0x390000e4, /* 14, -1.0dB */
170 0x35c000d7, /* 15, -1.5dB */
171 0x32c000cb, /* 16, -2.0dB */
172 0x300000c0, /* 17, -2.5dB */
173 0x2d4000b5, /* 18, -3.0dB */
174 0x2ac000ab, /* 19, -3.5dB */
175 0x288000a2, /* 20, -4.0dB */
176 0x26000098, /* 21, -4.5dB */
177 0x24000090, /* 22, -5.0dB */
178 0x22000088, /* 23, -5.5dB */
179 0x20000080, /* 24, -6.0dB */
180 0x1e400079, /* 25, -6.5dB */
181 0x1c800072, /* 26, -7.0dB */
182 0x1b00006c, /* 27. -7.5dB */
183 0x19800066, /* 28, -8.0dB */
184 0x18000060, /* 29, -8.5dB */
185 0x16c0005b, /* 30, -9.0dB */
186 0x15800056, /* 31, -9.5dB */
187 0x14400051, /* 32, -10.0dB */
188 0x1300004c, /* 33, -10.5dB */
189 0x12000048, /* 34, -11.0dB */
190 0x11000044, /* 35, -11.5dB */
191 0x10000040, /* 36, -12.0dB */
192 0x0f00003c, /* 37, -12.5dB */
193 0x0e400039, /* 38, -13.0dB */
194 0x0d800036, /* 39, -13.5dB */
195 0x0cc00033, /* 40, -14.0dB */
196 0x0c000030, /* 41, -14.5dB */
197 0x0b40002d, /* 42, -15.0dB */
198 };
199
200 static const u8 cck_tbl_ch1_13[CCK_TABLE_SIZE][8] = {
201 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
202 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
203 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
204 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
205 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
206 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
207 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
208 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
209 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
210 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
211 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
212 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
213 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
214 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
215 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
216 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
217 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
218 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
219 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
220 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
221 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
222 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
223 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
224 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
225 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
226 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
227 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
228 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
229 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
230 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
231 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
232 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
233 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
234 };
235
236 static const u8 cck_tbl_ch14[CCK_TABLE_SIZE][8] = {
237 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
238 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
239 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
240 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
241 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
242 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
243 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
244 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
245 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
246 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
247 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
248 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
249 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
250 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
251 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
252 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
253 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
254 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
255 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
256 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
257 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
258 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
259 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
260 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
261 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
262 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
263 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
264 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
265 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
266 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
267 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
268 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
269 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
270 };
271
272 #define CAL_SWING_OFF(_off, _dir, _size, _del) \
273 do { \
274 for (_off = 0; _off < _size; _off++) { \
275 if (_del < thermal_threshold[_dir][_off]) { \
276 if (_off != 0) \
277 _off--; \
278 break; \
279 } \
280 } \
281 if (_off >= _size) \
282 _off = _size - 1; \
283 } while (0)
284
285 static void rtl88e_set_iqk_matrix(struct ieee80211_hw *hw,
286 u8 ofdm_index, u8 rfpath,
287 long iqk_result_x, long iqk_result_y)
288 {
289 long ele_a = 0, ele_d, ele_c = 0, value32;
290
291 ele_d = (ofdmswing_table[ofdm_index] & 0xFFC00000)>>22;
292
293 if (iqk_result_x != 0) {
294 if ((iqk_result_x & 0x00000200) != 0)
295 iqk_result_x = iqk_result_x | 0xFFFFFC00;
296 ele_a = ((iqk_result_x * ele_d)>>8)&0x000003FF;
297
298 if ((iqk_result_y & 0x00000200) != 0)
299 iqk_result_y = iqk_result_y | 0xFFFFFC00;
300 ele_c = ((iqk_result_y * ele_d)>>8)&0x000003FF;
301
302 switch (rfpath) {
303 case RF90_PATH_A:
304 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
305 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
306 MASKDWORD, value32);
307 value32 = (ele_c & 0x000003C0) >> 6;
308 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
309 value32);
310 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
311 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
312 value32);
313 break;
314 case RF90_PATH_B:
315 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
316 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
317 value32);
318 value32 = (ele_c & 0x000003C0) >> 6;
319 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32);
320 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
321 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
322 value32);
323 break;
324 default:
325 break;
326 }
327 } else {
328 switch (rfpath) {
329 case RF90_PATH_A:
330 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
331 MASKDWORD, ofdmswing_table[ofdm_index]);
332 rtl_set_bbreg(hw, ROFDM0_XCTXAFE,
333 MASKH4BITS, 0x00);
334 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
335 BIT(24), 0x00);
336 break;
337 case RF90_PATH_B:
338 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
339 MASKDWORD, ofdmswing_table[ofdm_index]);
340 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
341 MASKH4BITS, 0x00);
342 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
343 BIT(28), 0x00);
344 break;
345 default:
346 break;
347 }
348 }
349 }
350
351 void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
352 u8 type, u8 *pdirection, u32 *poutwrite_val)
353 {
354 struct rtl_priv *rtlpriv = rtl_priv(hw);
355 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
356 u8 pwr_val = 0;
357 u8 cck_base = rtldm->swing_idx_cck_base;
358 u8 cck_val = rtldm->swing_idx_cck;
359 u8 ofdm_base = rtldm->swing_idx_ofdm_base[0];
360 u8 ofdm_val = rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A];
361
362 if (type == 0) {
363 if (ofdm_val <= ofdm_base) {
364 *pdirection = 1;
365 pwr_val = ofdm_base - ofdm_val;
366 } else {
367 *pdirection = 2;
368 pwr_val = ofdm_base - ofdm_val;
369 }
370 } else if (type == 1) {
371 if (cck_val <= cck_base) {
372 *pdirection = 1;
373 pwr_val = cck_base - cck_val;
374 } else {
375 *pdirection = 2;
376 pwr_val = cck_val - cck_base;
377 }
378 }
379
380 if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1))
381 pwr_val = TXPWRTRACK_MAX_IDX;
382
383 *poutwrite_val = pwr_val | (pwr_val << 8) | (pwr_val << 16) |
384 (pwr_val << 24);
385 }
386
387 static void dm_tx_pwr_track_set_pwr(struct ieee80211_hw *hw,
388 enum pwr_track_control_method method,
389 u8 rfpath, u8 channel_mapped_index)
390 {
391 struct rtl_priv *rtlpriv = rtl_priv(hw);
392 struct rtl_phy *rtlphy = &rtlpriv->phy;
393 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
394
395 if (method == TXAGC) {
396 if (rtldm->swing_flag_ofdm ||
397 rtldm->swing_flag_cck) {
398 rtl88e_phy_set_txpower_level(hw,
399 rtlphy->current_channel);
400 rtldm->swing_flag_ofdm = false;
401 rtldm->swing_flag_cck = false;
402 }
403 } else if (method == BBSWING) {
404 if (!rtldm->cck_inch14) {
405 rtl_write_byte(rtlpriv, 0xa22,
406 cck_tbl_ch1_13[rtldm->swing_idx_cck][0]);
407 rtl_write_byte(rtlpriv, 0xa23,
408 cck_tbl_ch1_13[rtldm->swing_idx_cck][1]);
409 rtl_write_byte(rtlpriv, 0xa24,
410 cck_tbl_ch1_13[rtldm->swing_idx_cck][2]);
411 rtl_write_byte(rtlpriv, 0xa25,
412 cck_tbl_ch1_13[rtldm->swing_idx_cck][3]);
413 rtl_write_byte(rtlpriv, 0xa26,
414 cck_tbl_ch1_13[rtldm->swing_idx_cck][4]);
415 rtl_write_byte(rtlpriv, 0xa27,
416 cck_tbl_ch1_13[rtldm->swing_idx_cck][5]);
417 rtl_write_byte(rtlpriv, 0xa28,
418 cck_tbl_ch1_13[rtldm->swing_idx_cck][6]);
419 rtl_write_byte(rtlpriv, 0xa29,
420 cck_tbl_ch1_13[rtldm->swing_idx_cck][7]);
421 } else {
422 rtl_write_byte(rtlpriv, 0xa22,
423 cck_tbl_ch14[rtldm->swing_idx_cck][0]);
424 rtl_write_byte(rtlpriv, 0xa23,
425 cck_tbl_ch14[rtldm->swing_idx_cck][1]);
426 rtl_write_byte(rtlpriv, 0xa24,
427 cck_tbl_ch14[rtldm->swing_idx_cck][2]);
428 rtl_write_byte(rtlpriv, 0xa25,
429 cck_tbl_ch14[rtldm->swing_idx_cck][3]);
430 rtl_write_byte(rtlpriv, 0xa26,
431 cck_tbl_ch14[rtldm->swing_idx_cck][4]);
432 rtl_write_byte(rtlpriv, 0xa27,
433 cck_tbl_ch14[rtldm->swing_idx_cck][5]);
434 rtl_write_byte(rtlpriv, 0xa28,
435 cck_tbl_ch14[rtldm->swing_idx_cck][6]);
436 rtl_write_byte(rtlpriv, 0xa29,
437 cck_tbl_ch14[rtldm->swing_idx_cck][7]);
438 }
439
440 if (rfpath == RF90_PATH_A) {
441 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath],
442 rfpath, rtlphy->iqk_matrix
443 [channel_mapped_index].
444 value[0][0],
445 rtlphy->iqk_matrix
446 [channel_mapped_index].
447 value[0][1]);
448 } else if (rfpath == RF90_PATH_B) {
449 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath],
450 rfpath, rtlphy->iqk_matrix
451 [channel_mapped_index].
452 value[0][4],
453 rtlphy->iqk_matrix
454 [channel_mapped_index].
455 value[0][5]);
456 }
457 } else {
458 return;
459 }
460 }
461
462 static u8 rtl88e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
463 {
464 struct rtl_priv *rtlpriv = rtl_priv(hw);
465 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
466 long rssi_val_min = 0;
467
468 if ((dm_dig->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
469 (dm_dig->cur_sta_cstate == DIG_STA_CONNECT)) {
470 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
471 rssi_val_min =
472 (rtlpriv->dm.entry_min_undec_sm_pwdb >
473 rtlpriv->dm.undec_sm_pwdb) ?
474 rtlpriv->dm.undec_sm_pwdb :
475 rtlpriv->dm.entry_min_undec_sm_pwdb;
476 else
477 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
478 } else if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT ||
479 dm_dig->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) {
480 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
481 } else if (dm_dig->curmultista_cstate ==
482 DIG_MULTISTA_CONNECT) {
483 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
484 }
485
486 return (u8)rssi_val_min;
487 }
488
489 static void rtl88e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
490 {
491 u32 ret_value;
492 struct rtl_priv *rtlpriv = rtl_priv(hw);
493 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
494
495 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1);
496 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1);
497
498 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
499 falsealm_cnt->cnt_fast_fsync_fail = (ret_value&0xffff);
500 falsealm_cnt->cnt_sb_search_fail = ((ret_value&0xffff0000)>>16);
501
502 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
503 falsealm_cnt->cnt_ofdm_cca = (ret_value&0xffff);
504 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
505
506 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
507 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
508 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
509
510 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
511 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
512 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
513 falsealm_cnt->cnt_rate_illegal +
514 falsealm_cnt->cnt_crc8_fail +
515 falsealm_cnt->cnt_mcs_fail +
516 falsealm_cnt->cnt_fast_fsync_fail +
517 falsealm_cnt->cnt_sb_search_fail;
518
519 ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD);
520 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
521 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
522
523 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1);
524 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
525
526 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
527 falsealm_cnt->cnt_cck_fail = ret_value;
528
529 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
530 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
531
532 ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD);
533 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
534 ((ret_value&0xFF00)>>8);
535
536 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_fast_fsync_fail +
537 falsealm_cnt->cnt_sb_search_fail +
538 falsealm_cnt->cnt_parity_fail +
539 falsealm_cnt->cnt_rate_illegal +
540 falsealm_cnt->cnt_crc8_fail +
541 falsealm_cnt->cnt_mcs_fail +
542 falsealm_cnt->cnt_cck_fail);
543 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
544 falsealm_cnt->cnt_cck_cca;
545
546 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1);
547 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0);
548 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1);
549 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0);
550 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
551 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
552 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0);
553 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2);
554 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0);
555 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2);
556
557 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
558 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
559 falsealm_cnt->cnt_parity_fail,
560 falsealm_cnt->cnt_rate_illegal,
561 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
562
563 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
564 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
565 falsealm_cnt->cnt_ofdm_fail,
566 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
567 }
568
569 static void rtl88e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
570 {
571 struct rtl_priv *rtlpriv = rtl_priv(hw);
572 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
573 u8 cur_cck_cca_thresh;
574
575 if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) {
576 dm_dig->rssi_val_min = rtl88e_dm_initial_gain_min_pwdb(hw);
577 if (dm_dig->rssi_val_min > 25) {
578 cur_cck_cca_thresh = 0xcd;
579 } else if ((dm_dig->rssi_val_min <= 25) &&
580 (dm_dig->rssi_val_min > 10)) {
581 cur_cck_cca_thresh = 0x83;
582 } else {
583 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
584 cur_cck_cca_thresh = 0x83;
585 else
586 cur_cck_cca_thresh = 0x40;
587 }
588
589 } else {
590 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
591 cur_cck_cca_thresh = 0x83;
592 else
593 cur_cck_cca_thresh = 0x40;
594 }
595
596 if (dm_dig->cur_cck_cca_thres != cur_cck_cca_thresh)
597 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
598
599 dm_dig->cur_cck_cca_thres = cur_cck_cca_thresh;
600 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
601 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
602 "CCK cca thresh hold =%x\n", dm_dig->cur_cck_cca_thres);
603 }
604
605 static void rtl88e_dm_dig(struct ieee80211_hw *hw)
606 {
607 struct rtl_priv *rtlpriv = rtl_priv(hw);
608 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
609 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
610 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
611 u8 dig_dynamic_min, dig_maxofmin;
612 bool bfirstconnect;
613 u8 dm_dig_max, dm_dig_min;
614 u8 current_igi = dm_dig->cur_igvalue;
615
616 if (rtlpriv->dm.dm_initialgain_enable == false)
617 return;
618 if (dm_dig->dig_enable_flag == false)
619 return;
620 if (mac->act_scanning == true)
621 return;
622
623 if (mac->link_state >= MAC80211_LINKED)
624 dm_dig->cur_sta_cstate = DIG_STA_CONNECT;
625 else
626 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT;
627 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
628 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
629 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT;
630
631 dm_dig_max = DM_DIG_MAX;
632 dm_dig_min = DM_DIG_MIN;
633 dig_maxofmin = DM_DIG_MAX_AP;
634 dig_dynamic_min = dm_dig->dig_min_0;
635 bfirstconnect = ((mac->link_state >= MAC80211_LINKED) ? true : false) &&
636 !dm_dig->media_connect_0;
637
638 dm_dig->rssi_val_min =
639 rtl88e_dm_initial_gain_min_pwdb(hw);
640
641 if (mac->link_state >= MAC80211_LINKED) {
642 if ((dm_dig->rssi_val_min + 20) > dm_dig_max)
643 dm_dig->rx_gain_max = dm_dig_max;
644 else if ((dm_dig->rssi_val_min + 20) < dm_dig_min)
645 dm_dig->rx_gain_max = dm_dig_min;
646 else
647 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 20;
648
649 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
650 dig_dynamic_min = dm_dig->antdiv_rssi_max;
651 } else {
652 if (dm_dig->rssi_val_min < dm_dig_min)
653 dig_dynamic_min = dm_dig_min;
654 else if (dm_dig->rssi_val_min < dig_maxofmin)
655 dig_dynamic_min = dig_maxofmin;
656 else
657 dig_dynamic_min = dm_dig->rssi_val_min;
658 }
659 } else {
660 dm_dig->rx_gain_max = dm_dig_max;
661 dig_dynamic_min = dm_dig_min;
662 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
663 }
664
665 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
666 dm_dig->large_fa_hit++;
667 if (dm_dig->forbidden_igi < current_igi) {
668 dm_dig->forbidden_igi = current_igi;
669 dm_dig->large_fa_hit = 1;
670 }
671
672 if (dm_dig->large_fa_hit >= 3) {
673 if ((dm_dig->forbidden_igi + 1) >
674 dm_dig->rx_gain_max)
675 dm_dig->rx_gain_min =
676 dm_dig->rx_gain_max;
677 else
678 dm_dig->rx_gain_min =
679 dm_dig->forbidden_igi + 1;
680 dm_dig->recover_cnt = 3600;
681 }
682 } else {
683 if (dm_dig->recover_cnt != 0) {
684 dm_dig->recover_cnt--;
685 } else {
686 if (dm_dig->large_fa_hit == 0) {
687 if ((dm_dig->forbidden_igi - 1) <
688 dig_dynamic_min) {
689 dm_dig->forbidden_igi = dig_dynamic_min;
690 dm_dig->rx_gain_min = dig_dynamic_min;
691 } else {
692 dm_dig->forbidden_igi--;
693 dm_dig->rx_gain_min =
694 dm_dig->forbidden_igi + 1;
695 }
696 } else if (dm_dig->large_fa_hit == 3) {
697 dm_dig->large_fa_hit = 0;
698 }
699 }
700 }
701
702 if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) {
703 if (bfirstconnect) {
704 current_igi = dm_dig->rssi_val_min;
705 } else {
706 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
707 current_igi += 2;
708 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
709 current_igi++;
710 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
711 current_igi--;
712 }
713 } else {
714 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
715 current_igi += 2;
716 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
717 current_igi++;
718 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
719 current_igi--;
720 }
721
722 if (current_igi > DM_DIG_FA_UPPER)
723 current_igi = DM_DIG_FA_UPPER;
724 else if (current_igi < DM_DIG_FA_LOWER)
725 current_igi = DM_DIG_FA_LOWER;
726
727 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
728 current_igi = DM_DIG_FA_UPPER;
729
730 dm_dig->cur_igvalue = current_igi;
731 rtl88e_dm_write_dig(hw);
732 dm_dig->media_connect_0 =
733 ((mac->link_state >= MAC80211_LINKED) ? true : false);
734 dm_dig->dig_min_0 = dig_dynamic_min;
735
736 rtl88e_dm_cck_packet_detection_thresh(hw);
737 }
738
739 static void rtl88e_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
740 {
741 struct rtl_priv *rtlpriv = rtl_priv(hw);
742
743 rtlpriv->dm.dynamic_txpower_enable = false;
744
745 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
746 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
747 }
748
749 static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
750 {
751 struct rtl_priv *rtlpriv = rtl_priv(hw);
752 struct rtl_phy *rtlphy = &rtlpriv->phy;
753 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
754 long undec_sm_pwdb;
755
756 if (!rtlpriv->dm.dynamic_txpower_enable)
757 return;
758
759 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
760 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
761 return;
762 }
763
764 if ((mac->link_state < MAC80211_LINKED) &&
765 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
766 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
767 "Not connected to any\n");
768
769 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
770
771 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
772 return;
773 }
774
775 if (mac->link_state >= MAC80211_LINKED) {
776 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
777 undec_sm_pwdb =
778 rtlpriv->dm.entry_min_undec_sm_pwdb;
779 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
780 "AP Client PWDB = 0x%lx\n",
781 undec_sm_pwdb);
782 } else {
783 undec_sm_pwdb =
784 rtlpriv->dm.undec_sm_pwdb;
785 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
786 "STA Default Port PWDB = 0x%lx\n",
787 undec_sm_pwdb);
788 }
789 } else {
790 undec_sm_pwdb =
791 rtlpriv->dm.entry_min_undec_sm_pwdb;
792
793 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
794 "AP Ext Port PWDB = 0x%lx\n",
795 undec_sm_pwdb);
796 }
797
798 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
799 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
800 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
801 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x0)\n");
802 } else if ((undec_sm_pwdb <
803 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
804 (undec_sm_pwdb >=
805 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
806 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
807 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
808 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x10)\n");
809 } else if (undec_sm_pwdb <
810 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
811 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
812 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
813 "TXHIGHPWRLEVEL_NORMAL\n");
814 }
815
816 if ((rtlpriv->dm.dynamic_txhighpower_lvl !=
817 rtlpriv->dm.last_dtp_lvl)) {
818 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
819 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
820 rtlphy->current_channel);
821 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
822 }
823
824 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
825 }
826
827 void rtl88e_dm_write_dig(struct ieee80211_hw *hw)
828 {
829 struct rtl_priv *rtlpriv = rtl_priv(hw);
830 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
831
832 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
833 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
834 dm_dig->cur_igvalue, dm_dig->pre_igvalue,
835 dm_dig->back_val);
836
837 if (dm_dig->cur_igvalue > 0x3f)
838 dm_dig->cur_igvalue = 0x3f;
839 if (dm_dig->pre_igvalue != dm_dig->cur_igvalue) {
840 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
841 dm_dig->cur_igvalue);
842
843 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
844 }
845 }
846
847 static void rtl88e_dm_pwdb_monitor(struct ieee80211_hw *hw)
848 {
849 struct rtl_priv *rtlpriv = rtl_priv(hw);
850 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
851 struct rtl_sta_info *drv_priv;
852 static u64 last_record_txok_cnt;
853 static u64 last_record_rxok_cnt;
854 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
855
856 if (rtlhal->oem_id == RT_CID_819X_HP) {
857 u64 cur_txok_cnt = 0;
858 u64 cur_rxok_cnt = 0;
859 cur_txok_cnt = rtlpriv->stats.txbytesunicast -
860 last_record_txok_cnt;
861 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast -
862 last_record_rxok_cnt;
863 last_record_txok_cnt = cur_txok_cnt;
864 last_record_rxok_cnt = cur_rxok_cnt;
865
866 if (cur_rxok_cnt > (cur_txok_cnt * 6))
867 rtl_write_dword(rtlpriv, REG_ARFR0, 0x8f015);
868 else
869 rtl_write_dword(rtlpriv, REG_ARFR0, 0xff015);
870 }
871
872 /* AP & ADHOC & MESH */
873 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
874 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
875 if (drv_priv->rssi_stat.undec_sm_pwdb <
876 tmp_entry_min_pwdb)
877 tmp_entry_min_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
878 if (drv_priv->rssi_stat.undec_sm_pwdb >
879 tmp_entry_max_pwdb)
880 tmp_entry_max_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
881 }
882 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
883
884 /* If associated entry is found */
885 if (tmp_entry_max_pwdb != 0) {
886 rtlpriv->dm.entry_max_undec_sm_pwdb = tmp_entry_max_pwdb;
887 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMaxPWDB = 0x%lx(%ld)\n",
888 tmp_entry_max_pwdb, tmp_entry_max_pwdb);
889 } else {
890 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
891 }
892 /* If associated entry is found */
893 if (tmp_entry_min_pwdb != 0xff) {
894 rtlpriv->dm.entry_min_undec_sm_pwdb = tmp_entry_min_pwdb;
895 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMinPWDB = 0x%lx(%ld)\n",
896 tmp_entry_min_pwdb, tmp_entry_min_pwdb);
897 } else {
898 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
899 }
900 /* Indicate Rx signal strength to FW. */
901 if (rtlpriv->dm.useramask) {
902 u8 h2c_parameter[3] = { 0 };
903
904 h2c_parameter[2] = (u8)(rtlpriv->dm.undec_sm_pwdb & 0xFF);
905 h2c_parameter[0] = 0x20;
906 } else {
907 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb);
908 }
909 }
910
911 void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw)
912 {
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914
915 rtlpriv->dm.current_turbo_edca = false;
916 rtlpriv->dm.is_any_nonbepkts = false;
917 rtlpriv->dm.is_cur_rdlstate = false;
918 }
919
920 static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw)
921 {
922 struct rtl_priv *rtlpriv = rtl_priv(hw);
923 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
924 static u64 last_txok_cnt;
925 static u64 last_rxok_cnt;
926 static u32 last_bt_edca_ul;
927 static u32 last_bt_edca_dl;
928 u64 cur_txok_cnt = 0;
929 u64 cur_rxok_cnt = 0;
930 u32 edca_be_ul = 0x5ea42b;
931 u32 edca_be_dl = 0x5ea42b;
932 bool bt_change_edca = false;
933
934 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
935 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
936 rtlpriv->dm.current_turbo_edca = false;
937 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
938 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
939 }
940
941 if (rtlpriv->btcoexist.bt_edca_ul != 0) {
942 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
943 bt_change_edca = true;
944 }
945
946 if (rtlpriv->btcoexist.bt_edca_dl != 0) {
947 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
948 bt_change_edca = true;
949 }
950
951 if (mac->link_state != MAC80211_LINKED) {
952 rtlpriv->dm.current_turbo_edca = false;
953 return;
954 }
955 if ((bt_change_edca) ||
956 ((!rtlpriv->dm.is_any_nonbepkts) &&
957 (!rtlpriv->dm.disable_framebursting))) {
958
959 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
960 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
961
962 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
963 if (!rtlpriv->dm.is_cur_rdlstate ||
964 !rtlpriv->dm.current_turbo_edca) {
965 rtl_write_dword(rtlpriv,
966 REG_EDCA_BE_PARAM,
967 edca_be_dl);
968 rtlpriv->dm.is_cur_rdlstate = true;
969 }
970 } else {
971 if (rtlpriv->dm.is_cur_rdlstate ||
972 !rtlpriv->dm.current_turbo_edca) {
973 rtl_write_dword(rtlpriv,
974 REG_EDCA_BE_PARAM,
975 edca_be_ul);
976 rtlpriv->dm.is_cur_rdlstate = false;
977 }
978 }
979 rtlpriv->dm.current_turbo_edca = true;
980 } else {
981 if (rtlpriv->dm.current_turbo_edca) {
982 u8 tmp = AC0_BE;
983
984 rtlpriv->cfg->ops->set_hw_reg(hw,
985 HW_VAR_AC_PARAM,
986 &tmp);
987 rtlpriv->dm.current_turbo_edca = false;
988 }
989 }
990
991 rtlpriv->dm.is_any_nonbepkts = false;
992 last_txok_cnt = rtlpriv->stats.txbytesunicast;
993 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
994 }
995
996 static void dm_txpower_track_cb_therm(struct ieee80211_hw *hw)
997 {
998 struct rtl_priv *rtlpriv = rtl_priv(hw);
999 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1000 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1001 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1002 u8 thermalvalue = 0, delta, delta_lck, delta_iqk, offset;
1003 u8 thermalvalue_avg_count = 0;
1004 u32 thermalvalue_avg = 0;
1005 long ele_d, temp_cck;
1006 char ofdm_index[2], cck_index = 0,
1007 ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
1008 int i = 0;
1009 /*bool is2t = false;*/
1010
1011 u8 ofdm_min_index = 6, rf = 1;
1012 /*u8 index_for_channel;*/
1013 enum _power_dec_inc {power_dec, power_inc};
1014
1015 /*0.1 the following TWO tables decide the
1016 *final index of OFDM/CCK swing table
1017 */
1018 char delta_swing_table_idx[2][15] = {
1019 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11},
1020 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10}
1021 };
1022 u8 thermal_threshold[2][15] = {
1023 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27},
1024 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
1025 };
1026
1027 /*Initilization (7 steps in total) */
1028 rtlpriv->dm.txpower_trackinginit = true;
1029 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1030 "dm_txpower_track_cb_therm\n");
1031
1032 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER,
1033 0xfc00);
1034 if (!thermalvalue)
1035 return;
1036 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1037 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
1038 thermalvalue, rtlpriv->dm.thermalvalue,
1039 rtlefuse->eeprom_thermalmeter);
1040
1041 /*1. Query OFDM Default Setting: Path A*/
1042 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) &
1043 MASKOFDM_D;
1044 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
1045 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
1046 ofdm_index_old[0] = (u8)i;
1047 rtldm->swing_idx_ofdm_base[RF90_PATH_A] = (u8)i;
1048 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1049 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index = 0x%x\n",
1050 ROFDM0_XATXIQIMBALANCE,
1051 ele_d, ofdm_index_old[0]);
1052 break;
1053 }
1054 }
1055
1056 /*2.Query CCK default setting From 0xa24*/
1057 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
1058 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
1059 if (rtlpriv->dm.cck_inch14) {
1060 if (memcmp(&temp_cck, &cck_tbl_ch14[i][2], 4) == 0) {
1061 cck_index_old = (u8)i;
1062 rtldm->swing_idx_cck_base = (u8)i;
1063 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
1064 DBG_LOUD,
1065 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch 14 %d\n",
1066 RCCK0_TXFILTER2, temp_cck,
1067 cck_index_old,
1068 rtlpriv->dm.cck_inch14);
1069 break;
1070 }
1071 } else {
1072 if (memcmp(&temp_cck, &cck_tbl_ch1_13[i][2], 4) == 0) {
1073 cck_index_old = (u8)i;
1074 rtldm->swing_idx_cck_base = (u8)i;
1075 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
1076 DBG_LOUD,
1077 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
1078 RCCK0_TXFILTER2, temp_cck,
1079 cck_index_old,
1080 rtlpriv->dm.cck_inch14);
1081 break;
1082 }
1083 }
1084 }
1085
1086 /*3 Initialize ThermalValues of RFCalibrateInfo*/
1087 if (!rtldm->thermalvalue) {
1088 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter;
1089 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1090 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1091 for (i = 0; i < rf; i++)
1092 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
1093 rtlpriv->dm.cck_index = cck_index_old;
1094 }
1095
1096 /*4 Calculate average thermal meter*/
1097 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermalvalue;
1098 rtldm->thermalvalue_avg_index++;
1099 if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_88E)
1100 rtldm->thermalvalue_avg_index = 0;
1101
1102 for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
1103 if (rtldm->thermalvalue_avg[i]) {
1104 thermalvalue_avg += rtldm->thermalvalue_avg[i];
1105 thermalvalue_avg_count++;
1106 }
1107 }
1108
1109 if (thermalvalue_avg_count)
1110 thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count);
1111
1112 /* 5 Calculate delta, delta_LCK, delta_IQK.*/
1113 if (rtlhal->reloadtxpowerindex) {
1114 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1115 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1116 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1117 rtlhal->reloadtxpowerindex = false;
1118 rtlpriv->dm.done_txpower = false;
1119 } else if (rtlpriv->dm.done_txpower) {
1120 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
1121 (thermalvalue - rtlpriv->dm.thermalvalue) :
1122 (rtlpriv->dm.thermalvalue - thermalvalue);
1123 } else {
1124 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1125 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1126 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1127 }
1128 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
1129 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
1130 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
1131 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
1132 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
1133 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
1134
1135 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1136 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
1137 thermalvalue, rtlpriv->dm.thermalvalue,
1138 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
1139 delta_iqk);
1140 /* 6 If necessary, do LCK.*/
1141 if (delta_lck >= 8) {
1142 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1143 rtl88e_phy_lc_calibrate(hw);
1144 }
1145
1146 /* 7 If necessary, move the index of
1147 * swing table to adjust Tx power.
1148 */
1149 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
1150 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1151 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1152 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1153
1154 /* 7.1 Get the final CCK_index and OFDM_index for each
1155 * swing table.
1156 */
1157 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
1158 CAL_SWING_OFF(offset, power_inc, INDEX_MAPPING_NUM,
1159 delta);
1160 for (i = 0; i < rf; i++)
1161 ofdm_index[i] =
1162 rtldm->ofdm_index[i] +
1163 delta_swing_table_idx[power_inc][offset];
1164 cck_index = rtldm->cck_index +
1165 delta_swing_table_idx[power_inc][offset];
1166 } else {
1167 CAL_SWING_OFF(offset, power_dec, INDEX_MAPPING_NUM,
1168 delta);
1169 for (i = 0; i < rf; i++)
1170 ofdm_index[i] =
1171 rtldm->ofdm_index[i] +
1172 delta_swing_table_idx[power_dec][offset];
1173 cck_index = rtldm->cck_index +
1174 delta_swing_table_idx[power_dec][offset];
1175 }
1176
1177 /* 7.2 Handle boundary conditions of index.*/
1178 for (i = 0; i < rf; i++) {
1179 if (ofdm_index[i] > OFDM_TABLE_SIZE-1)
1180 ofdm_index[i] = OFDM_TABLE_SIZE-1;
1181 else if (rtldm->ofdm_index[i] < ofdm_min_index)
1182 ofdm_index[i] = ofdm_min_index;
1183 }
1184
1185 if (cck_index > CCK_TABLE_SIZE-1)
1186 cck_index = CCK_TABLE_SIZE-1;
1187 else if (cck_index < 0)
1188 cck_index = 0;
1189
1190 /*7.3Configure the Swing Table to adjust Tx Power.*/
1191 if (rtlpriv->dm.txpower_track_control) {
1192 rtldm->done_txpower = true;
1193 rtldm->swing_idx_ofdm[RF90_PATH_A] =
1194 (u8)ofdm_index[RF90_PATH_A];
1195 rtldm->swing_idx_cck = cck_index;
1196 if (rtldm->swing_idx_ofdm_cur !=
1197 rtldm->swing_idx_ofdm[0]) {
1198 rtldm->swing_idx_ofdm_cur =
1199 rtldm->swing_idx_ofdm[0];
1200 rtldm->swing_flag_ofdm = true;
1201 }
1202
1203 if (rtldm->swing_idx_cck_cur != rtldm->swing_idx_cck) {
1204 rtldm->swing_idx_cck_cur = rtldm->swing_idx_cck;
1205 rtldm->swing_flag_cck = true;
1206 }
1207
1208 dm_tx_pwr_track_set_pwr(hw, TXAGC, 0, 0);
1209 }
1210 }
1211
1212 if (delta_iqk >= 8) {
1213 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1214 rtl88e_phy_iq_calibrate(hw, false);
1215 }
1216
1217 if (rtldm->txpower_track_control)
1218 rtldm->thermalvalue = thermalvalue;
1219 rtldm->txpowercount = 0;
1220 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n");
1221 }
1222
1223 static void rtl88e_dm_init_txpower_tracking(struct ieee80211_hw *hw)
1224 {
1225 struct rtl_priv *rtlpriv = rtl_priv(hw);
1226
1227 rtlpriv->dm.txpower_tracking = true;
1228 rtlpriv->dm.txpower_trackinginit = false;
1229 rtlpriv->dm.txpowercount = 0;
1230 rtlpriv->dm.txpower_track_control = true;
1231
1232 rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A] = 12;
1233 rtlpriv->dm.swing_idx_ofdm_cur = 12;
1234 rtlpriv->dm.swing_flag_ofdm = false;
1235 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1236 "rtlpriv->dm.txpower_tracking = %d\n",
1237 rtlpriv->dm.txpower_tracking);
1238 }
1239
1240 void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1241 {
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243
1244 if (!rtlpriv->dm.txpower_tracking)
1245 return;
1246
1247 if (!rtlpriv->dm.tm_trigger) {
1248 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16),
1249 0x03);
1250 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1251 "Trigger 88E Thermal Meter!!\n");
1252 rtlpriv->dm.tm_trigger = 1;
1253 return;
1254 } else {
1255 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1256 "Schedule TxPowerTracking !!\n");
1257 dm_txpower_track_cb_therm(hw);
1258 rtlpriv->dm.tm_trigger = 0;
1259 }
1260 }
1261
1262 void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1263 {
1264 struct rtl_priv *rtlpriv = rtl_priv(hw);
1265 struct rate_adaptive *p_ra = &rtlpriv->ra;
1266
1267 p_ra->ratr_state = DM_RATR_STA_INIT;
1268 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1269
1270 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1271 rtlpriv->dm.useramask = true;
1272 else
1273 rtlpriv->dm.useramask = false;
1274 }
1275
1276 static void rtl88e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1277 {
1278 struct rtl_priv *rtlpriv = rtl_priv(hw);
1279 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1280 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1281 struct rate_adaptive *p_ra = &rtlpriv->ra;
1282 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1283 struct ieee80211_sta *sta = NULL;
1284
1285 if (is_hal_stop(rtlhal)) {
1286 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1287 "driver is going to unload\n");
1288 return;
1289 }
1290
1291 if (!rtlpriv->dm.useramask) {
1292 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1293 "driver does not control rate adaptive mask\n");
1294 return;
1295 }
1296
1297 if (mac->link_state == MAC80211_LINKED &&
1298 mac->opmode == NL80211_IFTYPE_STATION) {
1299 switch (p_ra->pre_ratr_state) {
1300 case DM_RATR_STA_HIGH:
1301 high_rssithresh_for_ra = 50;
1302 low_rssithresh_for_ra = 20;
1303 break;
1304 case DM_RATR_STA_MIDDLE:
1305 high_rssithresh_for_ra = 55;
1306 low_rssithresh_for_ra = 20;
1307 break;
1308 case DM_RATR_STA_LOW:
1309 high_rssithresh_for_ra = 50;
1310 low_rssithresh_for_ra = 25;
1311 break;
1312 default:
1313 high_rssithresh_for_ra = 50;
1314 low_rssithresh_for_ra = 20;
1315 break;
1316 }
1317
1318 if (rtlpriv->dm.undec_sm_pwdb >
1319 (long)high_rssithresh_for_ra)
1320 p_ra->ratr_state = DM_RATR_STA_HIGH;
1321 else if (rtlpriv->dm.undec_sm_pwdb >
1322 (long)low_rssithresh_for_ra)
1323 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1324 else
1325 p_ra->ratr_state = DM_RATR_STA_LOW;
1326
1327 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1328 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1329 "RSSI = %ld\n",
1330 rtlpriv->dm.undec_sm_pwdb);
1331 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1332 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1333 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1334 "PreState = %d, CurState = %d\n",
1335 p_ra->pre_ratr_state, p_ra->ratr_state);
1336
1337 rcu_read_lock();
1338 sta = rtl_find_sta(hw, mac->bssid);
1339 if (sta)
1340 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1341 p_ra->ratr_state);
1342 rcu_read_unlock();
1343
1344 p_ra->pre_ratr_state = p_ra->ratr_state;
1345 }
1346 }
1347 }
1348
1349 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1350 {
1351 struct rtl_priv *rtlpriv = rtl_priv(hw);
1352 struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1353
1354 dm_pstable->pre_ccastate = CCA_MAX;
1355 dm_pstable->cur_ccasate = CCA_MAX;
1356 dm_pstable->pre_rfstate = RF_MAX;
1357 dm_pstable->cur_rfstate = RF_MAX;
1358 dm_pstable->rssi_val_min = 0;
1359 }
1360
1361 static void rtl88e_dm_update_rx_idle_ant(struct ieee80211_hw *hw,
1362 u8 ant)
1363 {
1364 struct rtl_priv *rtlpriv = rtl_priv(hw);
1365 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1366 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1367 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1368 u32 default_ant, optional_ant;
1369
1370 if (pfat_table->rx_idle_ant != ant) {
1371 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1372 "need to update rx idle ant\n");
1373 if (ant == MAIN_ANT) {
1374 default_ant =
1375 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1376 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1377 optional_ant =
1378 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1379 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1380 } else {
1381 default_ant =
1382 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1383 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1384 optional_ant =
1385 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1386 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1387 }
1388
1389 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1390 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1391 BIT(5) | BIT(4) | BIT(3), default_ant);
1392 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1393 BIT(8) | BIT(7) | BIT(6), optional_ant);
1394 rtl_set_bbreg(hw, DM_REG_ANTSEL_CTRL_11N,
1395 BIT(14) | BIT(13) | BIT(12),
1396 default_ant);
1397 rtl_set_bbreg(hw, DM_REG_RESP_TX_11N,
1398 BIT(6) | BIT(7), default_ant);
1399 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1400 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1401 BIT(5) | BIT(4) | BIT(3), default_ant);
1402 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1403 BIT(8) | BIT(7) | BIT(6), optional_ant);
1404 }
1405 }
1406 pfat_table->rx_idle_ant = ant;
1407 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RxIdleAnt %s\n",
1408 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT"));
1409 }
1410
1411 static void rtl88e_dm_update_tx_ant(struct ieee80211_hw *hw,
1412 u8 ant, u32 mac_id)
1413 {
1414 struct rtl_priv *rtlpriv = rtl_priv(hw);
1415 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1416 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1417 u8 target_ant;
1418
1419 if (ant == MAIN_ANT)
1420 target_ant = MAIN_ANT_CG_TRX;
1421 else
1422 target_ant = AUX_ANT_CG_TRX;
1423
1424 pfat_table->antsel_a[mac_id] = target_ant & BIT(0);
1425 pfat_table->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1;
1426 pfat_table->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2;
1427 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "txfrominfo target ant %s\n",
1428 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT"));
1429 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "antsel_tr_mux = 3'b%d%d%d\n",
1430 pfat_table->antsel_c[mac_id],
1431 pfat_table->antsel_b[mac_id],
1432 pfat_table->antsel_a[mac_id]);
1433 }
1434
1435 static void rtl88e_dm_rx_hw_antena_div_init(struct ieee80211_hw *hw)
1436 {
1437 u32 value32;
1438
1439 /*MAC Setting*/
1440 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1441 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N,
1442 MASKDWORD, value32 | (BIT(23) | BIT(25)));
1443 /*Pin Setting*/
1444 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1445 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1446 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1);
1447 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1448 /*OFDM Setting*/
1449 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1450 /*CCK Setting*/
1451 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1452 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1453 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1454 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1455 }
1456
1457 static void rtl88e_dm_trx_hw_antenna_div_init(struct ieee80211_hw *hw)
1458 {
1459 u32 value32;
1460
1461 /*MAC Setting*/
1462 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1463 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD,
1464 value32 | (BIT(23) | BIT(25)));
1465 /*Pin Setting*/
1466 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1467 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1468 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1469 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1470 /*OFDM Setting*/
1471 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1472 /*CCK Setting*/
1473 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1474 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1475 /*TX Setting*/
1476 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
1477 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1478 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1479 }
1480
1481 static void rtl88e_dm_fast_training_init(struct ieee80211_hw *hw)
1482 {
1483 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1484 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1485 u32 ant_combination = 2;
1486 u32 value32, i;
1487
1488 for (i = 0; i < 6; i++) {
1489 pfat_table->bssid[i] = 0;
1490 pfat_table->ant_sum[i] = 0;
1491 pfat_table->ant_cnt[i] = 0;
1492 pfat_table->ant_ave[i] = 0;
1493 }
1494 pfat_table->train_idx = 0;
1495 pfat_table->fat_state = FAT_NORMAL_STATE;
1496
1497 /*MAC Setting*/
1498 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1499 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N,
1500 MASKDWORD, value32 | (BIT(23) | BIT(25)));
1501 value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, MASKDWORD);
1502 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1503 MASKDWORD, value32 | (BIT(16) | BIT(17)));
1504 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1505 MASKLWORD, 0);
1506 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N,
1507 MASKDWORD, 0);
1508
1509 /*Pin Setting*/
1510 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1511 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1512 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1513 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1514
1515 /*OFDM Setting*/
1516 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1517 /*antenna mapping table*/
1518 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1);
1519 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2);
1520
1521 /*TX Setting*/
1522 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1);
1523 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1524 BIT(5) | BIT(4) | BIT(3), 0);
1525 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1526 BIT(8) | BIT(7) | BIT(6), 1);
1527 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1528 BIT(2) | BIT(1) | BIT(0), (ant_combination - 1));
1529
1530 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1531 }
1532
1533 static void rtl88e_dm_antenna_div_init(struct ieee80211_hw *hw)
1534 {
1535 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1536
1537 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1538 rtl88e_dm_rx_hw_antena_div_init(hw);
1539 else if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1540 rtl88e_dm_trx_hw_antenna_div_init(hw);
1541 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1542 rtl88e_dm_fast_training_init(hw);
1543
1544 }
1545
1546 void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
1547 u8 *pdesc, u32 mac_id)
1548 {
1549 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1550 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1551 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1552
1553 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1554 (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)) {
1555 SET_TX_DESC_ANTSEL_A(pdesc, pfat_table->antsel_a[mac_id]);
1556 SET_TX_DESC_ANTSEL_B(pdesc, pfat_table->antsel_b[mac_id]);
1557 SET_TX_DESC_ANTSEL_C(pdesc, pfat_table->antsel_c[mac_id]);
1558 }
1559 }
1560
1561 void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
1562 u8 antsel_tr_mux, u32 mac_id,
1563 u32 rx_pwdb_all)
1564 {
1565 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1566 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1567 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1568
1569 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1570 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
1571 pfat_table->main_ant_sum[mac_id] += rx_pwdb_all;
1572 pfat_table->main_ant_cnt[mac_id]++;
1573 } else {
1574 pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all;
1575 pfat_table->aux_ant_cnt[mac_id]++;
1576 }
1577 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1578 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
1579 pfat_table->main_ant_sum[mac_id] += rx_pwdb_all;
1580 pfat_table->main_ant_cnt[mac_id]++;
1581 } else {
1582 pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all;
1583 pfat_table->aux_ant_cnt[mac_id]++;
1584 }
1585 }
1586 }
1587
1588 static void rtl88e_dm_hw_ant_div(struct ieee80211_hw *hw)
1589 {
1590 struct rtl_priv *rtlpriv = rtl_priv(hw);
1591 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1592 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1593 struct rtl_sta_info *drv_priv;
1594 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1595 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
1596 u32 i, min_rssi = 0xff, ant_div_max_rssi = 0;
1597 u32 max_rssi = 0, local_min_rssi, local_max_rssi;
1598 u32 main_rssi, aux_rssi;
1599 u8 rx_idle_ant = 0, target_ant = 7;
1600
1601 /*for sta its self*/
1602 i = 0;
1603 main_rssi = (pfat_table->main_ant_cnt[i] != 0) ?
1604 (pfat_table->main_ant_sum[i] / pfat_table->main_ant_cnt[i]) : 0;
1605 aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ?
1606 (pfat_table->aux_ant_sum[i] / pfat_table->aux_ant_cnt[i]) : 0;
1607 target_ant = (main_rssi == aux_rssi) ?
1608 pfat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ?
1609 MAIN_ANT : AUX_ANT);
1610 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1611 "main_ant_sum %d main_ant_cnt %d\n",
1612 pfat_table->main_ant_sum[i],
1613 pfat_table->main_ant_cnt[i]);
1614 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1615 "aux_ant_sum %d aux_ant_cnt %d\n",
1616 pfat_table->aux_ant_sum[i], pfat_table->aux_ant_cnt[i]);
1617 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "main_rssi %d aux_rssi%d\n",
1618 main_rssi, aux_rssi);
1619 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
1620 if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40))
1621 ant_div_max_rssi = local_max_rssi;
1622 if (local_max_rssi > max_rssi)
1623 max_rssi = local_max_rssi;
1624
1625 if ((pfat_table->rx_idle_ant == MAIN_ANT) && (main_rssi == 0))
1626 main_rssi = aux_rssi;
1627 else if ((pfat_table->rx_idle_ant == AUX_ANT) && (aux_rssi == 0))
1628 aux_rssi = main_rssi;
1629
1630 local_min_rssi = (main_rssi > aux_rssi) ? aux_rssi : main_rssi;
1631 if (local_min_rssi < min_rssi) {
1632 min_rssi = local_min_rssi;
1633 rx_idle_ant = target_ant;
1634 }
1635 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1636 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1637
1638 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1639 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) {
1640 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1641 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1642 i++;
1643 main_rssi = (pfat_table->main_ant_cnt[i] != 0) ?
1644 (pfat_table->main_ant_sum[i] /
1645 pfat_table->main_ant_cnt[i]) : 0;
1646 aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ?
1647 (pfat_table->aux_ant_sum[i] /
1648 pfat_table->aux_ant_cnt[i]) : 0;
1649 target_ant = (main_rssi == aux_rssi) ?
1650 pfat_table->rx_idle_ant : ((main_rssi >=
1651 aux_rssi) ? MAIN_ANT : AUX_ANT);
1652
1653 local_max_rssi = (main_rssi > aux_rssi) ?
1654 main_rssi : aux_rssi;
1655 if ((local_max_rssi > ant_div_max_rssi) &&
1656 (local_max_rssi < 40))
1657 ant_div_max_rssi = local_max_rssi;
1658 if (local_max_rssi > max_rssi)
1659 max_rssi = local_max_rssi;
1660
1661 if ((pfat_table->rx_idle_ant == MAIN_ANT) &&
1662 (main_rssi == 0))
1663 main_rssi = aux_rssi;
1664 else if ((pfat_table->rx_idle_ant == AUX_ANT) &&
1665 (aux_rssi == 0))
1666 aux_rssi = main_rssi;
1667
1668 local_min_rssi = (main_rssi > aux_rssi) ?
1669 aux_rssi : main_rssi;
1670 if (local_min_rssi < min_rssi) {
1671 min_rssi = local_min_rssi;
1672 rx_idle_ant = target_ant;
1673 }
1674 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1675 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1676 }
1677 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1678 }
1679
1680 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1681 pfat_table->main_ant_sum[i] = 0;
1682 pfat_table->aux_ant_sum[i] = 0;
1683 pfat_table->main_ant_cnt[i] = 0;
1684 pfat_table->aux_ant_cnt[i] = 0;
1685 }
1686
1687 rtl88e_dm_update_rx_idle_ant(hw, rx_idle_ant);
1688
1689 dm_dig->antdiv_rssi_max = ant_div_max_rssi;
1690 dm_dig->rssi_max = max_rssi;
1691 }
1692
1693 static void rtl88e_set_next_mac_address_target(struct ieee80211_hw *hw)
1694 {
1695 struct rtl_priv *rtlpriv = rtl_priv(hw);
1696 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1697 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1698 struct rtl_sta_info *drv_priv;
1699 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1700 u32 value32, i, j = 0;
1701
1702 if (mac->link_state >= MAC80211_LINKED) {
1703 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1704 if ((pfat_table->train_idx + 1) == ASSOCIATE_ENTRY_NUM)
1705 pfat_table->train_idx = 0;
1706 else
1707 pfat_table->train_idx++;
1708
1709 if (pfat_table->train_idx == 0) {
1710 value32 = (mac->mac_addr[5] << 8) |
1711 mac->mac_addr[4];
1712 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1713 MASKLWORD, value32);
1714
1715 value32 = (mac->mac_addr[3] << 24) |
1716 (mac->mac_addr[2] << 16) |
1717 (mac->mac_addr[1] << 8) |
1718 mac->mac_addr[0];
1719 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N,
1720 MASKDWORD, value32);
1721 break;
1722 }
1723
1724 if (rtlpriv->mac80211.opmode !=
1725 NL80211_IFTYPE_STATION) {
1726 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1727 list_for_each_entry(drv_priv,
1728 &rtlpriv->entry_list, list) {
1729 j++;
1730 if (j != pfat_table->train_idx)
1731 continue;
1732
1733 value32 = (drv_priv->mac_addr[5] << 8) |
1734 drv_priv->mac_addr[4];
1735 rtl_set_bbreg(hw,
1736 DM_REG_ANT_TRAIN_PARA2_11N,
1737 MASKLWORD, value32);
1738
1739 value32 = (drv_priv->mac_addr[3] << 24) |
1740 (drv_priv->mac_addr[2] << 16) |
1741 (drv_priv->mac_addr[1] << 8) |
1742 drv_priv->mac_addr[0];
1743 rtl_set_bbreg(hw,
1744 DM_REG_ANT_TRAIN_PARA1_11N,
1745 MASKDWORD, value32);
1746 break;
1747 }
1748 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1749 /*find entry, break*/
1750 if (j == pfat_table->train_idx)
1751 break;
1752 }
1753 }
1754 }
1755 }
1756
1757 static void rtl88e_dm_fast_ant_training(struct ieee80211_hw *hw)
1758 {
1759 struct rtl_priv *rtlpriv = rtl_priv(hw);
1760 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1761 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1762 u32 i, max_rssi = 0;
1763 u8 target_ant = 2;
1764 bool bpkt_filter_match = false;
1765
1766 if (pfat_table->fat_state == FAT_TRAINING_STATE) {
1767 for (i = 0; i < 7; i++) {
1768 if (pfat_table->ant_cnt[i] == 0) {
1769 pfat_table->ant_ave[i] = 0;
1770 } else {
1771 pfat_table->ant_ave[i] =
1772 pfat_table->ant_sum[i] /
1773 pfat_table->ant_cnt[i];
1774 bpkt_filter_match = true;
1775 }
1776
1777 if (pfat_table->ant_ave[i] > max_rssi) {
1778 max_rssi = pfat_table->ant_ave[i];
1779 target_ant = (u8) i;
1780 }
1781 }
1782
1783 if (bpkt_filter_match == false) {
1784 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1785 BIT(16), 0);
1786 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1787 } else {
1788 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1789 BIT(16), 0);
1790 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) |
1791 BIT(7) | BIT(6), target_ant);
1792 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1793 BIT(21), 1);
1794
1795 pfat_table->antsel_a[pfat_table->train_idx] =
1796 target_ant & BIT(0);
1797 pfat_table->antsel_b[pfat_table->train_idx] =
1798 (target_ant & BIT(1)) >> 1;
1799 pfat_table->antsel_c[pfat_table->train_idx] =
1800 (target_ant & BIT(2)) >> 2;
1801
1802 if (target_ant == 0)
1803 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1804 }
1805
1806 for (i = 0; i < 7; i++) {
1807 pfat_table->ant_sum[i] = 0;
1808 pfat_table->ant_cnt[i] = 0;
1809 }
1810
1811 pfat_table->fat_state = FAT_NORMAL_STATE;
1812 return;
1813 }
1814
1815 if (pfat_table->fat_state == FAT_NORMAL_STATE) {
1816 rtl88e_set_next_mac_address_target(hw);
1817
1818 pfat_table->fat_state = FAT_TRAINING_STATE;
1819 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1);
1820 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1821
1822 mod_timer(&rtlpriv->works.fast_antenna_training_timer,
1823 jiffies + MSECS(RTL_WATCH_DOG_TIME));
1824 }
1825 }
1826
1827 void rtl88e_dm_fast_antenna_training_callback(unsigned long data)
1828 {
1829 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1830
1831 rtl88e_dm_fast_ant_training(hw);
1832 }
1833
1834 static void rtl88e_dm_antenna_diversity(struct ieee80211_hw *hw)
1835 {
1836 struct rtl_priv *rtlpriv = rtl_priv(hw);
1837 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1838 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1839 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1840 struct fast_ant_training *pfat_table = &rtldm->fat_table;
1841
1842 if (mac->link_state < MAC80211_LINKED) {
1843 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "No Link\n");
1844 if (pfat_table->becomelinked) {
1845 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1846 "need to turn off HW AntDiv\n");
1847 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1848 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1849 BIT(15), 0);
1850 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1851 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1852 BIT(21), 0);
1853 pfat_table->becomelinked =
1854 (mac->link_state == MAC80211_LINKED) ?
1855 true : false;
1856 }
1857 return;
1858 } else {
1859 if (!pfat_table->becomelinked) {
1860 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1861 "Need to turn on HW AntDiv\n");
1862 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1863 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1864 BIT(15), 1);
1865 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1866 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1867 BIT(21), 1);
1868 pfat_table->becomelinked =
1869 (mac->link_state >= MAC80211_LINKED) ?
1870 true : false;
1871 }
1872 }
1873
1874 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1875 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV))
1876 rtl88e_dm_hw_ant_div(hw);
1877 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1878 rtl88e_dm_fast_ant_training(hw);
1879 }
1880
1881 void rtl88e_dm_init(struct ieee80211_hw *hw)
1882 {
1883 struct rtl_priv *rtlpriv = rtl_priv(hw);
1884 u32 cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
1885
1886 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1887 rtl_dm_diginit(hw, cur_igvalue);
1888 rtl88e_dm_init_dynamic_txpower(hw);
1889 rtl88e_dm_init_edca_turbo(hw);
1890 rtl88e_dm_init_rate_adaptive_mask(hw);
1891 rtl88e_dm_init_txpower_tracking(hw);
1892 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1893 rtl88e_dm_antenna_div_init(hw);
1894 }
1895
1896 void rtl88e_dm_watchdog(struct ieee80211_hw *hw)
1897 {
1898 struct rtl_priv *rtlpriv = rtl_priv(hw);
1899 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1900 bool fw_current_inpsmode = false;
1901 bool fw_ps_awake = true;
1902
1903 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1904 (u8 *)(&fw_current_inpsmode));
1905 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1906 (u8 *)(&fw_ps_awake));
1907 if (ppsc->p2p_ps_info.p2p_ps_mode)
1908 fw_ps_awake = false;
1909
1910 if ((ppsc->rfpwr_state == ERFON) &&
1911 ((!fw_current_inpsmode) && fw_ps_awake) &&
1912 (!ppsc->rfchange_inprogress)) {
1913 rtl88e_dm_pwdb_monitor(hw);
1914 rtl88e_dm_dig(hw);
1915 rtl88e_dm_false_alarm_counter_statistics(hw);
1916 rtl92c_dm_dynamic_txpower(hw);
1917 rtl88e_dm_check_txpower_tracking(hw);
1918 rtl88e_dm_refresh_rate_adaptive_mask(hw);
1919 rtl88e_dm_check_edca_turbo(hw);
1920 rtl88e_dm_antenna_diversity(hw);
1921 }
1922 }
1923
1924 #line 117 "/work/ldvuser/andrianov/work/current--X--drivers/net/wireless/--X--defaultlinux-4.5-rc7--X--races--X--cpachecker/linux-4.5-rc7/csd_deg_dscv/376/dscv_tempdir/dscv/ri/races/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.o.c.prepared" 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../pci.h"
28 #include "../base.h"
29 #include "../core.h"
30 #include "reg.h"
31 #include "def.h"
32 #include "fw.h"
33
34 static void _rtl88e_enable_fw_download(struct ieee80211_hw *hw, bool enable)
35 {
36 struct rtl_priv *rtlpriv = rtl_priv(hw);
37 u8 tmp;
38
39 if (enable) {
40 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
41 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
42
43 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
44 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
45
46 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
47 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
48 } else {
49 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
50 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
51
52 rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
53 }
54 }
55
56 static void _rtl88e_fw_block_write(struct ieee80211_hw *hw,
57 const u8 *buffer, u32 size)
58 {
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
60 u32 blocksize = sizeof(u32);
61 u8 *bufferptr = (u8 *)buffer;
62 u32 *pu4BytePtr = (u32 *)buffer;
63 u32 i, offset, blockcount, remainsize;
64
65 blockcount = size / blocksize;
66 remainsize = size % blocksize;
67
68 for (i = 0; i < blockcount; i++) {
69 offset = i * blocksize;
70 rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
71 *(pu4BytePtr + i));
72 }
73
74 if (remainsize) {
75 offset = blockcount * blocksize;
76 bufferptr += offset;
77 for (i = 0; i < remainsize; i++) {
78 rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
79 offset + i), *(bufferptr + i));
80 }
81 }
82 }
83
84 static void _rtl88e_fw_page_write(struct ieee80211_hw *hw,
85 u32 page, const u8 *buffer, u32 size)
86 {
87 struct rtl_priv *rtlpriv = rtl_priv(hw);
88 u8 value8;
89 u8 u8page = (u8) (page & 0x07);
90
91 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
92
93 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
94 _rtl88e_fw_block_write(hw, buffer, size);
95 }
96
97 static void _rtl88e_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
98 {
99 u32 fwlen = *pfwlen;
100 u8 remain = (u8) (fwlen % 4);
101
102 remain = (remain == 0) ? 0 : (4 - remain);
103
104 while (remain > 0) {
105 pfwbuf[fwlen] = 0;
106 fwlen++;
107 remain--;
108 }
109
110 *pfwlen = fwlen;
111 }
112
113 static void _rtl88e_write_fw(struct ieee80211_hw *hw,
114 enum version_8188e version, u8 *buffer, u32 size)
115 {
116 struct rtl_priv *rtlpriv = rtl_priv(hw);
117 u8 *bufferptr = (u8 *)buffer;
118 u32 pagenums, remainsize;
119 u32 page, offset;
120
121 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
122
123 _rtl88e_fill_dummy(bufferptr, &size);
124
125 pagenums = size / FW_8192C_PAGE_SIZE;
126 remainsize = size % FW_8192C_PAGE_SIZE;
127
128 if (pagenums > 8) {
129 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
130 "Page numbers should not greater then 8\n");
131 }
132
133 for (page = 0; page < pagenums; page++) {
134 offset = page * FW_8192C_PAGE_SIZE;
135 _rtl88e_fw_page_write(hw, page, (bufferptr + offset),
136 FW_8192C_PAGE_SIZE);
137 }
138
139 if (remainsize) {
140 offset = pagenums * FW_8192C_PAGE_SIZE;
141 page = pagenums;
142 _rtl88e_fw_page_write(hw, page, (bufferptr + offset),
143 remainsize);
144 }
145 }
146
147 static int _rtl88e_fw_free_to_go(struct ieee80211_hw *hw)
148 {
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 int err = -EIO;
151 u32 counter = 0;
152 u32 value32;
153
154 do {
155 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
156 } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
157 (!(value32 & FWDL_CHKSUM_RPT)));
158
159 if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
161 "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
162 value32);
163 goto exit;
164 }
165
166 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
167 "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
168
169 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
170 value32 |= MCUFWDL_RDY;
171 value32 &= ~WINTINI_RDY;
172 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
173
174 rtl88e_firmware_selfreset(hw);
175 counter = 0;
176
177 do {
178 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
179 if (value32 & WINTINI_RDY) {
180 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
181 "Polling FW ready success!! REG_MCUFWDL:0x%08x.\n",
182 value32);
183 err = 0;
184 goto exit;
185 }
186
187 udelay(FW_8192C_POLLING_DELAY);
188
189 } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
190
191 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
192 "Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32);
193
194 exit:
195 return err;
196 }
197
198 int rtl88e_download_fw(struct ieee80211_hw *hw,
199 bool buse_wake_on_wlan_fw)
200 {
201 struct rtl_priv *rtlpriv = rtl_priv(hw);
202 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
203 struct rtlwifi_firmware_header *pfwheader;
204 u8 *pfwdata;
205 u32 fwsize;
206 int err;
207 enum version_8188e version = rtlhal->version;
208
209 if (!rtlhal->pfirmware)
210 return 1;
211
212 pfwheader = (struct rtlwifi_firmware_header *)rtlhal->pfirmware;
213 pfwdata = rtlhal->pfirmware;
214 fwsize = rtlhal->fwsize;
215 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
216 "normal Firmware SIZE %d\n", fwsize);
217
218 if (IS_FW_HEADER_EXIST(pfwheader)) {
219 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
220 "Firmware Version(%d), Signature(%#x), Size(%d)\n",
221 pfwheader->version, pfwheader->signature,
222 (int)sizeof(struct rtlwifi_firmware_header));
223
224 pfwdata = pfwdata + sizeof(struct rtlwifi_firmware_header);
225 fwsize = fwsize - sizeof(struct rtlwifi_firmware_header);
226 }
227
228 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
229 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
230 rtl88e_firmware_selfreset(hw);
231 }
232 _rtl88e_enable_fw_download(hw, true);
233 _rtl88e_write_fw(hw, version, pfwdata, fwsize);
234 _rtl88e_enable_fw_download(hw, false);
235
236 err = _rtl88e_fw_free_to_go(hw);
237 if (err) {
238 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
239 "Firmware is not ready to run!\n");
240 } else {
241 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
242 "Firmware is ready to run!\n");
243 }
244
245 return 0;
246 }
247
248 static bool _rtl88e_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
249 {
250 struct rtl_priv *rtlpriv = rtl_priv(hw);
251 u8 val_hmetfr;
252
253 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
254 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
255 return true;
256 return false;
257 }
258
259 static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
260 u8 element_id, u32 cmd_len,
261 u8 *cmd_b)
262 {
263 struct rtl_priv *rtlpriv = rtl_priv(hw);
264 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
265 u8 boxnum;
266 u16 box_reg = 0, box_extreg = 0;
267 u8 u1b_tmp;
268 bool isfw_read = false;
269 u8 buf_index = 0;
270 bool write_sucess = false;
271 u8 wait_h2c_limmit = 100;
272 u8 wait_writeh2c_limit = 100;
273 u8 boxcontent[4], boxextcontent[4];
274 u32 h2c_waitcounter = 0;
275 unsigned long flag;
276 u8 idx;
277
278 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
279
280 while (true) {
281 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
282 if (rtlhal->h2c_setinprogress) {
283 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
284 "H2C set in progress! Wait to set..element_id(%d).\n",
285 element_id);
286
287 while (rtlhal->h2c_setinprogress) {
288 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
289 flag);
290 h2c_waitcounter++;
291 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
292 "Wait 100 us (%d times)...\n",
293 h2c_waitcounter);
294 udelay(100);
295
296 if (h2c_waitcounter > 1000)
297 return;
298 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
299 flag);
300 }
301 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
302 } else {
303 rtlhal->h2c_setinprogress = true;
304 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
305 break;
306 }
307 }
308
309 while (!write_sucess) {
310 wait_writeh2c_limit--;
311 if (wait_writeh2c_limit == 0) {
312 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
313 "Write H2C fail because no trigger for FW INT!\n");
314 break;
315 }
316
317 boxnum = rtlhal->last_hmeboxnum;
318 switch (boxnum) {
319 case 0:
320 box_reg = REG_HMEBOX_0;
321 box_extreg = REG_HMEBOX_EXT_0;
322 break;
323 case 1:
324 box_reg = REG_HMEBOX_1;
325 box_extreg = REG_HMEBOX_EXT_1;
326 break;
327 case 2:
328 box_reg = REG_HMEBOX_2;
329 box_extreg = REG_HMEBOX_EXT_2;
330 break;
331 case 3:
332 box_reg = REG_HMEBOX_3;
333 box_extreg = REG_HMEBOX_EXT_3;
334 break;
335 default:
336 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
337 "switch case not process\n");
338 break;
339 }
340 isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
341 while (!isfw_read) {
342 wait_h2c_limmit--;
343 if (wait_h2c_limmit == 0) {
344 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
345 "Waiting too long for FW read clear HMEBox(%d)!\n",
346 boxnum);
347 break;
348 }
349
350 udelay(10);
351
352 isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
353 u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
354 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
355 "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
356 boxnum, u1b_tmp);
357 }
358
359 if (!isfw_read) {
360 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
361 "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
362 boxnum);
363 break;
364 }
365
366 memset(boxcontent, 0, sizeof(boxcontent));
367 memset(boxextcontent, 0, sizeof(boxextcontent));
368 boxcontent[0] = element_id;
369 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
370 "Write element_id box_reg(%4x) = %2x\n",
371 box_reg, element_id);
372
373 switch (cmd_len) {
374 case 1:
375 case 2:
376 case 3:
377 /*boxcontent[0] &= ~(BIT(7));*/
378 memcpy((u8 *)(boxcontent) + 1,
379 cmd_b + buf_index, cmd_len);
380
381 for (idx = 0; idx < 4; idx++) {
382 rtl_write_byte(rtlpriv, box_reg + idx,
383 boxcontent[idx]);
384 }
385 break;
386 case 4:
387 case 5:
388 case 6:
389 case 7:
390 /*boxcontent[0] |= (BIT(7));*/
391 memcpy((u8 *)(boxextcontent),
392 cmd_b + buf_index+3, cmd_len-3);
393 memcpy((u8 *)(boxcontent) + 1,
394 cmd_b + buf_index, 3);
395
396 for (idx = 0; idx < 2; idx++) {
397 rtl_write_byte(rtlpriv, box_extreg + idx,
398 boxextcontent[idx]);
399 }
400
401 for (idx = 0; idx < 4; idx++) {
402 rtl_write_byte(rtlpriv, box_reg + idx,
403 boxcontent[idx]);
404 }
405 break;
406 default:
407 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
408 "switch case not process\n");
409 break;
410 }
411
412 write_sucess = true;
413
414 rtlhal->last_hmeboxnum = boxnum + 1;
415 if (rtlhal->last_hmeboxnum == 4)
416 rtlhal->last_hmeboxnum = 0;
417
418 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
419 "pHalData->last_hmeboxnum = %d\n",
420 rtlhal->last_hmeboxnum);
421 }
422
423 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
424 rtlhal->h2c_setinprogress = false;
425 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
426
427 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
428 }
429
430 void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw,
431 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
432 {
433 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
434 u32 tmp_cmdbuf[2];
435
436 if (!rtlhal->fw_ready) {
437 RT_ASSERT(false,
438 "return H2C cmd because of Fw download fail!!!\n");
439 return;
440 }
441
442 memset(tmp_cmdbuf, 0, 8);
443 memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
444 _rtl88e_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
445
446 return;
447 }
448
449 void rtl88e_firmware_selfreset(struct ieee80211_hw *hw)
450 {
451 u8 u1b_tmp;
452 struct rtl_priv *rtlpriv = rtl_priv(hw);
453
454 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
455 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
456 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
457 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
458 "8051Reset88E(): 8051 reset success\n");
459
460 }
461
462 void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
463 {
464 struct rtl_priv *rtlpriv = rtl_priv(hw);
465 u8 u1_h2c_set_pwrmode[H2C_88E_PWEMODE_LENGTH] = { 0 };
466 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
467 u8 rlbm, power_state = 0;
468 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
469
470 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
471 rlbm = 0;/*YJ, temp, 120316. FW now not support RLBM=2.*/
472 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
473 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
474 (rtlpriv->mac80211.p2p) ? ppsc->smart_ps : 1);
475 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
476 ppsc->reg_max_lps_awakeintvl);
477 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
478 if (mode == FW_PS_ACTIVE_MODE)
479 power_state |= FW_PWR_STATE_ACTIVE;
480 else
481 power_state |= FW_PWR_STATE_RF_OFF;
482
483 SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
484
485 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
486 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
487 u1_h2c_set_pwrmode, H2C_88E_PWEMODE_LENGTH);
488 rtl88e_fill_h2c_cmd(hw, H2C_88E_SETPWRMODE,
489 H2C_88E_PWEMODE_LENGTH, u1_h2c_set_pwrmode);
490 }
491
492 void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
493 {
494 u8 u1_joinbssrpt_parm[1] = { 0 };
495
496 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
497
498 rtl88e_fill_h2c_cmd(hw, H2C_88E_JOINBSSRPT, 1, u1_joinbssrpt_parm);
499 }
500
501 void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
502 u8 ap_offload_enable)
503 {
504 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
505 u8 u1_apoffload_parm[H2C_88E_AP_OFFLOAD_LENGTH] = { 0 };
506
507 SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
508 SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
509 SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
510
511 rtl88e_fill_h2c_cmd(hw, H2C_88E_AP_OFFLOAD,
512 H2C_88E_AP_OFFLOAD_LENGTH, u1_apoffload_parm);
513
514 }
515
516 #define BEACON_PG 0 /* ->1 */
517 #define PSPOLL_PG 2
518 #define NULL_PG 3
519 #define PROBERSP_PG 4 /* ->5 */
520
521 #define TOTAL_RESERVED_PKT_LEN 768
522
523 static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
524 /* page 0 beacon */
525 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
526 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
527 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
528 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
529 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
530 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
531 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
532 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
533 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
534 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
535 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
536 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
537 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
538 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
539 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
540 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
541
542 /* page 1 beacon */
543 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
544 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
546 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
547 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
548 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
549 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
552 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
553 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
554 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
555 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
557 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
559
560 /* page 2 ps-poll */
561 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
562 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
563 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
564 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
566 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
567 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
568 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
569 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
570 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
571 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
572 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
573 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
574 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
575 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
576 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
577
578 /* page 3 null */
579 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
580 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
581 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
582 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
583 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
584 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
586 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
587 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
588 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
589 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
590 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
591 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
592 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
593 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
594 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
595
596 /* page 4 probe_resp */
597 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
598 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
599 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
600 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
601 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
602 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
603 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
604 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
605 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
606 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
607 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
608 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
609 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
610 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
611 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
612 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
613
614 /* page 5 probe_resp */
615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
617 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
618 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
619 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
620 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
621 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
624 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
626 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
628 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631 };
632
633 void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
634 {
635 struct rtl_priv *rtlpriv = rtl_priv(hw);
636 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
637 struct sk_buff *skb = NULL;
638 u32 totalpacketlen;
639 bool rtstatus;
640 u8 u1rsvdpageloc[5] = { 0 };
641 bool b_dlok = false;
642 u8 *beacon;
643 u8 *p_pspoll;
644 u8 *nullfunc;
645 u8 *p_probersp;
646
647 /*---------------------------------------------------------
648 * (1) beacon
649 *---------------------------------------------------------
650 */
651 beacon = &reserved_page_packet[BEACON_PG * 128];
652 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
653 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
654
655 /*-------------------------------------------------------
656 * (2) ps-poll
657 *--------------------------------------------------------
658 */
659 p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
660 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
661 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
662 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
663
664 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
665
666 /*--------------------------------------------------------
667 * (3) null data
668 *---------------------------------------------------------
669 */
670 nullfunc = &reserved_page_packet[NULL_PG * 128];
671 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
672 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
673 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
674
675 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
676
677 /*---------------------------------------------------------
678 * (4) probe response
679 *----------------------------------------------------------
680 */
681 p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
682 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
683 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
684 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
685
686 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
687
688 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
689
690 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
691 "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
692 &reserved_page_packet[0], totalpacketlen);
693 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
694 "rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
695 u1rsvdpageloc, 3);
696
697 skb = dev_alloc_skb(totalpacketlen);
698 memcpy(skb_put(skb, totalpacketlen),
699 &reserved_page_packet, totalpacketlen);
700
701 rtstatus = rtl_cmd_send_packet(hw, skb);
702
703 if (rtstatus)
704 b_dlok = true;
705
706 if (b_dlok) {
707 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
708 "Set RSVD page location to Fw.\n");
709 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
710 "H2C_RSVDPAGE:\n", u1rsvdpageloc, 3);
711 rtl88e_fill_h2c_cmd(hw, H2C_88E_RSVDPAGE,
712 sizeof(u1rsvdpageloc), u1rsvdpageloc);
713 } else
714 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
715 "Set RSVD page location to Fw FAIL!!!!!!.\n");
716 }
717
718 /*Should check FW support p2p or not.*/
719 static void rtl88e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
720 {
721 u8 u1_ctwindow_period[1] = { ctwindow};
722
723 rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
724
725 }
726
727 void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
728 {
729 struct rtl_priv *rtlpriv = rtl_priv(hw);
730 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
731 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
732 struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
733 struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
734 u8 i;
735 u16 ctwindow;
736 u32 start_time, tsf_low;
737
738 switch (p2p_ps_state) {
739 case P2P_PS_DISABLE:
740 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
741 memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
742 break;
743 case P2P_PS_ENABLE:
744 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
745 /* update CTWindow value. */
746 if (p2pinfo->ctwindow > 0) {
747 p2p_ps_offload->ctwindow_en = 1;
748 ctwindow = p2pinfo->ctwindow;
749 rtl88e_set_p2p_ctw_period_cmd(hw, ctwindow);
750 }
751
752 /* hw only support 2 set of NoA */
753 for (i = 0 ; i < p2pinfo->noa_num; i++) {
754 /* To control the register setting for which NOA*/
755 rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
756 if (i == 0)
757 p2p_ps_offload->noa0_en = 1;
758 else
759 p2p_ps_offload->noa1_en = 1;
760
761 /* config P2P NoA Descriptor Register */
762 rtl_write_dword(rtlpriv, 0x5E0,
763 p2pinfo->noa_duration[i]);
764 rtl_write_dword(rtlpriv, 0x5E4,
765 p2pinfo->noa_interval[i]);
766
767 /*Get Current TSF value */
768 tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
769
770 start_time = p2pinfo->noa_start_time[i];
771 if (p2pinfo->noa_count_type[i] != 1) {
772 while (start_time <= (tsf_low+(50*1024))) {
773 start_time += p2pinfo->noa_interval[i];
774 if (p2pinfo->noa_count_type[i] != 255)
775 p2pinfo->noa_count_type[i]--;
776 }
777 }
778 rtl_write_dword(rtlpriv, 0x5E8, start_time);
779 rtl_write_dword(rtlpriv, 0x5EC,
780 p2pinfo->noa_count_type[i]);
781 }
782
783 if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
784 /* rst p2p circuit */
785 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
786
787 p2p_ps_offload->offload_en = 1;
788
789 if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
790 p2p_ps_offload->role = 1;
791 p2p_ps_offload->allstasleep = -1;
792 } else {
793 p2p_ps_offload->role = 0;
794 }
795
796 p2p_ps_offload->discovery = 0;
797 }
798 break;
799 case P2P_PS_SCAN:
800 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
801 p2p_ps_offload->discovery = 1;
802 break;
803 case P2P_PS_SCAN_DONE:
804 RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
805 p2p_ps_offload->discovery = 0;
806 p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
807 break;
808 default:
809 break;
810 }
811
812 rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_OFFLOAD, 1,
813 (u8 *)p2p_ps_offload);
814
815 } 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../efuse.h"
28 #include "../base.h"
29 #include "../regd.h"
30 #include "../cam.h"
31 #include "../ps.h"
32 #include "../pci.h"
33 #include "../pwrseqcmd.h"
34 #include "reg.h"
35 #include "def.h"
36 #include "phy.h"
37 #include "dm.h"
38 #include "fw.h"
39 #include "led.h"
40 #include "hw.h"
41 #include "pwrseq.h"
42
43 #define LLT_CONFIG 5
44
45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
46 u8 set_bits, u8 clear_bits)
47 {
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50
51 rtlpci->reg_bcn_ctrl_val |= set_bits;
52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
53
54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
55 }
56
57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
58 {
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
60 u8 tmp1byte;
61
62 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
65 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
66 tmp1byte &= ~(BIT(0));
67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
68 }
69
70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
71 {
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 u8 tmp1byte;
74
75 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
78 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
79 tmp1byte |= BIT(0);
80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
81 }
82
83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
84 {
85 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
86 }
87
88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
89 {
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
93 unsigned long flags;
94
95 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
96 while (skb_queue_len(&ring->queue)) {
97 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
98 struct sk_buff *skb = __skb_dequeue(&ring->queue);
99
100 pci_unmap_single(rtlpci->pdev,
101 rtlpriv->cfg->ops->get_desc(
102 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
103 skb->len, PCI_DMA_TODEVICE);
104 kfree_skb(skb);
105 ring->idx = (ring->idx + 1) % ring->entries;
106 }
107 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
108 }
109
110 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
111 {
112 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
113 }
114
115 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
116 u8 rpwm_val, bool b_need_turn_off_ckk)
117 {
118 struct rtl_priv *rtlpriv = rtl_priv(hw);
119 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
120 bool b_support_remote_wake_up;
121 u32 count = 0, isr_regaddr, content;
122 bool schedule_timer = b_need_turn_off_ckk;
123 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
124 (u8 *)(&b_support_remote_wake_up));
125
126 if (!rtlhal->fw_ready)
127 return;
128 if (!rtlpriv->psc.fw_current_inpsmode)
129 return;
130
131 while (1) {
132 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
133 if (rtlhal->fw_clk_change_in_progress) {
134 while (rtlhal->fw_clk_change_in_progress) {
135 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
136 count++;
137 udelay(100);
138 if (count > 1000)
139 return;
140 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
141 }
142 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
143 } else {
144 rtlhal->fw_clk_change_in_progress = false;
145 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
146 break;
147 }
148 }
149
150 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
151 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
152 if (FW_PS_IS_ACK(rpwm_val)) {
153 isr_regaddr = REG_HISR;
154 content = rtl_read_dword(rtlpriv, isr_regaddr);
155 while (!(content & IMR_CPWM) && (count < 500)) {
156 udelay(50);
157 count++;
158 content = rtl_read_dword(rtlpriv, isr_regaddr);
159 }
160
161 if (content & IMR_CPWM) {
162 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
163 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
164 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
165 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
166 rtlhal->fw_ps_state);
167 }
168 }
169
170 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
171 rtlhal->fw_clk_change_in_progress = false;
172 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
173 if (schedule_timer) {
174 mod_timer(&rtlpriv->works.fw_clockoff_timer,
175 jiffies + MSECS(10));
176 }
177
178 } else {
179 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
180 rtlhal->fw_clk_change_in_progress = false;
181 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
182 }
183 }
184
185 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
186 u8 rpwm_val)
187 {
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
191 struct rtl8192_tx_ring *ring;
192 enum rf_pwrstate rtstate;
193 bool schedule_timer = false;
194 u8 queue;
195
196 if (!rtlhal->fw_ready)
197 return;
198 if (!rtlpriv->psc.fw_current_inpsmode)
199 return;
200 if (!rtlhal->allow_sw_to_change_hwclc)
201 return;
202 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
203 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
204 return;
205
206 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
207 ring = &rtlpci->tx_ring[queue];
208 if (skb_queue_len(&ring->queue)) {
209 schedule_timer = true;
210 break;
211 }
212 }
213
214 if (schedule_timer) {
215 mod_timer(&rtlpriv->works.fw_clockoff_timer,
216 jiffies + MSECS(10));
217 return;
218 }
219
220 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
221 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
222 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
223 if (!rtlhal->fw_clk_change_in_progress) {
224 rtlhal->fw_clk_change_in_progress = true;
225 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
226 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
227 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
228 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
229 &rpwm_val);
230 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
231 rtlhal->fw_clk_change_in_progress = false;
232 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
233 } else {
234 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
235 mod_timer(&rtlpriv->works.fw_clockoff_timer,
236 jiffies + MSECS(10));
237 }
238 }
239 }
240
241 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
242 {
243 u8 rpwm_val = 0;
244
245 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
246 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
247 }
248
249 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
250 {
251 u8 rpwm_val = 0;
252 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
253 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
254 }
255 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
256 {
257 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
258
259 _rtl88ee_set_fw_ps_rf_off_low_power(hw);
260 }
261
262 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
263 {
264 struct rtl_priv *rtlpriv = rtl_priv(hw);
265 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
267 bool fw_current_inps = false;
268 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
269
270 if (ppsc->low_power_enable) {
271 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
272 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
273 rtlhal->allow_sw_to_change_hwclc = false;
274 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
275 &fw_pwrmode);
276 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
277 (u8 *)(&fw_current_inps));
278 } else {
279 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */
280 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
282 &fw_pwrmode);
283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
284 (u8 *)(&fw_current_inps));
285 }
286 }
287
288 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
289 {
290 struct rtl_priv *rtlpriv = rtl_priv(hw);
291 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
292 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
293 bool fw_current_inps = true;
294 u8 rpwm_val;
295
296 if (ppsc->low_power_enable) {
297 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */
298 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
299 (u8 *)(&fw_current_inps));
300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
301 &ppsc->fwctrl_psmode);
302 rtlhal->allow_sw_to_change_hwclc = true;
303 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
304 } else {
305 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */
306 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
307 (u8 *)(&fw_current_inps));
308 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
309 &ppsc->fwctrl_psmode);
310 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
311 }
312 }
313
314 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
315 {
316 struct rtl_priv *rtlpriv = rtl_priv(hw);
317 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
318 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
319
320 switch (variable) {
321 case HW_VAR_RCR:
322 *((u32 *)(val)) = rtlpci->receive_config;
323 break;
324 case HW_VAR_RF_STATE:
325 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
326 break;
327 case HW_VAR_FWLPS_RF_ON:{
328 enum rf_pwrstate rfstate;
329 u32 val_rcr;
330
331 rtlpriv->cfg->ops->get_hw_reg(hw,
332 HW_VAR_RF_STATE,
333 (u8 *)(&rfstate));
334 if (rfstate == ERFOFF) {
335 *((bool *)(val)) = true;
336 } else {
337 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
338 val_rcr &= 0x00070000;
339 if (val_rcr)
340 *((bool *)(val)) = false;
341 else
342 *((bool *)(val)) = true;
343 }
344 break; }
345 case HW_VAR_FW_PSMODE_STATUS:
346 *((bool *)(val)) = ppsc->fw_current_inpsmode;
347 break;
348 case HW_VAR_CORRECT_TSF:{
349 u64 tsf;
350 u32 *ptsf_low = (u32 *)&tsf;
351 u32 *ptsf_high = ((u32 *)&tsf) + 1;
352
353 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
354 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
355
356 *((u64 *)(val)) = tsf;
357 break; }
358 default:
359 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
360 "switch case not process %x\n", variable);
361 break;
362 }
363 }
364
365 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
366 {
367 struct rtl_priv *rtlpriv = rtl_priv(hw);
368 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
369 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
370 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
371 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
372 u8 idx;
373
374 switch (variable) {
375 case HW_VAR_ETHER_ADDR:
376 for (idx = 0; idx < ETH_ALEN; idx++) {
377 rtl_write_byte(rtlpriv, (REG_MACID + idx),
378 val[idx]);
379 }
380 break;
381 case HW_VAR_BASIC_RATE:{
382 u16 b_rate_cfg = ((u16 *)val)[0];
383 u8 rate_index = 0;
384 b_rate_cfg = b_rate_cfg & 0x15f;
385 b_rate_cfg |= 0x01;
386 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
387 rtl_write_byte(rtlpriv, REG_RRSR + 1,
388 (b_rate_cfg >> 8) & 0xff);
389 while (b_rate_cfg > 0x1) {
390 b_rate_cfg = (b_rate_cfg >> 1);
391 rate_index++;
392 }
393 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
394 rate_index);
395 break;
396 }
397 case HW_VAR_BSSID:
398 for (idx = 0; idx < ETH_ALEN; idx++) {
399 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
400 val[idx]);
401 }
402 break;
403 case HW_VAR_SIFS:
404 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
405 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
406
407 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
408 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
409
410 if (!mac->ht_enable)
411 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
412 0x0e0e);
413 else
414 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
415 *((u16 *)val));
416 break;
417 case HW_VAR_SLOT_TIME:{
418 u8 e_aci;
419
420 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
421 "HW_VAR_SLOT_TIME %x\n", val[0]);
422
423 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
424
425 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
426 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
427 &e_aci);
428 }
429 break;
430 }
431 case HW_VAR_ACK_PREAMBLE:{
432 u8 reg_tmp;
433 u8 short_preamble = (bool)*val;
434 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
435 if (short_preamble) {
436 reg_tmp |= 0x02;
437 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
438 2, reg_tmp);
439 } else {
440 reg_tmp |= 0xFD;
441 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
442 2, reg_tmp);
443 }
444 break; }
445 case HW_VAR_WPA_CONFIG:
446 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
447 break;
448 case HW_VAR_AMPDU_MIN_SPACE:{
449 u8 min_spacing_to_set;
450 u8 sec_min_space;
451
452 min_spacing_to_set = *val;
453 if (min_spacing_to_set <= 7) {
454 sec_min_space = 0;
455
456 if (min_spacing_to_set < sec_min_space)
457 min_spacing_to_set = sec_min_space;
458
459 mac->min_space_cfg = ((mac->min_space_cfg &
460 0xf8) |
461 min_spacing_to_set);
462
463 *val = min_spacing_to_set;
464
465 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
466 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
467 mac->min_space_cfg);
468
469 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
470 mac->min_space_cfg);
471 }
472 break; }
473 case HW_VAR_SHORTGI_DENSITY:{
474 u8 density_to_set;
475
476 density_to_set = *val;
477 mac->min_space_cfg |= (density_to_set << 3);
478
479 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
480 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
481 mac->min_space_cfg);
482
483 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
484 mac->min_space_cfg);
485 break;
486 }
487 case HW_VAR_AMPDU_FACTOR:{
488 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
489 u8 factor_toset;
490 u8 *p_regtoset = NULL;
491 u8 index = 0;
492
493 p_regtoset = regtoset_normal;
494
495 factor_toset = *val;
496 if (factor_toset <= 3) {
497 factor_toset = (1 << (factor_toset + 2));
498 if (factor_toset > 0xf)
499 factor_toset = 0xf;
500
501 for (index = 0; index < 4; index++) {
502 if ((p_regtoset[index] & 0xf0) >
503 (factor_toset << 4))
504 p_regtoset[index] =
505 (p_regtoset[index] & 0x0f) |
506 (factor_toset << 4);
507
508 if ((p_regtoset[index] & 0x0f) >
509 factor_toset)
510 p_regtoset[index] =
511 (p_regtoset[index] & 0xf0) |
512 (factor_toset);
513
514 rtl_write_byte(rtlpriv,
515 (REG_AGGLEN_LMT + index),
516 p_regtoset[index]);
517
518 }
519
520 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
521 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
522 factor_toset);
523 }
524 break; }
525 case HW_VAR_AC_PARAM:{
526 u8 e_aci = *val;
527 rtl88e_dm_init_edca_turbo(hw);
528
529 if (rtlpci->acm_method != EACMWAY2_SW)
530 rtlpriv->cfg->ops->set_hw_reg(hw,
531 HW_VAR_ACM_CTRL,
532 &e_aci);
533 break; }
534 case HW_VAR_ACM_CTRL:{
535 u8 e_aci = *val;
536 union aci_aifsn *p_aci_aifsn =
537 (union aci_aifsn *)(&(mac->ac[0].aifs));
538 u8 acm = p_aci_aifsn->f.acm;
539 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
540
541 acm_ctrl = acm_ctrl |
542 ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
543
544 if (acm) {
545 switch (e_aci) {
546 case AC0_BE:
547 acm_ctrl |= ACMHW_BEQEN;
548 break;
549 case AC2_VI:
550 acm_ctrl |= ACMHW_VIQEN;
551 break;
552 case AC3_VO:
553 acm_ctrl |= ACMHW_VOQEN;
554 break;
555 default:
556 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
557 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
558 acm);
559 break;
560 }
561 } else {
562 switch (e_aci) {
563 case AC0_BE:
564 acm_ctrl &= (~ACMHW_BEQEN);
565 break;
566 case AC2_VI:
567 acm_ctrl &= (~ACMHW_VIQEN);
568 break;
569 case AC3_VO:
570 acm_ctrl &= (~ACMHW_VOQEN);
571 break;
572 default:
573 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
574 "switch case not process\n");
575 break;
576 }
577 }
578
579 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
580 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
581 acm_ctrl);
582 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
583 break; }
584 case HW_VAR_RCR:
585 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
586 rtlpci->receive_config = ((u32 *)(val))[0];
587 break;
588 case HW_VAR_RETRY_LIMIT:{
589 u8 retry_limit = *val;
590
591 rtl_write_word(rtlpriv, REG_RL,
592 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
593 retry_limit << RETRY_LIMIT_LONG_SHIFT);
594 break; }
595 case HW_VAR_DUAL_TSF_RST:
596 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
597 break;
598 case HW_VAR_EFUSE_BYTES:
599 rtlefuse->efuse_usedbytes = *((u16 *)val);
600 break;
601 case HW_VAR_EFUSE_USAGE:
602 rtlefuse->efuse_usedpercentage = *val;
603 break;
604 case HW_VAR_IO_CMD:
605 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
606 break;
607 case HW_VAR_SET_RPWM:{
608 u8 rpwm_val;
609
610 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
611 udelay(1);
612
613 if (rpwm_val & BIT(7)) {
614 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
615 } else {
616 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
617 }
618 break; }
619 case HW_VAR_H2C_FW_PWRMODE:
620 rtl88e_set_fw_pwrmode_cmd(hw, *val);
621 break;
622 case HW_VAR_FW_PSMODE_STATUS:
623 ppsc->fw_current_inpsmode = *((bool *)val);
624 break;
625 case HW_VAR_RESUME_CLK_ON:
626 _rtl88ee_set_fw_ps_rf_on(hw);
627 break;
628 case HW_VAR_FW_LPS_ACTION:{
629 bool enter_fwlps = *((bool *)val);
630
631 if (enter_fwlps)
632 _rtl88ee_fwlps_enter(hw);
633 else
634 _rtl88ee_fwlps_leave(hw);
635
636 break; }
637 case HW_VAR_H2C_FW_JOINBSSRPT:{
638 u8 mstatus = *val;
639 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
640 u8 count = 0, dlbcn_count = 0;
641 bool b_recover = false;
642
643 if (mstatus == RT_MEDIA_CONNECT) {
644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
645 NULL);
646
647 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
648 rtl_write_byte(rtlpriv, REG_CR + 1,
649 (tmp_regcr | BIT(0)));
650
651 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
652 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
653
654 tmp_reg422 =
655 rtl_read_byte(rtlpriv,
656 REG_FWHW_TXQ_CTRL + 2);
657 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
658 tmp_reg422 & (~BIT(6)));
659 if (tmp_reg422 & BIT(6))
660 b_recover = true;
661
662 do {
663 bcnvalid_reg = rtl_read_byte(rtlpriv,
664 REG_TDECTRL+2);
665 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
666 (bcnvalid_reg | BIT(0)));
667 _rtl88ee_return_beacon_queue_skb(hw);
668
669 rtl88e_set_fw_rsvdpagepkt(hw, 0);
670 bcnvalid_reg = rtl_read_byte(rtlpriv,
671 REG_TDECTRL+2);
672 count = 0;
673 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
674 count++;
675 udelay(10);
676 bcnvalid_reg =
677 rtl_read_byte(rtlpriv, REG_TDECTRL+2);
678 }
679 dlbcn_count++;
680 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
681
682 if (bcnvalid_reg & BIT(0))
683 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
684
685 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
686 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
687
688 if (b_recover) {
689 rtl_write_byte(rtlpriv,
690 REG_FWHW_TXQ_CTRL + 2,
691 tmp_reg422);
692 }
693
694 rtl_write_byte(rtlpriv, REG_CR + 1,
695 (tmp_regcr & ~(BIT(0))));
696 }
697 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
698 break; }
699 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
700 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
701 break;
702 case HW_VAR_AID:{
703 u16 u2btmp;
704
705 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
706 u2btmp &= 0xC000;
707 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
708 mac->assoc_id));
709 break; }
710 case HW_VAR_CORRECT_TSF:{
711 u8 btype_ibss = *val;
712
713 if (btype_ibss)
714 _rtl88ee_stop_tx_beacon(hw);
715
716 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
717
718 rtl_write_dword(rtlpriv, REG_TSFTR,
719 (u32)(mac->tsf & 0xffffffff));
720 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
721 (u32)((mac->tsf >> 32) & 0xffffffff));
722
723 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
724
725 if (btype_ibss)
726 _rtl88ee_resume_tx_beacon(hw);
727 break; }
728 case HW_VAR_KEEP_ALIVE: {
729 u8 array[2];
730
731 array[0] = 0xff;
732 array[1] = *((u8 *)val);
733 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
734 2, array);
735 break; }
736 default:
737 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
738 "switch case not process %x\n", variable);
739 break;
740 }
741 }
742
743 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
744 {
745 struct rtl_priv *rtlpriv = rtl_priv(hw);
746 bool status = true;
747 long count = 0;
748 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
749 _LLT_OP(_LLT_WRITE_ACCESS);
750
751 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
752
753 do {
754 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
755 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
756 break;
757
758 if (count > POLLING_LLT_THRESHOLD) {
759 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
760 "Failed to polling write LLT done at address %d!\n",
761 address);
762 status = false;
763 break;
764 }
765 } while (++count);
766
767 return status;
768 }
769
770 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
771 {
772 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 unsigned short i;
774 u8 txpktbuf_bndy;
775 u8 maxpage;
776 bool status;
777
778 maxpage = 0xAF;
779 txpktbuf_bndy = 0xAB;
780
781 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
782 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
783
784 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
785 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
786 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
787
788 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
789 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
790
791 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
792 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
793 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
794
795 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
796 status = _rtl88ee_llt_write(hw, i, i + 1);
797 if (true != status)
798 return status;
799 }
800
801 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
802 if (true != status)
803 return status;
804
805 for (i = txpktbuf_bndy; i < maxpage; i++) {
806 status = _rtl88ee_llt_write(hw, i, (i + 1));
807 if (true != status)
808 return status;
809 }
810
811 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
812 if (true != status)
813 return status;
814
815 return true;
816 }
817
818 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
819 {
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
822 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
823 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
824
825 if (rtlpriv->rtlhal.up_first_time)
826 return;
827
828 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
829 rtl88ee_sw_led_on(hw, pLed0);
830 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
831 rtl88ee_sw_led_on(hw, pLed0);
832 else
833 rtl88ee_sw_led_off(hw, pLed0);
834 }
835
836 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
837 {
838 struct rtl_priv *rtlpriv = rtl_priv(hw);
839 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
840 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
841
842 u8 bytetmp;
843 u16 wordtmp;
844
845 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
846 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
847 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
848 /*Auto Power Down to CHIP-off State*/
849 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
850 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
851
852 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
853 /* HW Power on sequence */
854 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
855 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
856 RTL8188EE_NIC_ENABLE_FLOW)) {
857 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
858 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
859 return false;
860 }
861
862 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
863 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
864
865 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
866 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
867
868 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
869 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
870
871 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
872 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
873
874 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
875 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
876 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
877 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
878
879 /*Add for wake up online*/
880 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
881
882 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
883 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
884 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
885 rtl_write_byte(rtlpriv, 0x367, 0x80);
886
887 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
888 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
889 rtl_write_byte(rtlpriv, MSR, 0x00);
890
891 if (!rtlhal->mac_func_enable) {
892 if (_rtl88ee_llt_table_init(hw) == false) {
893 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
894 "LLT table init fail\n");
895 return false;
896 }
897 }
898 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
899 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
900
901 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
902 wordtmp &= 0xf;
903 wordtmp |= 0xE771;
904 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
905
906 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
907 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
908 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
909
910 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
911 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
912 DMA_BIT_MASK(32));
913 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
914 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
915 DMA_BIT_MASK(32));
916 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
917 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
918 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
919 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
920 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
921 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
922 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
923 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
924 rtl_write_dword(rtlpriv, REG_HQ_DESA,
925 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
926 DMA_BIT_MASK(32));
927 rtl_write_dword(rtlpriv, REG_RX_DESA,
928 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
929 DMA_BIT_MASK(32));
930
931 /* if we want to support 64 bit DMA, we should set it here,
932 * but now we do not support 64 bit DMA
933 */
934 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
935
936 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
937 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
938
939 if (rtlhal->earlymode_enable) {/*Early mode enable*/
940 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
941 bytetmp |= 0x1f;
942 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
943 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
944 }
945 _rtl88ee_gen_refresh_led_state(hw);
946 return true;
947 }
948
949 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
950 {
951 struct rtl_priv *rtlpriv = rtl_priv(hw);
952 u8 reg_bw_opmode;
953 u32 reg_ratr, reg_prsr;
954
955 reg_bw_opmode = BW_OPMODE_20MHZ;
956 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
957 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
958 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
959
960 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
961 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
962 }
963
964 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
965 {
966 struct rtl_priv *rtlpriv = rtl_priv(hw);
967 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
968 u8 tmp1byte = 0;
969 u32 tmp4byte = 0, count = 0;
970
971 rtl_write_word(rtlpriv, 0x354, 0x8104);
972 rtl_write_word(rtlpriv, 0x358, 0x24);
973
974 rtl_write_word(rtlpriv, 0x350, 0x70c);
975 rtl_write_byte(rtlpriv, 0x352, 0x2);
976 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
977 count = 0;
978 while (tmp1byte && count < 20) {
979 udelay(10);
980 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
981 count++;
982 }
983 if (0 == tmp1byte) {
984 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
985 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
986 rtl_write_word(rtlpriv, 0x350, 0xf70c);
987 rtl_write_byte(rtlpriv, 0x352, 0x1);
988 }
989
990 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
991 count = 0;
992 while (tmp1byte && count < 20) {
993 udelay(10);
994 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
995 count++;
996 }
997
998 rtl_write_word(rtlpriv, 0x350, 0x718);
999 rtl_write_byte(rtlpriv, 0x352, 0x2);
1000 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1001 count = 0;
1002 while (tmp1byte && count < 20) {
1003 udelay(10);
1004 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1005 count++;
1006 }
1007
1008 if (ppsc->support_backdoor || (0 == tmp1byte)) {
1009 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1010 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1011 rtl_write_word(rtlpriv, 0x350, 0xf718);
1012 rtl_write_byte(rtlpriv, 0x352, 0x1);
1013 }
1014
1015 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1016 count = 0;
1017 while (tmp1byte && count < 20) {
1018 udelay(10);
1019 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1020 count++;
1021 }
1022 }
1023
1024 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1025 {
1026 struct rtl_priv *rtlpriv = rtl_priv(hw);
1027 u8 sec_reg_value;
1028
1029 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1030 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1031 rtlpriv->sec.pairwise_enc_algorithm,
1032 rtlpriv->sec.group_enc_algorithm);
1033
1034 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1035 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1036 "not open hw encryption\n");
1037 return;
1038 }
1039
1040 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1041
1042 if (rtlpriv->sec.use_defaultkey) {
1043 sec_reg_value |= SCR_TXUSEDK;
1044 sec_reg_value |= SCR_RXUSEDK;
1045 }
1046
1047 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1048
1049 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1050
1051 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1052 "The SECR-value %x\n", sec_reg_value);
1053
1054 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1055 }
1056
1057 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1058 {
1059 struct rtl_priv *rtlpriv = rtl_priv(hw);
1060 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1061 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1062 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1063 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1064 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1065 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1066 bool rtstatus = true;
1067 int err = 0;
1068 u8 tmp_u1b, u1byte;
1069 unsigned long flags;
1070
1071 rtlpriv->rtlhal.being_init_adapter = true;
1072 /* As this function can take a very long time (up to 350 ms)
1073 * and can be called with irqs disabled, reenable the irqs
1074 * to let the other devices continue being serviced.
1075 *
1076 * It is safe doing so since our own interrupts will only be enabled
1077 * in a subsequent step.
1078 */
1079 local_save_flags(flags);
1080 local_irq_enable();
1081 rtlhal->fw_ready = false;
1082
1083 rtlpriv->intf_ops->disable_aspm(hw);
1084
1085 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1086 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1087 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1088 rtlhal->mac_func_enable = true;
1089 } else {
1090 rtlhal->mac_func_enable = false;
1091 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1092 }
1093
1094 rtstatus = _rtl88ee_init_mac(hw);
1095 if (rtstatus != true) {
1096 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1097 err = 1;
1098 goto exit;
1099 }
1100
1101 err = rtl88e_download_fw(hw, false);
1102 if (err) {
1103 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1104 "Failed to download FW. Init HW without FW now..\n");
1105 err = 1;
1106 goto exit;
1107 }
1108 rtlhal->fw_ready = true;
1109 /*fw related variable initialize */
1110 rtlhal->last_hmeboxnum = 0;
1111 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1112 rtlhal->fw_clk_change_in_progress = false;
1113 rtlhal->allow_sw_to_change_hwclc = false;
1114 ppsc->fw_current_inpsmode = false;
1115
1116 rtl88e_phy_mac_config(hw);
1117 /* because last function modify RCR, so we update
1118 * rcr var here, or TP will unstable for receive_config
1119 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1120 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1121 */
1122 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1123 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1124
1125 rtl88e_phy_bb_config(hw);
1126 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1127 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1128
1129 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1130 rtl88e_phy_rf_config(hw);
1131
1132 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1133 RF_CHNLBW, RFREG_OFFSET_MASK);
1134 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1135
1136 _rtl88ee_hw_configure(hw);
1137 rtl_cam_reset_all_entry(hw);
1138 rtl88ee_enable_hw_security_config(hw);
1139
1140 rtlhal->mac_func_enable = true;
1141 ppsc->rfpwr_state = ERFON;
1142
1143 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1144 _rtl88ee_enable_aspm_back_door(hw);
1145 rtlpriv->intf_ops->enable_aspm(hw);
1146
1147 if (ppsc->rfpwr_state == ERFON) {
1148 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1149 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1150 (rtlhal->oem_id == RT_CID_819X_HP))) {
1151 rtl88e_phy_set_rfpath_switch(hw, true);
1152 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1153 } else {
1154 rtl88e_phy_set_rfpath_switch(hw, false);
1155 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1156 }
1157 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1158 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1159 ("MAIN_ANT") : ("AUX_ANT"));
1160
1161 if (rtlphy->iqk_initialized) {
1162 rtl88e_phy_iq_calibrate(hw, true);
1163 } else {
1164 rtl88e_phy_iq_calibrate(hw, false);
1165 rtlphy->iqk_initialized = true;
1166 }
1167
1168 rtl88e_dm_check_txpower_tracking(hw);
1169 rtl88e_phy_lc_calibrate(hw);
1170 }
1171
1172 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1173 if (!(tmp_u1b & BIT(0))) {
1174 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1176 }
1177
1178 if (!(tmp_u1b & BIT(4))) {
1179 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1180 tmp_u1b &= 0x0F;
1181 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1182 udelay(10);
1183 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1184 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1185 }
1186 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));
1187 rtl88e_dm_init(hw);
1188 exit:
1189 local_irq_restore(flags);
1190 rtlpriv->rtlhal.being_init_adapter = false;
1191 return err;
1192 }
1193
1194 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1195 {
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1198 enum version_8188e version = VERSION_UNKNOWN;
1199 u32 value32;
1200
1201 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1202 if (value32 & TRP_VAUX_EN) {
1203 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1204 } else {
1205 version = NORMAL_CHIP;
1206 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1207 version = version | ((value32 & VENDOR_ID) ?
1208 CHIP_VENDOR_UMC : 0);
1209 }
1210
1211 rtlphy->rf_type = RF_1T1R;
1212 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1213 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1214 "RF_2T2R" : "RF_1T1R");
1215
1216 return version;
1217 }
1218
1219 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1220 enum nl80211_iftype type)
1221 {
1222 struct rtl_priv *rtlpriv = rtl_priv(hw);
1223 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1224 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1225 u8 mode = MSR_NOLINK;
1226
1227 switch (type) {
1228 case NL80211_IFTYPE_UNSPECIFIED:
1229 mode = MSR_NOLINK;
1230 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1231 "Set Network type to NO LINK!\n");
1232 break;
1233 case NL80211_IFTYPE_ADHOC:
1234 case NL80211_IFTYPE_MESH_POINT:
1235 mode = MSR_ADHOC;
1236 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1237 "Set Network type to Ad Hoc!\n");
1238 break;
1239 case NL80211_IFTYPE_STATION:
1240 mode = MSR_INFRA;
1241 ledaction = LED_CTL_LINK;
1242 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1243 "Set Network type to STA!\n");
1244 break;
1245 case NL80211_IFTYPE_AP:
1246 mode = MSR_AP;
1247 ledaction = LED_CTL_LINK;
1248 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1249 "Set Network type to AP!\n");
1250 break;
1251 default:
1252 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1253 "Network type %d not support!\n", type);
1254 return 1;
1255 break;
1256 }
1257
1258 /* MSR_INFRA == Link in infrastructure network;
1259 * MSR_ADHOC == Link in ad hoc network;
1260 * Therefore, check link state is necessary.
1261 *
1262 * MSR_AP == AP mode; link state is not cared here.
1263 */
1264 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1265 mode = MSR_NOLINK;
1266 ledaction = LED_CTL_NO_LINK;
1267 }
1268
1269 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1270 _rtl88ee_stop_tx_beacon(hw);
1271 _rtl88ee_enable_bcn_sub_func(hw);
1272 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1273 _rtl88ee_resume_tx_beacon(hw);
1274 _rtl88ee_disable_bcn_sub_func(hw);
1275 } else {
1276 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1277 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1278 mode);
1279 }
1280
1281 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1282 rtlpriv->cfg->ops->led_control(hw, ledaction);
1283 if (mode == MSR_AP)
1284 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1285 else
1286 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1287 return 0;
1288 }
1289
1290 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1291 {
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1294 u32 reg_rcr = rtlpci->receive_config;
1295
1296 if (rtlpriv->psc.rfpwr_state != ERFON)
1297 return;
1298
1299 if (check_bssid == true) {
1300 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1301 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1302 (u8 *)(®_rcr));
1303 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1304 } else if (check_bssid == false) {
1305 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1306 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1307 rtlpriv->cfg->ops->set_hw_reg(hw,
1308 HW_VAR_RCR, (u8 *)(®_rcr));
1309 }
1310
1311 }
1312
1313 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1314 enum nl80211_iftype type)
1315 {
1316 struct rtl_priv *rtlpriv = rtl_priv(hw);
1317
1318 if (_rtl88ee_set_media_status(hw, type))
1319 return -EOPNOTSUPP;
1320
1321 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1322 if (type != NL80211_IFTYPE_AP &&
1323 type != NL80211_IFTYPE_MESH_POINT)
1324 rtl88ee_set_check_bssid(hw, true);
1325 } else {
1326 rtl88ee_set_check_bssid(hw, false);
1327 }
1328
1329 return 0;
1330 }
1331
1332 /* don't set REG_EDCA_BE_PARAM here
1333 * because mac80211 will send pkt when scan
1334 */
1335 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1336 {
1337 struct rtl_priv *rtlpriv = rtl_priv(hw);
1338 rtl88e_dm_init_edca_turbo(hw);
1339 switch (aci) {
1340 case AC1_BK:
1341 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1342 break;
1343 case AC0_BE:
1344 break;
1345 case AC2_VI:
1346 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1347 break;
1348 case AC3_VO:
1349 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1350 break;
1351 default:
1352 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1353 break;
1354 }
1355 }
1356
1357 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1358 {
1359 struct rtl_priv *rtlpriv = rtl_priv(hw);
1360 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1361
1362 rtl_write_dword(rtlpriv, REG_HIMR,
1363 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1364 rtl_write_dword(rtlpriv, REG_HIMRE,
1365 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1366 rtlpci->irq_enabled = true;
1367 /* there are some C2H CMDs have been sent
1368 * before system interrupt is enabled, e.g., C2H, CPWM.
1369 * So we need to clear all C2H events that FW has notified,
1370 * otherwise FW won't schedule any commands anymore.
1371 */
1372 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1373 /*enable system interrupt*/
1374 rtl_write_dword(rtlpriv, REG_HSIMR,
1375 rtlpci->sys_irq_mask & 0xFFFFFFFF);
1376 }
1377
1378 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1379 {
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1382
1383 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1384 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1385 rtlpci->irq_enabled = false;
1386 /*synchronize_irq(rtlpci->pdev->irq);*/
1387 }
1388
1389 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1390 {
1391 struct rtl_priv *rtlpriv = rtl_priv(hw);
1392 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1393 u8 u1b_tmp;
1394 u32 count = 0;
1395 rtlhal->mac_func_enable = false;
1396 rtlpriv->intf_ops->enable_aspm(hw);
1397
1398 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1399 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1400 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1401
1402 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1403 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1404 udelay(10);
1405 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1406 count++;
1407 }
1408 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1409
1410 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1411 PWR_INTF_PCI_MSK,
1412 RTL8188EE_NIC_LPS_ENTER_FLOW);
1413
1414 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1415
1416 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1417 rtl88e_firmware_selfreset(hw);
1418
1419 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1420 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1421 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1422
1423 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1424 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1425
1426 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1427 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1428
1429 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1430 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1431 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1432 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1433
1434 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1435
1436 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1437 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1438 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1439
1440 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1441 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1442 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1443 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1444
1445 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1446 }
1447
1448 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1449 {
1450 struct rtl_priv *rtlpriv = rtl_priv(hw);
1451 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1452 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1453 enum nl80211_iftype opmode;
1454
1455 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1456
1457 mac->link_state = MAC80211_NOLINK;
1458 opmode = NL80211_IFTYPE_UNSPECIFIED;
1459
1460 _rtl88ee_set_media_status(hw, opmode);
1461
1462 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1463 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1464 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1465
1466 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1467 _rtl88ee_poweroff_adapter(hw);
1468
1469 /* after power off we should do iqk again */
1470 rtlpriv->phy.iqk_initialized = false;
1471 }
1472
1473 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1474 u32 *p_inta, u32 *p_intb)
1475 {
1476 struct rtl_priv *rtlpriv = rtl_priv(hw);
1477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1478
1479 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1480 rtl_write_dword(rtlpriv, ISR, *p_inta);
1481
1482 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1483 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1484
1485 }
1486
1487 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1488 {
1489 struct rtl_priv *rtlpriv = rtl_priv(hw);
1490 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1492 u16 bcn_interval, atim_window;
1493
1494 bcn_interval = mac->beacon_interval;
1495 atim_window = 2; /*FIX MERGE */
1496 rtl88ee_disable_interrupt(hw);
1497 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1498 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1499 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1500 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1501 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1502 rtl_write_byte(rtlpriv, 0x606, 0x30);
1503 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1504 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1505 /*rtl88ee_enable_interrupt(hw);*/
1506 }
1507
1508 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1509 {
1510 struct rtl_priv *rtlpriv = rtl_priv(hw);
1511 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1512 u16 bcn_interval = mac->beacon_interval;
1513
1514 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1515 "beacon_interval:%d\n", bcn_interval);
1516 /*rtl88ee_disable_interrupt(hw);*/
1517 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1518 /*rtl88ee_enable_interrupt(hw);*/
1519 }
1520
1521 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1522 u32 add_msr, u32 rm_msr)
1523 {
1524 struct rtl_priv *rtlpriv = rtl_priv(hw);
1525 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1526
1527 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1528 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1529
1530 if (add_msr)
1531 rtlpci->irq_mask[0] |= add_msr;
1532 if (rm_msr)
1533 rtlpci->irq_mask[0] &= (~rm_msr);
1534 rtl88ee_disable_interrupt(hw);
1535 rtl88ee_enable_interrupt(hw);
1536 }
1537
1538 static u8 _rtl88e_get_chnl_group(u8 chnl)
1539 {
1540 u8 group = 0;
1541
1542 if (chnl < 3)
1543 group = 0;
1544 else if (chnl < 6)
1545 group = 1;
1546 else if (chnl < 9)
1547 group = 2;
1548 else if (chnl < 12)
1549 group = 3;
1550 else if (chnl < 14)
1551 group = 4;
1552 else if (chnl == 14)
1553 group = 5;
1554
1555 return group;
1556 }
1557
1558 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1559 {
1560 int group, txcnt;
1561
1562 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1563 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1564 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1565 }
1566 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1567 if (txcnt == 0) {
1568 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1569 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1570 } else {
1571 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1572 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1573 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1574 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1575 }
1576 }
1577 }
1578
1579 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1580 struct txpower_info_2g *pwrinfo24g,
1581 struct txpower_info_5g *pwrinfo5g,
1582 bool autoload_fail, u8 *hwinfo)
1583 {
1584 struct rtl_priv *rtlpriv = rtl_priv(hw);
1585 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1586
1587 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1588 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1589 (eeaddr+1), hwinfo[eeaddr+1]);
1590 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/
1591 autoload_fail = true;
1592
1593 if (autoload_fail) {
1594 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1595 "auto load fail : Use Default value!\n");
1596 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1597 /* 2.4G default value */
1598 set_24g_base(pwrinfo24g, rfpath);
1599 }
1600 return;
1601 }
1602
1603 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1604 /*2.4G default value*/
1605 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1606 pwrinfo24g->index_cck_base[rfpath][group] =
1607 hwinfo[eeaddr++];
1608 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1609 pwrinfo24g->index_cck_base[rfpath][group] =
1610 0x2D;
1611 }
1612 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1613 pwrinfo24g->index_bw40_base[rfpath][group] =
1614 hwinfo[eeaddr++];
1615 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1616 pwrinfo24g->index_bw40_base[rfpath][group] =
1617 0x2D;
1618 }
1619 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1620 if (hwinfo[eeaddr] == 0xFF) {
1621 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1622 } else {
1623 pwrinfo24g->bw20_diff[rfpath][0] =
1624 (hwinfo[eeaddr]&0xf0)>>4;
1625 /*bit sign number to 8 bit sign number*/
1626 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1627 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1628 }
1629
1630 if (hwinfo[eeaddr] == 0xFF) {
1631 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1632 } else {
1633 pwrinfo24g->ofdm_diff[rfpath][0] =
1634 (hwinfo[eeaddr]&0x0f);
1635 /*bit sign number to 8 bit sign number*/
1636 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1637 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1638 }
1639 pwrinfo24g->cck_diff[rfpath][0] = 0;
1640 eeaddr++;
1641 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1642 if (hwinfo[eeaddr] == 0xFF) {
1643 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1644 } else {
1645 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1646 (hwinfo[eeaddr]&0xf0)>>4;
1647 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1648 BIT(3))
1649 pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1650 0xF0;
1651 }
1652
1653 if (hwinfo[eeaddr] == 0xFF) {
1654 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1655 0xFE;
1656 } else {
1657 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1658 (hwinfo[eeaddr]&0x0f);
1659 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1660 BIT(3))
1661 pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1662 0xF0;
1663 }
1664 eeaddr++;
1665
1666 if (hwinfo[eeaddr] == 0xFF) {
1667 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1668 } else {
1669 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1670 (hwinfo[eeaddr]&0xf0)>>4;
1671 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1672 BIT(3))
1673 pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1674 0xF0;
1675 }
1676
1677 if (hwinfo[eeaddr] == 0xFF) {
1678 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1679 } else {
1680 pwrinfo24g->cck_diff[rfpath][txcnt] =
1681 (hwinfo[eeaddr]&0x0f);
1682 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1683 BIT(3))
1684 pwrinfo24g->cck_diff[rfpath][txcnt] |=
1685 0xF0;
1686 }
1687 eeaddr++;
1688 }
1689
1690 /*5G default value*/
1691 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1692 pwrinfo5g->index_bw40_base[rfpath][group] =
1693 hwinfo[eeaddr++];
1694 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1695 pwrinfo5g->index_bw40_base[rfpath][group] =
1696 0xFE;
1697 }
1698
1699 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1700
1701 if (hwinfo[eeaddr] == 0xFF) {
1702 pwrinfo5g->bw20_diff[rfpath][0] = 0;
1703 } else {
1704 pwrinfo5g->bw20_diff[rfpath][0] =
1705 (hwinfo[eeaddr]&0xf0)>>4;
1706 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1707 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1708 }
1709
1710 if (hwinfo[eeaddr] == 0xFF) {
1711 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1712 } else {
1713 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1714 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1715 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1716 }
1717 eeaddr++;
1718 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1719 if (hwinfo[eeaddr] == 0xFF) {
1720 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE;
1721 } else {
1722 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1723 (hwinfo[eeaddr]&0xf0)>>4;
1724 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1725 BIT(3))
1726 pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1727 0xF0;
1728 }
1729
1730 if (hwinfo[eeaddr] == 0xFF) {
1731 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE;
1732 } else {
1733 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1734 (hwinfo[eeaddr]&0x0f);
1735 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1736 BIT(3))
1737 pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1738 0xF0;
1739 }
1740 eeaddr++;
1741 }
1742
1743 if (hwinfo[eeaddr] == 0xFF) {
1744 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1745 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1746 } else {
1747 pwrinfo5g->ofdm_diff[rfpath][1] =
1748 (hwinfo[eeaddr]&0xf0)>>4;
1749 pwrinfo5g->ofdm_diff[rfpath][2] =
1750 (hwinfo[eeaddr]&0x0f);
1751 }
1752 eeaddr++;
1753
1754 if (hwinfo[eeaddr] == 0xFF)
1755 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1756 else
1757 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1758 eeaddr++;
1759
1760 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1761 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1762 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE;
1763 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1764 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1765 }
1766 }
1767 }
1768
1769 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1770 bool autoload_fail,
1771 u8 *hwinfo)
1772 {
1773 struct rtl_priv *rtlpriv = rtl_priv(hw);
1774 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1775 struct txpower_info_2g pwrinfo24g;
1776 struct txpower_info_5g pwrinfo5g;
1777 u8 rf_path, index;
1778 u8 i;
1779
1780 read_power_value_fromprom(hw, &pwrinfo24g,
1781 &pwrinfo5g, autoload_fail, hwinfo);
1782
1783 for (rf_path = 0; rf_path < 2; rf_path++) {
1784 for (i = 0; i < 14; i++) {
1785 index = _rtl88e_get_chnl_group(i+1);
1786
1787 rtlefuse->txpwrlevel_cck[rf_path][i] =
1788 pwrinfo24g.index_cck_base[rf_path][index];
1789 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1790 pwrinfo24g.index_bw40_base[rf_path][index];
1791 rtlefuse->txpwr_ht20diff[rf_path][i] =
1792 pwrinfo24g.bw20_diff[rf_path][0];
1793 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1794 pwrinfo24g.ofdm_diff[rf_path][0];
1795 }
1796
1797 for (i = 0; i < 14; i++) {
1798 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1799 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1800 rf_path, i,
1801 rtlefuse->txpwrlevel_cck[rf_path][i],
1802 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1803 }
1804 }
1805
1806 if (!autoload_fail)
1807 rtlefuse->eeprom_thermalmeter =
1808 hwinfo[EEPROM_THERMAL_METER_88E];
1809 else
1810 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1811
1812 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1813 rtlefuse->apk_thermalmeterignore = true;
1814 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1815 }
1816
1817 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1818 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1819 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1820
1821 if (!autoload_fail) {
1822 rtlefuse->eeprom_regulatory =
1823 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1824 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1825 rtlefuse->eeprom_regulatory = 0;
1826 } else {
1827 rtlefuse->eeprom_regulatory = 0;
1828 }
1829 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1830 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1831 }
1832
1833 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1834 {
1835 struct rtl_priv *rtlpriv = rtl_priv(hw);
1836 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1837 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1838 u16 i, usvalue;
1839 u8 hwinfo[HWSET_MAX_SIZE];
1840 u16 eeprom_id;
1841
1842 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1843 rtl_efuse_shadow_map_update(hw);
1844
1845 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1846 HWSET_MAX_SIZE);
1847 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1848 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1849 "RTL819X Not boot from eeprom, check it !!");
1850 return;
1851 } else {
1852 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1853 "boot from neither eeprom nor efuse, check it !!");
1854 return;
1855 }
1856
1857 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
1858 hwinfo, HWSET_MAX_SIZE);
1859
1860 eeprom_id = *((u16 *)&hwinfo[0]);
1861 if (eeprom_id != RTL8188E_EEPROM_ID) {
1862 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1863 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1864 rtlefuse->autoload_failflag = true;
1865 } else {
1866 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1867 rtlefuse->autoload_failflag = false;
1868 }
1869
1870 if (rtlefuse->autoload_failflag == true)
1871 return;
1872 /*VID DID SVID SDID*/
1873 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1874 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1875 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1876 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1877 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1878 "EEPROMId = 0x%4x\n", eeprom_id);
1879 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1880 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1881 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1882 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1883 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1884 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1885 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1886 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1887 /*customer ID*/
1888 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1889 if (rtlefuse->eeprom_oemid == 0xFF)
1890 rtlefuse->eeprom_oemid = 0;
1891
1892 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1893 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1894 /*EEPROM version*/
1895 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1896 /*mac address*/
1897 for (i = 0; i < 6; i += 2) {
1898 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1899 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1900 }
1901
1902 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1903 "dev_addr: %pM\n", rtlefuse->dev_addr);
1904 /*channel plan */
1905 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1906 /* set channel plan from efuse */
1907 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1908 /*tx power*/
1909 _rtl88ee_read_txpower_info_from_hwpg(hw,
1910 rtlefuse->autoload_failflag,
1911 hwinfo);
1912 rtlefuse->txpwr_fromeprom = true;
1913
1914 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1915 rtlefuse->autoload_failflag,
1916 hwinfo);
1917
1918 /*board type*/
1919 rtlefuse->board_type =
1920 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1921 rtlhal->board_type = rtlefuse->board_type;
1922 /*Wake on wlan*/
1923 rtlefuse->wowlan_enable =
1924 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1925 /*parse xtal*/
1926 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1927 if (hwinfo[EEPROM_XTAL_88E])
1928 rtlefuse->crystalcap = 0x20;
1929 /*antenna diversity*/
1930 rtlefuse->antenna_div_cfg =
1931 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1932 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1933 rtlefuse->antenna_div_cfg = 0;
1934 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1935 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1936 rtlefuse->antenna_div_cfg = 0;
1937
1938 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1939 if (rtlefuse->antenna_div_type == 0xFF)
1940 rtlefuse->antenna_div_type = 0x01;
1941 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1942 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1943 rtlefuse->antenna_div_cfg = 1;
1944
1945 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1946 switch (rtlefuse->eeprom_oemid) {
1947 case EEPROM_CID_DEFAULT:
1948 if (rtlefuse->eeprom_did == 0x8179) {
1949 if (rtlefuse->eeprom_svid == 0x1025) {
1950 rtlhal->oem_id = RT_CID_819X_ACER;
1951 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1952 rtlefuse->eeprom_smid == 0x0179) ||
1953 (rtlefuse->eeprom_svid == 0x17AA &&
1954 rtlefuse->eeprom_smid == 0x0179)) {
1955 rtlhal->oem_id = RT_CID_819X_LENOVO;
1956 } else if (rtlefuse->eeprom_svid == 0x103c &&
1957 rtlefuse->eeprom_smid == 0x197d) {
1958 rtlhal->oem_id = RT_CID_819X_HP;
1959 } else {
1960 rtlhal->oem_id = RT_CID_DEFAULT;
1961 }
1962 } else {
1963 rtlhal->oem_id = RT_CID_DEFAULT;
1964 }
1965 break;
1966 case EEPROM_CID_TOSHIBA:
1967 rtlhal->oem_id = RT_CID_TOSHIBA;
1968 break;
1969 case EEPROM_CID_QMI:
1970 rtlhal->oem_id = RT_CID_819X_QMI;
1971 break;
1972 case EEPROM_CID_WHQL:
1973 default:
1974 rtlhal->oem_id = RT_CID_DEFAULT;
1975 break;
1976
1977 }
1978 }
1979 }
1980
1981 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1982 {
1983 struct rtl_priv *rtlpriv = rtl_priv(hw);
1984 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1985 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1986
1987 pcipriv->ledctl.led_opendrain = true;
1988
1989 switch (rtlhal->oem_id) {
1990 case RT_CID_819X_HP:
1991 pcipriv->ledctl.led_opendrain = true;
1992 break;
1993 case RT_CID_819X_LENOVO:
1994 case RT_CID_DEFAULT:
1995 case RT_CID_TOSHIBA:
1996 case RT_CID_CCX:
1997 case RT_CID_819X_ACER:
1998 case RT_CID_WHQL:
1999 default:
2000 break;
2001 }
2002 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2003 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2004 }
2005
2006 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
2007 {
2008 struct rtl_priv *rtlpriv = rtl_priv(hw);
2009 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2010 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2011 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2012 u8 tmp_u1b;
2013
2014 rtlhal->version = _rtl88ee_read_chip_version(hw);
2015 if (get_rf_type(rtlphy) == RF_1T1R)
2016 rtlpriv->dm.rfpath_rxenable[0] = true;
2017 else
2018 rtlpriv->dm.rfpath_rxenable[0] =
2019 rtlpriv->dm.rfpath_rxenable[1] = true;
2020 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2021 rtlhal->version);
2022 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2023 if (tmp_u1b & BIT(4)) {
2024 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2025 rtlefuse->epromtype = EEPROM_93C46;
2026 } else {
2027 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2028 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2029 }
2030 if (tmp_u1b & BIT(5)) {
2031 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2032 rtlefuse->autoload_failflag = false;
2033 _rtl88ee_read_adapter_info(hw);
2034 } else {
2035 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2036 }
2037 _rtl88ee_hal_customized_behavior(hw);
2038 }
2039
2040 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
2041 struct ieee80211_sta *sta)
2042 {
2043 struct rtl_priv *rtlpriv = rtl_priv(hw);
2044 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2045 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2046 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2047 u32 ratr_value;
2048 u8 ratr_index = 0;
2049 u8 b_nmode = mac->ht_enable;
2050 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2051 u16 shortgi_rate;
2052 u32 tmp_ratr_value;
2053 u8 curtxbw_40mhz = mac->bw_40;
2054 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2055 1 : 0;
2056 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2057 1 : 0;
2058 enum wireless_mode wirelessmode = mac->mode;
2059 u32 ratr_mask;
2060
2061 if (rtlhal->current_bandtype == BAND_ON_5G)
2062 ratr_value = sta->supp_rates[1] << 4;
2063 else
2064 ratr_value = sta->supp_rates[0];
2065 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2066 ratr_value = 0xfff;
2067 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2068 sta->ht_cap.mcs.rx_mask[0] << 12);
2069 switch (wirelessmode) {
2070 case WIRELESS_MODE_B:
2071 if (ratr_value & 0x0000000c)
2072 ratr_value &= 0x0000000d;
2073 else
2074 ratr_value &= 0x0000000f;
2075 break;
2076 case WIRELESS_MODE_G:
2077 ratr_value &= 0x00000FF5;
2078 break;
2079 case WIRELESS_MODE_N_24G:
2080 case WIRELESS_MODE_N_5G:
2081 b_nmode = 1;
2082 if (get_rf_type(rtlphy) == RF_1T2R ||
2083 get_rf_type(rtlphy) == RF_1T1R)
2084 ratr_mask = 0x000ff005;
2085 else
2086 ratr_mask = 0x0f0ff005;
2087
2088 ratr_value &= ratr_mask;
2089 break;
2090 default:
2091 if (rtlphy->rf_type == RF_1T2R)
2092 ratr_value &= 0x000ff0ff;
2093 else
2094 ratr_value &= 0x0f0ff0ff;
2095
2096 break;
2097 }
2098
2099 if ((rtlpriv->btcoexist.bt_coexistence) &&
2100 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2101 (rtlpriv->btcoexist.bt_cur_state) &&
2102 (rtlpriv->btcoexist.bt_ant_isolation) &&
2103 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2104 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2105 ratr_value &= 0x0fffcfc0;
2106 else
2107 ratr_value &= 0x0FFFFFFF;
2108
2109 if (b_nmode &&
2110 ((curtxbw_40mhz && curshortgi_40mhz) ||
2111 (!curtxbw_40mhz && curshortgi_20mhz))) {
2112 ratr_value |= 0x10000000;
2113 tmp_ratr_value = (ratr_value >> 12);
2114
2115 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2116 if ((1 << shortgi_rate) & tmp_ratr_value)
2117 break;
2118 }
2119
2120 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2121 (shortgi_rate << 4) | (shortgi_rate);
2122 }
2123
2124 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2125
2126 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2127 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2128 }
2129
2130 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2131 struct ieee80211_sta *sta, u8 rssi_level)
2132 {
2133 struct rtl_priv *rtlpriv = rtl_priv(hw);
2134 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2135 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2136 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2137 struct rtl_sta_info *sta_entry = NULL;
2138 u32 ratr_bitmap;
2139 u8 ratr_index;
2140 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2141 ? 1 : 0;
2142 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2143 1 : 0;
2144 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2145 1 : 0;
2146 enum wireless_mode wirelessmode = 0;
2147 bool b_shortgi = false;
2148 u8 rate_mask[5];
2149 u8 macid = 0;
2150 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2151
2152 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2153 wirelessmode = sta_entry->wireless_mode;
2154 if (mac->opmode == NL80211_IFTYPE_STATION ||
2155 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2156 curtxbw_40mhz = mac->bw_40;
2157 else if (mac->opmode == NL80211_IFTYPE_AP ||
2158 mac->opmode == NL80211_IFTYPE_ADHOC)
2159 macid = sta->aid + 1;
2160
2161 if (rtlhal->current_bandtype == BAND_ON_5G)
2162 ratr_bitmap = sta->supp_rates[1] << 4;
2163 else
2164 ratr_bitmap = sta->supp_rates[0];
2165 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2166 ratr_bitmap = 0xfff;
2167 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2168 sta->ht_cap.mcs.rx_mask[0] << 12);
2169 switch (wirelessmode) {
2170 case WIRELESS_MODE_B:
2171 ratr_index = RATR_INX_WIRELESS_B;
2172 if (ratr_bitmap & 0x0000000c)
2173 ratr_bitmap &= 0x0000000d;
2174 else
2175 ratr_bitmap &= 0x0000000f;
2176 break;
2177 case WIRELESS_MODE_G:
2178 ratr_index = RATR_INX_WIRELESS_GB;
2179
2180 if (rssi_level == 1)
2181 ratr_bitmap &= 0x00000f00;
2182 else if (rssi_level == 2)
2183 ratr_bitmap &= 0x00000ff0;
2184 else
2185 ratr_bitmap &= 0x00000ff5;
2186 break;
2187 case WIRELESS_MODE_N_24G:
2188 case WIRELESS_MODE_N_5G:
2189 ratr_index = RATR_INX_WIRELESS_NGB;
2190 if (rtlphy->rf_type == RF_1T2R ||
2191 rtlphy->rf_type == RF_1T1R) {
2192 if (curtxbw_40mhz) {
2193 if (rssi_level == 1)
2194 ratr_bitmap &= 0x000f0000;
2195 else if (rssi_level == 2)
2196 ratr_bitmap &= 0x000ff000;
2197 else
2198 ratr_bitmap &= 0x000ff015;
2199 } else {
2200 if (rssi_level == 1)
2201 ratr_bitmap &= 0x000f0000;
2202 else if (rssi_level == 2)
2203 ratr_bitmap &= 0x000ff000;
2204 else
2205 ratr_bitmap &= 0x000ff005;
2206 }
2207 } else {
2208 if (curtxbw_40mhz) {
2209 if (rssi_level == 1)
2210 ratr_bitmap &= 0x0f8f0000;
2211 else if (rssi_level == 2)
2212 ratr_bitmap &= 0x0f8ff000;
2213 else
2214 ratr_bitmap &= 0x0f8ff015;
2215 } else {
2216 if (rssi_level == 1)
2217 ratr_bitmap &= 0x0f8f0000;
2218 else if (rssi_level == 2)
2219 ratr_bitmap &= 0x0f8ff000;
2220 else
2221 ratr_bitmap &= 0x0f8ff005;
2222 }
2223 }
2224 /*}*/
2225
2226 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2227 (!curtxbw_40mhz && curshortgi_20mhz)) {
2228
2229 if (macid == 0)
2230 b_shortgi = true;
2231 else if (macid == 1)
2232 b_shortgi = false;
2233 }
2234 break;
2235 default:
2236 ratr_index = RATR_INX_WIRELESS_NGB;
2237
2238 if (rtlphy->rf_type == RF_1T2R)
2239 ratr_bitmap &= 0x000ff0ff;
2240 else
2241 ratr_bitmap &= 0x0f0ff0ff;
2242 break;
2243 }
2244 sta_entry->ratr_index = ratr_index;
2245
2246 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2247 "ratr_bitmap :%x\n", ratr_bitmap);
2248 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2249 (ratr_index << 28);
2250 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2251 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2252 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2253 ratr_index, ratr_bitmap,
2254 rate_mask[0], rate_mask[1],
2255 rate_mask[2], rate_mask[3],
2256 rate_mask[4]);
2257 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2258 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2259 }
2260
2261 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2262 struct ieee80211_sta *sta, u8 rssi_level)
2263 {
2264 struct rtl_priv *rtlpriv = rtl_priv(hw);
2265
2266 if (rtlpriv->dm.useramask)
2267 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level);
2268 else
2269 rtl88ee_update_hal_rate_table(hw, sta);
2270 }
2271
2272 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2273 {
2274 struct rtl_priv *rtlpriv = rtl_priv(hw);
2275 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2276 u16 sifs_timer;
2277
2278 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2279 if (!mac->ht_enable)
2280 sifs_timer = 0x0a0a;
2281 else
2282 sifs_timer = 0x0e0e;
2283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2284 }
2285
2286 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2287 {
2288 struct rtl_priv *rtlpriv = rtl_priv(hw);
2289 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2290 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2291 u32 u4tmp;
2292 bool b_actuallyset = false;
2293
2294 if (rtlpriv->rtlhal.being_init_adapter)
2295 return false;
2296
2297 if (ppsc->swrf_processing)
2298 return false;
2299
2300 spin_lock(&rtlpriv->locks.rf_ps_lock);
2301 if (ppsc->rfchange_inprogress) {
2302 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2303 return false;
2304 } else {
2305 ppsc->rfchange_inprogress = true;
2306 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2307 }
2308
2309 cur_rfstate = ppsc->rfpwr_state;
2310
2311 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2312 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2313
2314 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2315 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2316 "GPIOChangeRF - HW Radio ON, RF ON\n");
2317
2318 e_rfpowerstate_toset = ERFON;
2319 ppsc->hwradiooff = false;
2320 b_actuallyset = true;
2321 } else if ((!ppsc->hwradiooff) &&
2322 (e_rfpowerstate_toset == ERFOFF)) {
2323 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2324 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2325
2326 e_rfpowerstate_toset = ERFOFF;
2327 ppsc->hwradiooff = true;
2328 b_actuallyset = true;
2329 }
2330
2331 if (b_actuallyset) {
2332 spin_lock(&rtlpriv->locks.rf_ps_lock);
2333 ppsc->rfchange_inprogress = false;
2334 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2335 } else {
2336 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2337 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2338
2339 spin_lock(&rtlpriv->locks.rf_ps_lock);
2340 ppsc->rfchange_inprogress = false;
2341 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2342 }
2343
2344 *valid = 1;
2345 return !ppsc->hwradiooff;
2346
2347 }
2348
2349 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2350 u8 *p_macaddr, bool is_group, u8 enc_algo,
2351 bool is_wepkey, bool clear_all)
2352 {
2353 struct rtl_priv *rtlpriv = rtl_priv(hw);
2354 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2355 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2356 u8 *macaddr = p_macaddr;
2357 u32 entry_id = 0;
2358 bool is_pairwise = false;
2359 static u8 cam_const_addr[4][6] = {
2360 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2361 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2362 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2363 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2364 };
2365 static u8 cam_const_broad[] = {
2366 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2367 };
2368
2369 if (clear_all) {
2370 u8 idx = 0;
2371 u8 cam_offset = 0;
2372 u8 clear_number = 5;
2373
2374 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2375
2376 for (idx = 0; idx < clear_number; idx++) {
2377 rtl_cam_mark_invalid(hw, cam_offset + idx);
2378 rtl_cam_empty_entry(hw, cam_offset + idx);
2379
2380 if (idx < 5) {
2381 memset(rtlpriv->sec.key_buf[idx], 0,
2382 MAX_KEY_LEN);
2383 rtlpriv->sec.key_len[idx] = 0;
2384 }
2385 }
2386
2387 } else {
2388 switch (enc_algo) {
2389 case WEP40_ENCRYPTION:
2390 enc_algo = CAM_WEP40;
2391 break;
2392 case WEP104_ENCRYPTION:
2393 enc_algo = CAM_WEP104;
2394 break;
2395 case TKIP_ENCRYPTION:
2396 enc_algo = CAM_TKIP;
2397 break;
2398 case AESCCMP_ENCRYPTION:
2399 enc_algo = CAM_AES;
2400 break;
2401 default:
2402 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2403 "switch case not process\n");
2404 enc_algo = CAM_TKIP;
2405 break;
2406 }
2407
2408 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2409 macaddr = cam_const_addr[key_index];
2410 entry_id = key_index;
2411 } else {
2412 if (is_group) {
2413 macaddr = cam_const_broad;
2414 entry_id = key_index;
2415 } else {
2416 if (mac->opmode == NL80211_IFTYPE_AP ||
2417 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2418 entry_id =
2419 rtl_cam_get_free_entry(hw, p_macaddr);
2420 if (entry_id >= TOTAL_CAM_ENTRY) {
2421 RT_TRACE(rtlpriv, COMP_SEC,
2422 DBG_EMERG,
2423 "Can not find free hw security cam entry\n");
2424 return;
2425 }
2426 } else {
2427 entry_id = CAM_PAIRWISE_KEY_POSITION;
2428 }
2429 key_index = PAIRWISE_KEYIDX;
2430 is_pairwise = true;
2431 }
2432 }
2433
2434 if (rtlpriv->sec.key_len[key_index] == 0) {
2435 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2436 "delete one entry, entry_id is %d\n",
2437 entry_id);
2438 if (mac->opmode == NL80211_IFTYPE_AP ||
2439 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2440 rtl_cam_del_entry(hw, p_macaddr);
2441 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2442 } else {
2443 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2444 "add one entry\n");
2445 if (is_pairwise) {
2446 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2447 "set Pairwise key\n");
2448
2449 rtl_cam_add_one_entry(hw, macaddr, key_index,
2450 entry_id, enc_algo,
2451 CAM_CONFIG_NO_USEDK,
2452 rtlpriv->sec.key_buf[key_index]);
2453 } else {
2454 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2455 "set group key\n");
2456
2457 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2458 rtl_cam_add_one_entry(hw,
2459 rtlefuse->dev_addr,
2460 PAIRWISE_KEYIDX,
2461 CAM_PAIRWISE_KEY_POSITION,
2462 enc_algo,
2463 CAM_CONFIG_NO_USEDK,
2464 rtlpriv->sec.key_buf
2465 [entry_id]);
2466 }
2467
2468 rtl_cam_add_one_entry(hw, macaddr, key_index,
2469 entry_id, enc_algo,
2470 CAM_CONFIG_NO_USEDK,
2471 rtlpriv->sec.key_buf[entry_id]);
2472 }
2473
2474 }
2475 }
2476 }
2477
2478 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2479 {
2480 struct rtl_priv *rtlpriv = rtl_priv(hw);
2481
2482 rtlpriv->btcoexist.bt_coexistence =
2483 rtlpriv->btcoexist.eeprom_bt_coexist;
2484 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2485 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2486
2487 if (rtlpriv->btcoexist.reg_bt_iso == 2)
2488 rtlpriv->btcoexist.bt_ant_isolation =
2489 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2490 else
2491 rtlpriv->btcoexist.bt_ant_isolation =
2492 rtlpriv->btcoexist.reg_bt_iso;
2493
2494 rtlpriv->btcoexist.bt_radio_shared_type =
2495 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2496
2497 if (rtlpriv->btcoexist.bt_coexistence) {
2498 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2499 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2500 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2501 rtlpriv->btcoexist.bt_service = BT_SCO;
2502 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2503 rtlpriv->btcoexist.bt_service = BT_BUSY;
2504 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2505 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2506 else
2507 rtlpriv->btcoexist.bt_service = BT_IDLE;
2508
2509 rtlpriv->btcoexist.bt_edca_ul = 0;
2510 rtlpriv->btcoexist.bt_edca_dl = 0;
2511 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2512 }
2513 }
2514
2515 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2516 bool auto_load_fail, u8 *hwinfo)
2517 {
2518 struct rtl_priv *rtlpriv = rtl_priv(hw);
2519 u8 value;
2520
2521 if (!auto_load_fail) {
2522 rtlpriv->btcoexist.eeprom_bt_coexist =
2523 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2524 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2525 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2526 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2527 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2528 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2529 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2530 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2531 ((value & 0x20) >> 5);
2532 } else {
2533 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2534 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2535 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2536 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2537 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2538 }
2539
2540 rtl8188ee_bt_var_init(hw);
2541 }
2542
2543 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2544 {
2545 struct rtl_priv *rtlpriv = rtl_priv(hw);
2546
2547 /* 0:Low, 1:High, 2:From Efuse. */
2548 rtlpriv->btcoexist.reg_bt_iso = 2;
2549 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2550 rtlpriv->btcoexist.reg_bt_sco = 3;
2551 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2552 rtlpriv->btcoexist.reg_bt_sco = 0;
2553 }
2554
2555 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2556 {
2557 struct rtl_priv *rtlpriv = rtl_priv(hw);
2558 struct rtl_phy *rtlphy = &rtlpriv->phy;
2559 u8 u1_tmp;
2560
2561 if (rtlpriv->btcoexist.bt_coexistence &&
2562 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2563 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2564 if (rtlpriv->btcoexist.bt_ant_isolation)
2565 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2566
2567 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2568 BIT_OFFSET_LEN_MASK_32(0, 1);
2569 u1_tmp = u1_tmp |
2570 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2571 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2572 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2573 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2574 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2575
2576 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2577 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2578 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2579
2580 /* Config to 1T1R. */
2581 if (rtlphy->rf_type == RF_1T1R) {
2582 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2583 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2584 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2585
2586 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2587 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2588 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2589 }
2590 }
2591 }
2592
2593 void rtl88ee_suspend(struct ieee80211_hw *hw)
2594 {
2595 }
2596
2597 void rtl88ee_resume(struct ieee80211_hw *hw)
2598 {
2599 } 1
2 #include <linux/kernel.h>
3 #include <linux/mutex.h>
4 #include <linux/spinlock.h>
5 #include <linux/errno.h>
6 #include <verifier/rcv.h>
7 #include <linux/list.h>
8
9 /* mutexes */
10 extern int mutex_lock_interruptible(struct mutex *lock);
11 extern int mutex_lock_killable(struct mutex *lock);
12 extern void mutex_lock(struct mutex *lock);
13
14 /* mutex model functions */
15 extern void ldv_mutex_lock(struct mutex *lock, char *sign);
16 extern int ldv_mutex_is_locked(struct mutex *lock, char *sign);
17 extern void ldv_mutex_unlock(struct mutex *lock, char *sign);
18
19
20 /* Spin locks */
21 extern void __ldv_spin_lock(spinlock_t *lock);
22 extern void __ldv_spin_unlock(spinlock_t *lock);
23 extern int __ldv_spin_trylock(spinlock_t *lock);
24 extern void __ldv_spin_unlock_wait(spinlock_t *lock);
25 extern void __ldv_spin_can_lock(spinlock_t *lock);
26 extern int __ldv_atomic_dec_and_lock(spinlock_t *lock);
27
28 /* spin model functions */
29 extern void ldv_spin_lock(spinlock_t *lock, char *sign);
30 extern void ldv_spin_unlock(spinlock_t *lock, char *sign);
31 extern int ldv_spin_is_locked(spinlock_t *lock, char *sign);
32
33 /* Support for list binder functions */
34 static inline struct list_head *ldv_list_get_first(struct list_head *head) {
35 return head->next;
36 }
37
38 static inline int ldv_list_is_stop(struct list_head *pos, struct list_head *head) {
39 return pos==head;
40 }
41
42 static inline struct list_head *ldv_list_get_next(struct list_head *pos) {
43 return pos->next;
44 }
45
46 #include <linux/mutex.h>
47 #include <linux/slab.h>
48 #include <verifier/rcv.h>
49 #include <linux/timer.h>
50 #include <linux/gfp.h>
51 extern struct timer_list * ldv_timer_list_4;
52 extern int ldv_timer_1_3;
53 extern int pci_counter;
54 extern struct timer_list * ldv_timer_list_2_0;
55 extern struct timer_list * ldv_timer_list_3;
56 extern int ldv_timer_2_1;
57 extern int ldv_state_variable_0;
58 extern int ldv_state_variable_5;
59 extern int ldv_timer_state_3 = 0;
60 extern int ldv_timer_2_2;
61 extern int ldv_timer_2_3;
62 extern int ldv_timer_1_0;
63 extern struct pci_dev *rtl88ee_driver_group1;
64 extern int ldv_timer_state_4 = 0;
65 extern int ref_cnt;
66 extern int ldv_state_variable_1;
67 extern int ldv_state_variable_7;
68 extern struct timer_list * ldv_timer_list_1_3;
69 extern struct sk_buff *rtl8188ee_hal_ops_group0;
70 extern struct timer_list * ldv_timer_list_1_1;
71 extern struct timer_list * ldv_timer_list_2_1;
72 extern struct ieee80211_hw *rtl8188ee_hal_ops_group1;
73 extern struct timer_list * ldv_timer_list_1_0;
74 extern int ldv_state_variable_6;
75 extern int ldv_timer_1_2;
76 extern int ldv_timer_2_0;
77 extern struct ieee80211_sta *rtl8188ee_hal_ops_group2;
78 extern int ldv_timer_1_1;
79 extern int ldv_state_variable_2;
80 extern struct timer_list * ldv_timer_list_1_2;
81 extern int LDV_IN_INTERRUPT = 1;
82 extern struct device *rtlwifi_pm_ops_group1;
83 extern struct mutex fs_mutex;
84 extern int ldv_state_variable_3;
85 extern struct timer_list * ldv_timer_list_2_3;
86 extern struct mutex ar_mutex;
87 extern struct timer_list * ldv_timer_list_2_2;
88 extern int ldv_state_variable_4;
89 extern void ldv_pci_driver_5(void);
90 extern void choose_timer_2(void);
91 extern int reg_timer_2(struct timer_list * timer, void (*function)(unsigned long), unsigned long data);
92 extern void activate_pending_timer_2(struct timer_list * timer, unsigned long data, int pending_flag);
93 extern void choose_timer_3(struct timer_list * timer);
94 extern void activate_pending_timer_4(struct timer_list * timer, unsigned long data, int pending_flag);
95 extern void activate_pending_timer_1(struct timer_list * timer, unsigned long data, int pending_flag);
96 extern void choose_timer_4(struct timer_list * timer);
97 extern void timer_init_2(void);
98 extern void timer_init_1(void);
99 extern void disable_suitable_timer_3(struct timer_list * timer);
100 extern void disable_suitable_timer_4(struct timer_list * timer);
101 extern void ldv_dev_pm_ops_6(void);
102 extern int reg_timer_1(struct timer_list * timer, void (*function)(unsigned long), unsigned long data);
103 extern int reg_timer_4(struct timer_list * timer);
104 extern void disable_suitable_timer_2(struct timer_list * timer);
105 extern void disable_suitable_timer_1(struct timer_list * timer);
106 extern void activate_suitable_timer_1(struct timer_list * timer, unsigned long data);
107 extern void activate_pending_timer_3(struct timer_list * timer, unsigned long data, int pending_flag);
108 extern int evil_hack_fs_lock(void);
109 extern int __VERIFIER_nondet_int(void);
110 extern int reg_timer_3(struct timer_list * timer);
111 extern void ldv_initialyze_rtl_hal_ops_7(void);
112 extern void choose_timer_1(void);
113 extern void ldv_timer_1(int state, struct timer_list * timer);
114 extern void activate_suitable_timer_2(struct timer_list * timer, unsigned long data);
115 extern int evil_hack_ar_lock(void);
116 extern void ldv_timer_2(int state, struct timer_list * timer);
117 #line 1 "/work/ldvuser/andrianov/work/current--X--drivers/net/wireless/--X--defaultlinux-4.5-rc7--X--races--X--cpachecker/linux-4.5-rc7/csd_deg_dscv/376/dscv_tempdir/dscv/ri/races/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c"
118 /******************************************************************************
119 *
120 * Copyright(c) 2009-2013 Realtek Corporation.
121 *
122 * This program is free software; you can redistribute it and/or modify it
123 * under the terms of version 2 of the GNU General Public License as
124 * published by the Free Software Foundation.
125 *
126 * This program is distributed in the hope that it will be useful, but WITHOUT
127 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
128 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
129 * more details.
130 *
131 * The full GNU General Public License is included in this distribution in the
132 * file called LICENSE.
133 *
134 * Contact Information:
135 * wlanfae <wlanfae@realtek.com>
136 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
137 * Hsinchu 300, Taiwan.
138 *
139 * Larry Finger <Larry.Finger@lwfinger.net>
140 *
141 *****************************************************************************/
142
143 #include "../wifi.h"
144 #include "../efuse.h"
145 #include "../base.h"
146 #include "../regd.h"
147 #include "../cam.h"
148 #include "../ps.h"
149 #include "../pci.h"
150 #include "../pwrseqcmd.h"
151 #include "reg.h"
152 #include "def.h"
153 #include "phy.h"
154 #include "dm.h"
155 #include "fw.h"
156 #include "led.h"
157 #include "hw.h"
158 #include "pwrseq.h"
159
160 #define LLT_CONFIG 5
161
162 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
163 u8 set_bits, u8 clear_bits)
164 {
165 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
166 struct rtl_priv *rtlpriv = rtl_priv(hw);
167
168 rtlpci->reg_bcn_ctrl_val |= set_bits;
169 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
170
171 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
172 }
173
174 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
175 {
176 struct rtl_priv *rtlpriv = rtl_priv(hw);
177 u8 tmp1byte;
178
179 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
180 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
181 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
182 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
183 tmp1byte &= ~(BIT(0));
184 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
185 }
186
187 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
188 {
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 u8 tmp1byte;
191
192 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
193 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
194 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
195 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
196 tmp1byte |= BIT(0);
197 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
198 }
199
200 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
201 {
202 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
203 }
204
205 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
206 {
207 struct rtl_priv *rtlpriv = rtl_priv(hw);
208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
209 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
210 unsigned long flags;
211
212 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
213 while (skb_queue_len(&ring->queue)) {
214 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
215 struct sk_buff *skb = __skb_dequeue(&ring->queue);
216
217 pci_unmap_single(rtlpci->pdev,
218 rtlpriv->cfg->ops->get_desc(
219 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
220 skb->len, PCI_DMA_TODEVICE);
221 kfree_skb(skb);
222 ring->idx = (ring->idx + 1) % ring->entries;
223 }
224 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
225 }
226
227 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
228 {
229 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
230 }
231
232 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
233 u8 rpwm_val, bool b_need_turn_off_ckk)
234 {
235 struct rtl_priv *rtlpriv = rtl_priv(hw);
236 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
237 bool b_support_remote_wake_up;
238 u32 count = 0, isr_regaddr, content;
239 bool schedule_timer = b_need_turn_off_ckk;
240 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
241 (u8 *)(&b_support_remote_wake_up));
242
243 if (!rtlhal->fw_ready)
244 return;
245 if (!rtlpriv->psc.fw_current_inpsmode)
246 return;
247
248 while (1) {
249 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
250 if (rtlhal->fw_clk_change_in_progress) {
251 while (rtlhal->fw_clk_change_in_progress) {
252 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
253 count++;
254 udelay(100);
255 if (count > 1000)
256 return;
257 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
258 }
259 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
260 } else {
261 rtlhal->fw_clk_change_in_progress = false;
262 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
263 break;
264 }
265 }
266
267 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
268 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
269 if (FW_PS_IS_ACK(rpwm_val)) {
270 isr_regaddr = REG_HISR;
271 content = rtl_read_dword(rtlpriv, isr_regaddr);
272 while (!(content & IMR_CPWM) && (count < 500)) {
273 udelay(50);
274 count++;
275 content = rtl_read_dword(rtlpriv, isr_regaddr);
276 }
277
278 if (content & IMR_CPWM) {
279 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
280 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
281 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
282 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
283 rtlhal->fw_ps_state);
284 }
285 }
286
287 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
288 rtlhal->fw_clk_change_in_progress = false;
289 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
290 if (schedule_timer) {
291 mod_timer(&rtlpriv->works.fw_clockoff_timer,
292 jiffies + MSECS(10));
293 }
294
295 } else {
296 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
297 rtlhal->fw_clk_change_in_progress = false;
298 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
299 }
300 }
301
302 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
303 u8 rpwm_val)
304 {
305 struct rtl_priv *rtlpriv = rtl_priv(hw);
306 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
308 struct rtl8192_tx_ring *ring;
309 enum rf_pwrstate rtstate;
310 bool schedule_timer = false;
311 u8 queue;
312
313 if (!rtlhal->fw_ready)
314 return;
315 if (!rtlpriv->psc.fw_current_inpsmode)
316 return;
317 if (!rtlhal->allow_sw_to_change_hwclc)
318 return;
319 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
320 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
321 return;
322
323 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
324 ring = &rtlpci->tx_ring[queue];
325 if (skb_queue_len(&ring->queue)) {
326 schedule_timer = true;
327 break;
328 }
329 }
330
331 if (schedule_timer) {
332 mod_timer(&rtlpriv->works.fw_clockoff_timer,
333 jiffies + MSECS(10));
334 return;
335 }
336
337 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
338 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
339 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
340 if (!rtlhal->fw_clk_change_in_progress) {
341 rtlhal->fw_clk_change_in_progress = true;
342 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
343 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
344 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
345 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
346 &rpwm_val);
347 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
348 rtlhal->fw_clk_change_in_progress = false;
349 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
350 } else {
351 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
352 mod_timer(&rtlpriv->works.fw_clockoff_timer,
353 jiffies + MSECS(10));
354 }
355 }
356 }
357
358 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
359 {
360 u8 rpwm_val = 0;
361
362 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
363 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
364 }
365
366 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
367 {
368 u8 rpwm_val = 0;
369 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
370 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
371 }
372 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
373 {
374 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
375
376 _rtl88ee_set_fw_ps_rf_off_low_power(hw);
377 }
378
379 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
380 {
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
383 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
384 bool fw_current_inps = false;
385 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
386
387 if (ppsc->low_power_enable) {
388 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
389 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
390 rtlhal->allow_sw_to_change_hwclc = false;
391 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
392 &fw_pwrmode);
393 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
394 (u8 *)(&fw_current_inps));
395 } else {
396 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */
397 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
398 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
399 &fw_pwrmode);
400 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
401 (u8 *)(&fw_current_inps));
402 }
403 }
404
405 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
406 {
407 struct rtl_priv *rtlpriv = rtl_priv(hw);
408 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
409 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
410 bool fw_current_inps = true;
411 u8 rpwm_val;
412
413 if (ppsc->low_power_enable) {
414 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */
415 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
416 (u8 *)(&fw_current_inps));
417 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
418 &ppsc->fwctrl_psmode);
419 rtlhal->allow_sw_to_change_hwclc = true;
420 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
421 } else {
422 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */
423 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
424 (u8 *)(&fw_current_inps));
425 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
426 &ppsc->fwctrl_psmode);
427 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
428 }
429 }
430
431 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
432 {
433 struct rtl_priv *rtlpriv = rtl_priv(hw);
434 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
435 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
436
437 switch (variable) {
438 case HW_VAR_RCR:
439 *((u32 *)(val)) = rtlpci->receive_config;
440 break;
441 case HW_VAR_RF_STATE:
442 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
443 break;
444 case HW_VAR_FWLPS_RF_ON:{
445 enum rf_pwrstate rfstate;
446 u32 val_rcr;
447
448 rtlpriv->cfg->ops->get_hw_reg(hw,
449 HW_VAR_RF_STATE,
450 (u8 *)(&rfstate));
451 if (rfstate == ERFOFF) {
452 *((bool *)(val)) = true;
453 } else {
454 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
455 val_rcr &= 0x00070000;
456 if (val_rcr)
457 *((bool *)(val)) = false;
458 else
459 *((bool *)(val)) = true;
460 }
461 break; }
462 case HW_VAR_FW_PSMODE_STATUS:
463 *((bool *)(val)) = ppsc->fw_current_inpsmode;
464 break;
465 case HW_VAR_CORRECT_TSF:{
466 u64 tsf;
467 u32 *ptsf_low = (u32 *)&tsf;
468 u32 *ptsf_high = ((u32 *)&tsf) + 1;
469
470 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
471 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
472
473 *((u64 *)(val)) = tsf;
474 break; }
475 default:
476 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
477 "switch case not process %x\n", variable);
478 break;
479 }
480 }
481
482 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
483 {
484 struct rtl_priv *rtlpriv = rtl_priv(hw);
485 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
486 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
487 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
488 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
489 u8 idx;
490
491 switch (variable) {
492 case HW_VAR_ETHER_ADDR:
493 for (idx = 0; idx < ETH_ALEN; idx++) {
494 rtl_write_byte(rtlpriv, (REG_MACID + idx),
495 val[idx]);
496 }
497 break;
498 case HW_VAR_BASIC_RATE:{
499 u16 b_rate_cfg = ((u16 *)val)[0];
500 u8 rate_index = 0;
501 b_rate_cfg = b_rate_cfg & 0x15f;
502 b_rate_cfg |= 0x01;
503 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
504 rtl_write_byte(rtlpriv, REG_RRSR + 1,
505 (b_rate_cfg >> 8) & 0xff);
506 while (b_rate_cfg > 0x1) {
507 b_rate_cfg = (b_rate_cfg >> 1);
508 rate_index++;
509 }
510 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
511 rate_index);
512 break;
513 }
514 case HW_VAR_BSSID:
515 for (idx = 0; idx < ETH_ALEN; idx++) {
516 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
517 val[idx]);
518 }
519 break;
520 case HW_VAR_SIFS:
521 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
522 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
523
524 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
525 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
526
527 if (!mac->ht_enable)
528 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
529 0x0e0e);
530 else
531 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
532 *((u16 *)val));
533 break;
534 case HW_VAR_SLOT_TIME:{
535 u8 e_aci;
536
537 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
538 "HW_VAR_SLOT_TIME %x\n", val[0]);
539
540 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
541
542 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
543 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
544 &e_aci);
545 }
546 break;
547 }
548 case HW_VAR_ACK_PREAMBLE:{
549 u8 reg_tmp;
550 u8 short_preamble = (bool)*val;
551 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
552 if (short_preamble) {
553 reg_tmp |= 0x02;
554 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
555 2, reg_tmp);
556 } else {
557 reg_tmp |= 0xFD;
558 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
559 2, reg_tmp);
560 }
561 break; }
562 case HW_VAR_WPA_CONFIG:
563 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
564 break;
565 case HW_VAR_AMPDU_MIN_SPACE:{
566 u8 min_spacing_to_set;
567 u8 sec_min_space;
568
569 min_spacing_to_set = *val;
570 if (min_spacing_to_set <= 7) {
571 sec_min_space = 0;
572
573 if (min_spacing_to_set < sec_min_space)
574 min_spacing_to_set = sec_min_space;
575
576 mac->min_space_cfg = ((mac->min_space_cfg &
577 0xf8) |
578 min_spacing_to_set);
579
580 *val = min_spacing_to_set;
581
582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
584 mac->min_space_cfg);
585
586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
587 mac->min_space_cfg);
588 }
589 break; }
590 case HW_VAR_SHORTGI_DENSITY:{
591 u8 density_to_set;
592
593 density_to_set = *val;
594 mac->min_space_cfg |= (density_to_set << 3);
595
596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
598 mac->min_space_cfg);
599
600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
601 mac->min_space_cfg);
602 break;
603 }
604 case HW_VAR_AMPDU_FACTOR:{
605 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
606 u8 factor_toset;
607 u8 *p_regtoset = NULL;
608 u8 index = 0;
609
610 p_regtoset = regtoset_normal;
611
612 factor_toset = *val;
613 if (factor_toset <= 3) {
614 factor_toset = (1 << (factor_toset + 2));
615 if (factor_toset > 0xf)
616 factor_toset = 0xf;
617
618 for (index = 0; index < 4; index++) {
619 if ((p_regtoset[index] & 0xf0) >
620 (factor_toset << 4))
621 p_regtoset[index] =
622 (p_regtoset[index] & 0x0f) |
623 (factor_toset << 4);
624
625 if ((p_regtoset[index] & 0x0f) >
626 factor_toset)
627 p_regtoset[index] =
628 (p_regtoset[index] & 0xf0) |
629 (factor_toset);
630
631 rtl_write_byte(rtlpriv,
632 (REG_AGGLEN_LMT + index),
633 p_regtoset[index]);
634
635 }
636
637 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
638 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
639 factor_toset);
640 }
641 break; }
642 case HW_VAR_AC_PARAM:{
643 u8 e_aci = *val;
644 rtl88e_dm_init_edca_turbo(hw);
645
646 if (rtlpci->acm_method != EACMWAY2_SW)
647 rtlpriv->cfg->ops->set_hw_reg(hw,
648 HW_VAR_ACM_CTRL,
649 &e_aci);
650 break; }
651 case HW_VAR_ACM_CTRL:{
652 u8 e_aci = *val;
653 union aci_aifsn *p_aci_aifsn =
654 (union aci_aifsn *)(&(mac->ac[0].aifs));
655 u8 acm = p_aci_aifsn->f.acm;
656 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
657
658 acm_ctrl = acm_ctrl |
659 ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
660
661 if (acm) {
662 switch (e_aci) {
663 case AC0_BE:
664 acm_ctrl |= ACMHW_BEQEN;
665 break;
666 case AC2_VI:
667 acm_ctrl |= ACMHW_VIQEN;
668 break;
669 case AC3_VO:
670 acm_ctrl |= ACMHW_VOQEN;
671 break;
672 default:
673 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
674 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
675 acm);
676 break;
677 }
678 } else {
679 switch (e_aci) {
680 case AC0_BE:
681 acm_ctrl &= (~ACMHW_BEQEN);
682 break;
683 case AC2_VI:
684 acm_ctrl &= (~ACMHW_VIQEN);
685 break;
686 case AC3_VO:
687 acm_ctrl &= (~ACMHW_VOQEN);
688 break;
689 default:
690 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
691 "switch case not process\n");
692 break;
693 }
694 }
695
696 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
697 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
698 acm_ctrl);
699 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
700 break; }
701 case HW_VAR_RCR:
702 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
703 rtlpci->receive_config = ((u32 *)(val))[0];
704 break;
705 case HW_VAR_RETRY_LIMIT:{
706 u8 retry_limit = *val;
707
708 rtl_write_word(rtlpriv, REG_RL,
709 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
710 retry_limit << RETRY_LIMIT_LONG_SHIFT);
711 break; }
712 case HW_VAR_DUAL_TSF_RST:
713 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
714 break;
715 case HW_VAR_EFUSE_BYTES:
716 rtlefuse->efuse_usedbytes = *((u16 *)val);
717 break;
718 case HW_VAR_EFUSE_USAGE:
719 rtlefuse->efuse_usedpercentage = *val;
720 break;
721 case HW_VAR_IO_CMD:
722 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
723 break;
724 case HW_VAR_SET_RPWM:{
725 u8 rpwm_val;
726
727 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
728 udelay(1);
729
730 if (rpwm_val & BIT(7)) {
731 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
732 } else {
733 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
734 }
735 break; }
736 case HW_VAR_H2C_FW_PWRMODE:
737 rtl88e_set_fw_pwrmode_cmd(hw, *val);
738 break;
739 case HW_VAR_FW_PSMODE_STATUS:
740 ppsc->fw_current_inpsmode = *((bool *)val);
741 break;
742 case HW_VAR_RESUME_CLK_ON:
743 _rtl88ee_set_fw_ps_rf_on(hw);
744 break;
745 case HW_VAR_FW_LPS_ACTION:{
746 bool enter_fwlps = *((bool *)val);
747
748 if (enter_fwlps)
749 _rtl88ee_fwlps_enter(hw);
750 else
751 _rtl88ee_fwlps_leave(hw);
752
753 break; }
754 case HW_VAR_H2C_FW_JOINBSSRPT:{
755 u8 mstatus = *val;
756 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
757 u8 count = 0, dlbcn_count = 0;
758 bool b_recover = false;
759
760 if (mstatus == RT_MEDIA_CONNECT) {
761 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
762 NULL);
763
764 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
765 rtl_write_byte(rtlpriv, REG_CR + 1,
766 (tmp_regcr | BIT(0)));
767
768 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
769 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
770
771 tmp_reg422 =
772 rtl_read_byte(rtlpriv,
773 REG_FWHW_TXQ_CTRL + 2);
774 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
775 tmp_reg422 & (~BIT(6)));
776 if (tmp_reg422 & BIT(6))
777 b_recover = true;
778
779 do {
780 bcnvalid_reg = rtl_read_byte(rtlpriv,
781 REG_TDECTRL+2);
782 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
783 (bcnvalid_reg | BIT(0)));
784 _rtl88ee_return_beacon_queue_skb(hw);
785
786 rtl88e_set_fw_rsvdpagepkt(hw, 0);
787 bcnvalid_reg = rtl_read_byte(rtlpriv,
788 REG_TDECTRL+2);
789 count = 0;
790 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
791 count++;
792 udelay(10);
793 bcnvalid_reg =
794 rtl_read_byte(rtlpriv, REG_TDECTRL+2);
795 }
796 dlbcn_count++;
797 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
798
799 if (bcnvalid_reg & BIT(0))
800 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
801
802 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
803 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
804
805 if (b_recover) {
806 rtl_write_byte(rtlpriv,
807 REG_FWHW_TXQ_CTRL + 2,
808 tmp_reg422);
809 }
810
811 rtl_write_byte(rtlpriv, REG_CR + 1,
812 (tmp_regcr & ~(BIT(0))));
813 }
814 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
815 break; }
816 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
817 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
818 break;
819 case HW_VAR_AID:{
820 u16 u2btmp;
821
822 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
823 u2btmp &= 0xC000;
824 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
825 mac->assoc_id));
826 break; }
827 case HW_VAR_CORRECT_TSF:{
828 u8 btype_ibss = *val;
829
830 if (btype_ibss)
831 _rtl88ee_stop_tx_beacon(hw);
832
833 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
834
835 rtl_write_dword(rtlpriv, REG_TSFTR,
836 (u32)(mac->tsf & 0xffffffff));
837 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
838 (u32)((mac->tsf >> 32) & 0xffffffff));
839
840 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
841
842 if (btype_ibss)
843 _rtl88ee_resume_tx_beacon(hw);
844 break; }
845 case HW_VAR_KEEP_ALIVE: {
846 u8 array[2];
847
848 array[0] = 0xff;
849 array[1] = *((u8 *)val);
850 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
851 2, array);
852 break; }
853 default:
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
855 "switch case not process %x\n", variable);
856 break;
857 }
858 }
859
860 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
861 {
862 struct rtl_priv *rtlpriv = rtl_priv(hw);
863 bool status = true;
864 long count = 0;
865 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
866 _LLT_OP(_LLT_WRITE_ACCESS);
867
868 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
869
870 do {
871 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
872 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
873 break;
874
875 if (count > POLLING_LLT_THRESHOLD) {
876 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
877 "Failed to polling write LLT done at address %d!\n",
878 address);
879 status = false;
880 break;
881 }
882 } while (++count);
883
884 return status;
885 }
886
887 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
888 {
889 struct rtl_priv *rtlpriv = rtl_priv(hw);
890 unsigned short i;
891 u8 txpktbuf_bndy;
892 u8 maxpage;
893 bool status;
894
895 maxpage = 0xAF;
896 txpktbuf_bndy = 0xAB;
897
898 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
899 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
900
901 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
902 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
903 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
904
905 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
906 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
907
908 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
909 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
910 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
911
912 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
913 status = _rtl88ee_llt_write(hw, i, i + 1);
914 if (true != status)
915 return status;
916 }
917
918 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
919 if (true != status)
920 return status;
921
922 for (i = txpktbuf_bndy; i < maxpage; i++) {
923 status = _rtl88ee_llt_write(hw, i, (i + 1));
924 if (true != status)
925 return status;
926 }
927
928 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
929 if (true != status)
930 return status;
931
932 return true;
933 }
934
935 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
936 {
937 struct rtl_priv *rtlpriv = rtl_priv(hw);
938 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
939 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
940 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
941
942 if (rtlpriv->rtlhal.up_first_time)
943 return;
944
945 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
946 rtl88ee_sw_led_on(hw, pLed0);
947 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
948 rtl88ee_sw_led_on(hw, pLed0);
949 else
950 rtl88ee_sw_led_off(hw, pLed0);
951 }
952
953 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
954 {
955 struct rtl_priv *rtlpriv = rtl_priv(hw);
956 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
957 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
958
959 u8 bytetmp;
960 u16 wordtmp;
961
962 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
963 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
964 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
965 /*Auto Power Down to CHIP-off State*/
966 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
967 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
968
969 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
970 /* HW Power on sequence */
971 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
972 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
973 RTL8188EE_NIC_ENABLE_FLOW)) {
974 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
975 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
976 return false;
977 }
978
979 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
980 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
981
982 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
983 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
984
985 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
986 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
987
988 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
989 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
990
991 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
992 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
993 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
994 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
995
996 /*Add for wake up online*/
997 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
998
999 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
1000 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
1001 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
1002 rtl_write_byte(rtlpriv, 0x367, 0x80);
1003
1004 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
1005 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
1006 rtl_write_byte(rtlpriv, MSR, 0x00);
1007
1008 if (!rtlhal->mac_func_enable) {
1009 if (_rtl88ee_llt_table_init(hw) == false) {
1010 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1011 "LLT table init fail\n");
1012 return false;
1013 }
1014 }
1015 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
1016 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
1017
1018 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
1019 wordtmp &= 0xf;
1020 wordtmp |= 0xE771;
1021 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
1022
1023 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1024 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
1025 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
1026
1027 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1028 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
1029 DMA_BIT_MASK(32));
1030 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1031 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
1032 DMA_BIT_MASK(32));
1033 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1034 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1035 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1036 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1037 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1038 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1039 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1040 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1041 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1042 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
1043 DMA_BIT_MASK(32));
1044 rtl_write_dword(rtlpriv, REG_RX_DESA,
1045 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
1046 DMA_BIT_MASK(32));
1047
1048 /* if we want to support 64 bit DMA, we should set it here,
1049 * but now we do not support 64 bit DMA
1050 */
1051 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1052
1053 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
1054 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
1055
1056 if (rtlhal->earlymode_enable) {/*Early mode enable*/
1057 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
1058 bytetmp |= 0x1f;
1059 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
1060 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
1061 }
1062 _rtl88ee_gen_refresh_led_state(hw);
1063 return true;
1064 }
1065
1066 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
1067 {
1068 struct rtl_priv *rtlpriv = rtl_priv(hw);
1069 u8 reg_bw_opmode;
1070 u32 reg_ratr, reg_prsr;
1071
1072 reg_bw_opmode = BW_OPMODE_20MHZ;
1073 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
1074 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1075 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1076
1077 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
1078 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1079 }
1080
1081 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1082 {
1083 struct rtl_priv *rtlpriv = rtl_priv(hw);
1084 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1085 u8 tmp1byte = 0;
1086 u32 tmp4byte = 0, count = 0;
1087
1088 rtl_write_word(rtlpriv, 0x354, 0x8104);
1089 rtl_write_word(rtlpriv, 0x358, 0x24);
1090
1091 rtl_write_word(rtlpriv, 0x350, 0x70c);
1092 rtl_write_byte(rtlpriv, 0x352, 0x2);
1093 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1094 count = 0;
1095 while (tmp1byte && count < 20) {
1096 udelay(10);
1097 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1098 count++;
1099 }
1100 if (0 == tmp1byte) {
1101 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1102 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
1103 rtl_write_word(rtlpriv, 0x350, 0xf70c);
1104 rtl_write_byte(rtlpriv, 0x352, 0x1);
1105 }
1106
1107 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1108 count = 0;
1109 while (tmp1byte && count < 20) {
1110 udelay(10);
1111 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1112 count++;
1113 }
1114
1115 rtl_write_word(rtlpriv, 0x350, 0x718);
1116 rtl_write_byte(rtlpriv, 0x352, 0x2);
1117 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1118 count = 0;
1119 while (tmp1byte && count < 20) {
1120 udelay(10);
1121 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1122 count++;
1123 }
1124
1125 if (ppsc->support_backdoor || (0 == tmp1byte)) {
1126 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1127 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1128 rtl_write_word(rtlpriv, 0x350, 0xf718);
1129 rtl_write_byte(rtlpriv, 0x352, 0x1);
1130 }
1131
1132 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1133 count = 0;
1134 while (tmp1byte && count < 20) {
1135 udelay(10);
1136 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1137 count++;
1138 }
1139 }
1140
1141 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1142 {
1143 struct rtl_priv *rtlpriv = rtl_priv(hw);
1144 u8 sec_reg_value;
1145
1146 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1147 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1148 rtlpriv->sec.pairwise_enc_algorithm,
1149 rtlpriv->sec.group_enc_algorithm);
1150
1151 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1152 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1153 "not open hw encryption\n");
1154 return;
1155 }
1156
1157 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1158
1159 if (rtlpriv->sec.use_defaultkey) {
1160 sec_reg_value |= SCR_TXUSEDK;
1161 sec_reg_value |= SCR_RXUSEDK;
1162 }
1163
1164 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1165
1166 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1167
1168 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1169 "The SECR-value %x\n", sec_reg_value);
1170
1171 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1172 }
1173
1174 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1175 {
1176 struct rtl_priv *rtlpriv = rtl_priv(hw);
1177 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1178 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1179 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1180 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1181 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1182 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1183 bool rtstatus = true;
1184 int err = 0;
1185 u8 tmp_u1b, u1byte;
1186 unsigned long flags;
1187
1188 rtlpriv->rtlhal.being_init_adapter = true;
1189 /* As this function can take a very long time (up to 350 ms)
1190 * and can be called with irqs disabled, reenable the irqs
1191 * to let the other devices continue being serviced.
1192 *
1193 * It is safe doing so since our own interrupts will only be enabled
1194 * in a subsequent step.
1195 */
1196 local_save_flags(flags);
1197 local_irq_enable();
1198 rtlhal->fw_ready = false;
1199
1200 rtlpriv->intf_ops->disable_aspm(hw);
1201
1202 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1203 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1204 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1205 rtlhal->mac_func_enable = true;
1206 } else {
1207 rtlhal->mac_func_enable = false;
1208 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1209 }
1210
1211 rtstatus = _rtl88ee_init_mac(hw);
1212 if (rtstatus != true) {
1213 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1214 err = 1;
1215 goto exit;
1216 }
1217
1218 err = rtl88e_download_fw(hw, false);
1219 if (err) {
1220 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1221 "Failed to download FW. Init HW without FW now..\n");
1222 err = 1;
1223 goto exit;
1224 }
1225 rtlhal->fw_ready = true;
1226 /*fw related variable initialize */
1227 rtlhal->last_hmeboxnum = 0;
1228 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1229 rtlhal->fw_clk_change_in_progress = false;
1230 rtlhal->allow_sw_to_change_hwclc = false;
1231 ppsc->fw_current_inpsmode = false;
1232
1233 rtl88e_phy_mac_config(hw);
1234 /* because last function modify RCR, so we update
1235 * rcr var here, or TP will unstable for receive_config
1236 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1237 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1238 */
1239 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1240 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1241
1242 rtl88e_phy_bb_config(hw);
1243 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1244 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1245
1246 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1247 rtl88e_phy_rf_config(hw);
1248
1249 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1250 RF_CHNLBW, RFREG_OFFSET_MASK);
1251 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1252
1253 _rtl88ee_hw_configure(hw);
1254 rtl_cam_reset_all_entry(hw);
1255 rtl88ee_enable_hw_security_config(hw);
1256
1257 rtlhal->mac_func_enable = true;
1258 ppsc->rfpwr_state = ERFON;
1259
1260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1261 _rtl88ee_enable_aspm_back_door(hw);
1262 rtlpriv->intf_ops->enable_aspm(hw);
1263
1264 if (ppsc->rfpwr_state == ERFON) {
1265 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1266 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1267 (rtlhal->oem_id == RT_CID_819X_HP))) {
1268 rtl88e_phy_set_rfpath_switch(hw, true);
1269 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1270 } else {
1271 rtl88e_phy_set_rfpath_switch(hw, false);
1272 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1273 }
1274 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1275 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1276 ("MAIN_ANT") : ("AUX_ANT"));
1277
1278 if (rtlphy->iqk_initialized) {
1279 rtl88e_phy_iq_calibrate(hw, true);
1280 } else {
1281 rtl88e_phy_iq_calibrate(hw, false);
1282 rtlphy->iqk_initialized = true;
1283 }
1284
1285 rtl88e_dm_check_txpower_tracking(hw);
1286 rtl88e_phy_lc_calibrate(hw);
1287 }
1288
1289 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1290 if (!(tmp_u1b & BIT(0))) {
1291 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1292 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1293 }
1294
1295 if (!(tmp_u1b & BIT(4))) {
1296 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1297 tmp_u1b &= 0x0F;
1298 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1299 udelay(10);
1300 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1301 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1302 }
1303 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));
1304 rtl88e_dm_init(hw);
1305 exit:
1306 local_irq_restore(flags);
1307 rtlpriv->rtlhal.being_init_adapter = false;
1308 return err;
1309 }
1310
1311 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1312 {
1313 struct rtl_priv *rtlpriv = rtl_priv(hw);
1314 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1315 enum version_8188e version = VERSION_UNKNOWN;
1316 u32 value32;
1317
1318 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1319 if (value32 & TRP_VAUX_EN) {
1320 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1321 } else {
1322 version = NORMAL_CHIP;
1323 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1324 version = version | ((value32 & VENDOR_ID) ?
1325 CHIP_VENDOR_UMC : 0);
1326 }
1327
1328 rtlphy->rf_type = RF_1T1R;
1329 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1330 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1331 "RF_2T2R" : "RF_1T1R");
1332
1333 return version;
1334 }
1335
1336 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1337 enum nl80211_iftype type)
1338 {
1339 struct rtl_priv *rtlpriv = rtl_priv(hw);
1340 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1341 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1342 u8 mode = MSR_NOLINK;
1343
1344 switch (type) {
1345 case NL80211_IFTYPE_UNSPECIFIED:
1346 mode = MSR_NOLINK;
1347 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1348 "Set Network type to NO LINK!\n");
1349 break;
1350 case NL80211_IFTYPE_ADHOC:
1351 case NL80211_IFTYPE_MESH_POINT:
1352 mode = MSR_ADHOC;
1353 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1354 "Set Network type to Ad Hoc!\n");
1355 break;
1356 case NL80211_IFTYPE_STATION:
1357 mode = MSR_INFRA;
1358 ledaction = LED_CTL_LINK;
1359 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1360 "Set Network type to STA!\n");
1361 break;
1362 case NL80211_IFTYPE_AP:
1363 mode = MSR_AP;
1364 ledaction = LED_CTL_LINK;
1365 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1366 "Set Network type to AP!\n");
1367 break;
1368 default:
1369 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1370 "Network type %d not support!\n", type);
1371 return 1;
1372 break;
1373 }
1374
1375 /* MSR_INFRA == Link in infrastructure network;
1376 * MSR_ADHOC == Link in ad hoc network;
1377 * Therefore, check link state is necessary.
1378 *
1379 * MSR_AP == AP mode; link state is not cared here.
1380 */
1381 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1382 mode = MSR_NOLINK;
1383 ledaction = LED_CTL_NO_LINK;
1384 }
1385
1386 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1387 _rtl88ee_stop_tx_beacon(hw);
1388 _rtl88ee_enable_bcn_sub_func(hw);
1389 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1390 _rtl88ee_resume_tx_beacon(hw);
1391 _rtl88ee_disable_bcn_sub_func(hw);
1392 } else {
1393 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1394 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1395 mode);
1396 }
1397
1398 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1399 rtlpriv->cfg->ops->led_control(hw, ledaction);
1400 if (mode == MSR_AP)
1401 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1402 else
1403 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1404 return 0;
1405 }
1406
1407 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1408 {
1409 struct rtl_priv *rtlpriv = rtl_priv(hw);
1410 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1411 u32 reg_rcr = rtlpci->receive_config;
1412
1413 if (rtlpriv->psc.rfpwr_state != ERFON)
1414 return;
1415
1416 if (check_bssid == true) {
1417 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1418 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1419 (u8 *)(®_rcr));
1420 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1421 } else if (check_bssid == false) {
1422 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1423 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1424 rtlpriv->cfg->ops->set_hw_reg(hw,
1425 HW_VAR_RCR, (u8 *)(®_rcr));
1426 }
1427
1428 }
1429
1430 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1431 enum nl80211_iftype type)
1432 {
1433 struct rtl_priv *rtlpriv = rtl_priv(hw);
1434
1435 if (_rtl88ee_set_media_status(hw, type))
1436 return -EOPNOTSUPP;
1437
1438 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1439 if (type != NL80211_IFTYPE_AP &&
1440 type != NL80211_IFTYPE_MESH_POINT)
1441 rtl88ee_set_check_bssid(hw, true);
1442 } else {
1443 rtl88ee_set_check_bssid(hw, false);
1444 }
1445
1446 return 0;
1447 }
1448
1449 /* don't set REG_EDCA_BE_PARAM here
1450 * because mac80211 will send pkt when scan
1451 */
1452 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1453 {
1454 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 rtl88e_dm_init_edca_turbo(hw);
1456 switch (aci) {
1457 case AC1_BK:
1458 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1459 break;
1460 case AC0_BE:
1461 break;
1462 case AC2_VI:
1463 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1464 break;
1465 case AC3_VO:
1466 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1467 break;
1468 default:
1469 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1470 break;
1471 }
1472 }
1473
1474 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1475 {
1476 struct rtl_priv *rtlpriv = rtl_priv(hw);
1477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1478
1479 rtl_write_dword(rtlpriv, REG_HIMR,
1480 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1481 rtl_write_dword(rtlpriv, REG_HIMRE,
1482 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1483 rtlpci->irq_enabled = true;
1484 /* there are some C2H CMDs have been sent
1485 * before system interrupt is enabled, e.g., C2H, CPWM.
1486 * So we need to clear all C2H events that FW has notified,
1487 * otherwise FW won't schedule any commands anymore.
1488 */
1489 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1490 /*enable system interrupt*/
1491 rtl_write_dword(rtlpriv, REG_HSIMR,
1492 rtlpci->sys_irq_mask & 0xFFFFFFFF);
1493 }
1494
1495 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1496 {
1497 struct rtl_priv *rtlpriv = rtl_priv(hw);
1498 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1499
1500 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1501 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1502 rtlpci->irq_enabled = false;
1503 /*synchronize_irq(rtlpci->pdev->irq);*/
1504 }
1505
1506 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1507 {
1508 struct rtl_priv *rtlpriv = rtl_priv(hw);
1509 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1510 u8 u1b_tmp;
1511 u32 count = 0;
1512 rtlhal->mac_func_enable = false;
1513 rtlpriv->intf_ops->enable_aspm(hw);
1514
1515 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1516 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1517 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1518
1519 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1520 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1521 udelay(10);
1522 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1523 count++;
1524 }
1525 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1526
1527 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1528 PWR_INTF_PCI_MSK,
1529 RTL8188EE_NIC_LPS_ENTER_FLOW);
1530
1531 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1532
1533 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1534 rtl88e_firmware_selfreset(hw);
1535
1536 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1537 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1538 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1539
1540 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1541 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1542
1543 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1544 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1545
1546 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1547 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1548 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1549 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1550
1551 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1552
1553 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1554 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1555 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1556
1557 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1558 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1559 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1560 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1561
1562 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1563 }
1564
1565 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1566 {
1567 struct rtl_priv *rtlpriv = rtl_priv(hw);
1568 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1569 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1570 enum nl80211_iftype opmode;
1571
1572 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1573
1574 mac->link_state = MAC80211_NOLINK;
1575 opmode = NL80211_IFTYPE_UNSPECIFIED;
1576
1577 _rtl88ee_set_media_status(hw, opmode);
1578
1579 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1580 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1581 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1582
1583 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1584 _rtl88ee_poweroff_adapter(hw);
1585
1586 /* after power off we should do iqk again */
1587 rtlpriv->phy.iqk_initialized = false;
1588 }
1589
1590 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1591 u32 *p_inta, u32 *p_intb)
1592 {
1593 struct rtl_priv *rtlpriv = rtl_priv(hw);
1594 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1595
1596 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1597 rtl_write_dword(rtlpriv, ISR, *p_inta);
1598
1599 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1600 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1601
1602 }
1603
1604 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1605 {
1606 struct rtl_priv *rtlpriv = rtl_priv(hw);
1607 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1608 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1609 u16 bcn_interval, atim_window;
1610
1611 bcn_interval = mac->beacon_interval;
1612 atim_window = 2; /*FIX MERGE */
1613 rtl88ee_disable_interrupt(hw);
1614 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1615 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1616 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1617 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1618 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1619 rtl_write_byte(rtlpriv, 0x606, 0x30);
1620 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1621 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1622 /*rtl88ee_enable_interrupt(hw);*/
1623 }
1624
1625 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1626 {
1627 struct rtl_priv *rtlpriv = rtl_priv(hw);
1628 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1629 u16 bcn_interval = mac->beacon_interval;
1630
1631 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1632 "beacon_interval:%d\n", bcn_interval);
1633 /*rtl88ee_disable_interrupt(hw);*/
1634 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1635 /*rtl88ee_enable_interrupt(hw);*/
1636 }
1637
1638 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1639 u32 add_msr, u32 rm_msr)
1640 {
1641 struct rtl_priv *rtlpriv = rtl_priv(hw);
1642 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1643
1644 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1645 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1646
1647 if (add_msr)
1648 rtlpci->irq_mask[0] |= add_msr;
1649 if (rm_msr)
1650 rtlpci->irq_mask[0] &= (~rm_msr);
1651 rtl88ee_disable_interrupt(hw);
1652 rtl88ee_enable_interrupt(hw);
1653 }
1654
1655 static u8 _rtl88e_get_chnl_group(u8 chnl)
1656 {
1657 u8 group = 0;
1658
1659 if (chnl < 3)
1660 group = 0;
1661 else if (chnl < 6)
1662 group = 1;
1663 else if (chnl < 9)
1664 group = 2;
1665 else if (chnl < 12)
1666 group = 3;
1667 else if (chnl < 14)
1668 group = 4;
1669 else if (chnl == 14)
1670 group = 5;
1671
1672 return group;
1673 }
1674
1675 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1676 {
1677 int group, txcnt;
1678
1679 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1680 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1681 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1682 }
1683 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1684 if (txcnt == 0) {
1685 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1686 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1687 } else {
1688 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1689 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1690 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1691 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1692 }
1693 }
1694 }
1695
1696 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1697 struct txpower_info_2g *pwrinfo24g,
1698 struct txpower_info_5g *pwrinfo5g,
1699 bool autoload_fail, u8 *hwinfo)
1700 {
1701 struct rtl_priv *rtlpriv = rtl_priv(hw);
1702 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1703
1704 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1705 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1706 (eeaddr+1), hwinfo[eeaddr+1]);
1707 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/
1708 autoload_fail = true;
1709
1710 if (autoload_fail) {
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1712 "auto load fail : Use Default value!\n");
1713 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1714 /* 2.4G default value */
1715 set_24g_base(pwrinfo24g, rfpath);
1716 }
1717 return;
1718 }
1719
1720 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1721 /*2.4G default value*/
1722 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1723 pwrinfo24g->index_cck_base[rfpath][group] =
1724 hwinfo[eeaddr++];
1725 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1726 pwrinfo24g->index_cck_base[rfpath][group] =
1727 0x2D;
1728 }
1729 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1730 pwrinfo24g->index_bw40_base[rfpath][group] =
1731 hwinfo[eeaddr++];
1732 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1733 pwrinfo24g->index_bw40_base[rfpath][group] =
1734 0x2D;
1735 }
1736 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1737 if (hwinfo[eeaddr] == 0xFF) {
1738 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1739 } else {
1740 pwrinfo24g->bw20_diff[rfpath][0] =
1741 (hwinfo[eeaddr]&0xf0)>>4;
1742 /*bit sign number to 8 bit sign number*/
1743 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1744 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1745 }
1746
1747 if (hwinfo[eeaddr] == 0xFF) {
1748 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1749 } else {
1750 pwrinfo24g->ofdm_diff[rfpath][0] =
1751 (hwinfo[eeaddr]&0x0f);
1752 /*bit sign number to 8 bit sign number*/
1753 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1754 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1755 }
1756 pwrinfo24g->cck_diff[rfpath][0] = 0;
1757 eeaddr++;
1758 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1759 if (hwinfo[eeaddr] == 0xFF) {
1760 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1761 } else {
1762 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1763 (hwinfo[eeaddr]&0xf0)>>4;
1764 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1765 BIT(3))
1766 pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1767 0xF0;
1768 }
1769
1770 if (hwinfo[eeaddr] == 0xFF) {
1771 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1772 0xFE;
1773 } else {
1774 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1775 (hwinfo[eeaddr]&0x0f);
1776 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1777 BIT(3))
1778 pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1779 0xF0;
1780 }
1781 eeaddr++;
1782
1783 if (hwinfo[eeaddr] == 0xFF) {
1784 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1785 } else {
1786 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1787 (hwinfo[eeaddr]&0xf0)>>4;
1788 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1789 BIT(3))
1790 pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1791 0xF0;
1792 }
1793
1794 if (hwinfo[eeaddr] == 0xFF) {
1795 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1796 } else {
1797 pwrinfo24g->cck_diff[rfpath][txcnt] =
1798 (hwinfo[eeaddr]&0x0f);
1799 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1800 BIT(3))
1801 pwrinfo24g->cck_diff[rfpath][txcnt] |=
1802 0xF0;
1803 }
1804 eeaddr++;
1805 }
1806
1807 /*5G default value*/
1808 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1809 pwrinfo5g->index_bw40_base[rfpath][group] =
1810 hwinfo[eeaddr++];
1811 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1812 pwrinfo5g->index_bw40_base[rfpath][group] =
1813 0xFE;
1814 }
1815
1816 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1817
1818 if (hwinfo[eeaddr] == 0xFF) {
1819 pwrinfo5g->bw20_diff[rfpath][0] = 0;
1820 } else {
1821 pwrinfo5g->bw20_diff[rfpath][0] =
1822 (hwinfo[eeaddr]&0xf0)>>4;
1823 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1824 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1825 }
1826
1827 if (hwinfo[eeaddr] == 0xFF) {
1828 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1829 } else {
1830 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1831 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1832 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1833 }
1834 eeaddr++;
1835 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1836 if (hwinfo[eeaddr] == 0xFF) {
1837 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE;
1838 } else {
1839 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1840 (hwinfo[eeaddr]&0xf0)>>4;
1841 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1842 BIT(3))
1843 pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1844 0xF0;
1845 }
1846
1847 if (hwinfo[eeaddr] == 0xFF) {
1848 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE;
1849 } else {
1850 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1851 (hwinfo[eeaddr]&0x0f);
1852 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1853 BIT(3))
1854 pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1855 0xF0;
1856 }
1857 eeaddr++;
1858 }
1859
1860 if (hwinfo[eeaddr] == 0xFF) {
1861 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1862 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1863 } else {
1864 pwrinfo5g->ofdm_diff[rfpath][1] =
1865 (hwinfo[eeaddr]&0xf0)>>4;
1866 pwrinfo5g->ofdm_diff[rfpath][2] =
1867 (hwinfo[eeaddr]&0x0f);
1868 }
1869 eeaddr++;
1870
1871 if (hwinfo[eeaddr] == 0xFF)
1872 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1873 else
1874 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1875 eeaddr++;
1876
1877 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1878 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1879 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE;
1880 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1881 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1882 }
1883 }
1884 }
1885
1886 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1887 bool autoload_fail,
1888 u8 *hwinfo)
1889 {
1890 struct rtl_priv *rtlpriv = rtl_priv(hw);
1891 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1892 struct txpower_info_2g pwrinfo24g;
1893 struct txpower_info_5g pwrinfo5g;
1894 u8 rf_path, index;
1895 u8 i;
1896
1897 read_power_value_fromprom(hw, &pwrinfo24g,
1898 &pwrinfo5g, autoload_fail, hwinfo);
1899
1900 for (rf_path = 0; rf_path < 2; rf_path++) {
1901 for (i = 0; i < 14; i++) {
1902 index = _rtl88e_get_chnl_group(i+1);
1903
1904 rtlefuse->txpwrlevel_cck[rf_path][i] =
1905 pwrinfo24g.index_cck_base[rf_path][index];
1906 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1907 pwrinfo24g.index_bw40_base[rf_path][index];
1908 rtlefuse->txpwr_ht20diff[rf_path][i] =
1909 pwrinfo24g.bw20_diff[rf_path][0];
1910 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1911 pwrinfo24g.ofdm_diff[rf_path][0];
1912 }
1913
1914 for (i = 0; i < 14; i++) {
1915 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1916 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1917 rf_path, i,
1918 rtlefuse->txpwrlevel_cck[rf_path][i],
1919 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1920 }
1921 }
1922
1923 if (!autoload_fail)
1924 rtlefuse->eeprom_thermalmeter =
1925 hwinfo[EEPROM_THERMAL_METER_88E];
1926 else
1927 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1928
1929 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1930 rtlefuse->apk_thermalmeterignore = true;
1931 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1932 }
1933
1934 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1935 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1936 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1937
1938 if (!autoload_fail) {
1939 rtlefuse->eeprom_regulatory =
1940 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1941 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1942 rtlefuse->eeprom_regulatory = 0;
1943 } else {
1944 rtlefuse->eeprom_regulatory = 0;
1945 }
1946 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1947 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1948 }
1949
1950 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1951 {
1952 struct rtl_priv *rtlpriv = rtl_priv(hw);
1953 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1954 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1955 u16 i, usvalue;
1956 u8 hwinfo[HWSET_MAX_SIZE];
1957 u16 eeprom_id;
1958
1959 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1960 rtl_efuse_shadow_map_update(hw);
1961
1962 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1963 HWSET_MAX_SIZE);
1964 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1965 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1966 "RTL819X Not boot from eeprom, check it !!");
1967 return;
1968 } else {
1969 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1970 "boot from neither eeprom nor efuse, check it !!");
1971 return;
1972 }
1973
1974 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
1975 hwinfo, HWSET_MAX_SIZE);
1976
1977 eeprom_id = *((u16 *)&hwinfo[0]);
1978 if (eeprom_id != RTL8188E_EEPROM_ID) {
1979 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1980 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1981 rtlefuse->autoload_failflag = true;
1982 } else {
1983 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1984 rtlefuse->autoload_failflag = false;
1985 }
1986
1987 if (rtlefuse->autoload_failflag == true)
1988 return;
1989 /*VID DID SVID SDID*/
1990 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1991 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1992 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1993 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1994 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1995 "EEPROMId = 0x%4x\n", eeprom_id);
1996 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1997 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1999 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2000 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2001 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2002 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2003 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2004 /*customer ID*/
2005 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
2006 if (rtlefuse->eeprom_oemid == 0xFF)
2007 rtlefuse->eeprom_oemid = 0;
2008
2009 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2010 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2011 /*EEPROM version*/
2012 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
2013 /*mac address*/
2014 for (i = 0; i < 6; i += 2) {
2015 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2016 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2017 }
2018
2019 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2020 "dev_addr: %pM\n", rtlefuse->dev_addr);
2021 /*channel plan */
2022 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
2023 /* set channel plan from efuse */
2024 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2025 /*tx power*/
2026 _rtl88ee_read_txpower_info_from_hwpg(hw,
2027 rtlefuse->autoload_failflag,
2028 hwinfo);
2029 rtlefuse->txpwr_fromeprom = true;
2030
2031 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
2032 rtlefuse->autoload_failflag,
2033 hwinfo);
2034
2035 /*board type*/
2036 rtlefuse->board_type =
2037 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
2038 rtlhal->board_type = rtlefuse->board_type;
2039 /*Wake on wlan*/
2040 rtlefuse->wowlan_enable =
2041 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
2042 /*parse xtal*/
2043 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
2044 if (hwinfo[EEPROM_XTAL_88E])
2045 rtlefuse->crystalcap = 0x20;
2046 /*antenna diversity*/
2047 rtlefuse->antenna_div_cfg =
2048 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
2049 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2050 rtlefuse->antenna_div_cfg = 0;
2051 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
2052 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
2053 rtlefuse->antenna_div_cfg = 0;
2054
2055 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
2056 if (rtlefuse->antenna_div_type == 0xFF)
2057 rtlefuse->antenna_div_type = 0x01;
2058 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
2059 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2060 rtlefuse->antenna_div_cfg = 1;
2061
2062 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2063 switch (rtlefuse->eeprom_oemid) {
2064 case EEPROM_CID_DEFAULT:
2065 if (rtlefuse->eeprom_did == 0x8179) {
2066 if (rtlefuse->eeprom_svid == 0x1025) {
2067 rtlhal->oem_id = RT_CID_819X_ACER;
2068 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2069 rtlefuse->eeprom_smid == 0x0179) ||
2070 (rtlefuse->eeprom_svid == 0x17AA &&
2071 rtlefuse->eeprom_smid == 0x0179)) {
2072 rtlhal->oem_id = RT_CID_819X_LENOVO;
2073 } else if (rtlefuse->eeprom_svid == 0x103c &&
2074 rtlefuse->eeprom_smid == 0x197d) {
2075 rtlhal->oem_id = RT_CID_819X_HP;
2076 } else {
2077 rtlhal->oem_id = RT_CID_DEFAULT;
2078 }
2079 } else {
2080 rtlhal->oem_id = RT_CID_DEFAULT;
2081 }
2082 break;
2083 case EEPROM_CID_TOSHIBA:
2084 rtlhal->oem_id = RT_CID_TOSHIBA;
2085 break;
2086 case EEPROM_CID_QMI:
2087 rtlhal->oem_id = RT_CID_819X_QMI;
2088 break;
2089 case EEPROM_CID_WHQL:
2090 default:
2091 rtlhal->oem_id = RT_CID_DEFAULT;
2092 break;
2093
2094 }
2095 }
2096 }
2097
2098 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
2099 {
2100 struct rtl_priv *rtlpriv = rtl_priv(hw);
2101 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2102 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2103
2104 pcipriv->ledctl.led_opendrain = true;
2105
2106 switch (rtlhal->oem_id) {
2107 case RT_CID_819X_HP:
2108 pcipriv->ledctl.led_opendrain = true;
2109 break;
2110 case RT_CID_819X_LENOVO:
2111 case RT_CID_DEFAULT:
2112 case RT_CID_TOSHIBA:
2113 case RT_CID_CCX:
2114 case RT_CID_819X_ACER:
2115 case RT_CID_WHQL:
2116 default:
2117 break;
2118 }
2119 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2120 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2121 }
2122
2123 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
2124 {
2125 struct rtl_priv *rtlpriv = rtl_priv(hw);
2126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2127 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2128 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2129 u8 tmp_u1b;
2130
2131 rtlhal->version = _rtl88ee_read_chip_version(hw);
2132 if (get_rf_type(rtlphy) == RF_1T1R)
2133 rtlpriv->dm.rfpath_rxenable[0] = true;
2134 else
2135 rtlpriv->dm.rfpath_rxenable[0] =
2136 rtlpriv->dm.rfpath_rxenable[1] = true;
2137 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2138 rtlhal->version);
2139 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2140 if (tmp_u1b & BIT(4)) {
2141 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2142 rtlefuse->epromtype = EEPROM_93C46;
2143 } else {
2144 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2145 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2146 }
2147 if (tmp_u1b & BIT(5)) {
2148 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2149 rtlefuse->autoload_failflag = false;
2150 _rtl88ee_read_adapter_info(hw);
2151 } else {
2152 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2153 }
2154 _rtl88ee_hal_customized_behavior(hw);
2155 }
2156
2157 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
2158 struct ieee80211_sta *sta)
2159 {
2160 struct rtl_priv *rtlpriv = rtl_priv(hw);
2161 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2162 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2163 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2164 u32 ratr_value;
2165 u8 ratr_index = 0;
2166 u8 b_nmode = mac->ht_enable;
2167 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2168 u16 shortgi_rate;
2169 u32 tmp_ratr_value;
2170 u8 curtxbw_40mhz = mac->bw_40;
2171 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2172 1 : 0;
2173 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2174 1 : 0;
2175 enum wireless_mode wirelessmode = mac->mode;
2176 u32 ratr_mask;
2177
2178 if (rtlhal->current_bandtype == BAND_ON_5G)
2179 ratr_value = sta->supp_rates[1] << 4;
2180 else
2181 ratr_value = sta->supp_rates[0];
2182 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2183 ratr_value = 0xfff;
2184 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2185 sta->ht_cap.mcs.rx_mask[0] << 12);
2186 switch (wirelessmode) {
2187 case WIRELESS_MODE_B:
2188 if (ratr_value & 0x0000000c)
2189 ratr_value &= 0x0000000d;
2190 else
2191 ratr_value &= 0x0000000f;
2192 break;
2193 case WIRELESS_MODE_G:
2194 ratr_value &= 0x00000FF5;
2195 break;
2196 case WIRELESS_MODE_N_24G:
2197 case WIRELESS_MODE_N_5G:
2198 b_nmode = 1;
2199 if (get_rf_type(rtlphy) == RF_1T2R ||
2200 get_rf_type(rtlphy) == RF_1T1R)
2201 ratr_mask = 0x000ff005;
2202 else
2203 ratr_mask = 0x0f0ff005;
2204
2205 ratr_value &= ratr_mask;
2206 break;
2207 default:
2208 if (rtlphy->rf_type == RF_1T2R)
2209 ratr_value &= 0x000ff0ff;
2210 else
2211 ratr_value &= 0x0f0ff0ff;
2212
2213 break;
2214 }
2215
2216 if ((rtlpriv->btcoexist.bt_coexistence) &&
2217 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2218 (rtlpriv->btcoexist.bt_cur_state) &&
2219 (rtlpriv->btcoexist.bt_ant_isolation) &&
2220 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2221 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2222 ratr_value &= 0x0fffcfc0;
2223 else
2224 ratr_value &= 0x0FFFFFFF;
2225
2226 if (b_nmode &&
2227 ((curtxbw_40mhz && curshortgi_40mhz) ||
2228 (!curtxbw_40mhz && curshortgi_20mhz))) {
2229 ratr_value |= 0x10000000;
2230 tmp_ratr_value = (ratr_value >> 12);
2231
2232 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2233 if ((1 << shortgi_rate) & tmp_ratr_value)
2234 break;
2235 }
2236
2237 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2238 (shortgi_rate << 4) | (shortgi_rate);
2239 }
2240
2241 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2242
2243 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2244 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2245 }
2246
2247 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2248 struct ieee80211_sta *sta, u8 rssi_level)
2249 {
2250 struct rtl_priv *rtlpriv = rtl_priv(hw);
2251 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2252 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2253 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2254 struct rtl_sta_info *sta_entry = NULL;
2255 u32 ratr_bitmap;
2256 u8 ratr_index;
2257 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2258 ? 1 : 0;
2259 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2260 1 : 0;
2261 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2262 1 : 0;
2263 enum wireless_mode wirelessmode = 0;
2264 bool b_shortgi = false;
2265 u8 rate_mask[5];
2266 u8 macid = 0;
2267 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2268
2269 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2270 wirelessmode = sta_entry->wireless_mode;
2271 if (mac->opmode == NL80211_IFTYPE_STATION ||
2272 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2273 curtxbw_40mhz = mac->bw_40;
2274 else if (mac->opmode == NL80211_IFTYPE_AP ||
2275 mac->opmode == NL80211_IFTYPE_ADHOC)
2276 macid = sta->aid + 1;
2277
2278 if (rtlhal->current_bandtype == BAND_ON_5G)
2279 ratr_bitmap = sta->supp_rates[1] << 4;
2280 else
2281 ratr_bitmap = sta->supp_rates[0];
2282 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2283 ratr_bitmap = 0xfff;
2284 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2285 sta->ht_cap.mcs.rx_mask[0] << 12);
2286 switch (wirelessmode) {
2287 case WIRELESS_MODE_B:
2288 ratr_index = RATR_INX_WIRELESS_B;
2289 if (ratr_bitmap & 0x0000000c)
2290 ratr_bitmap &= 0x0000000d;
2291 else
2292 ratr_bitmap &= 0x0000000f;
2293 break;
2294 case WIRELESS_MODE_G:
2295 ratr_index = RATR_INX_WIRELESS_GB;
2296
2297 if (rssi_level == 1)
2298 ratr_bitmap &= 0x00000f00;
2299 else if (rssi_level == 2)
2300 ratr_bitmap &= 0x00000ff0;
2301 else
2302 ratr_bitmap &= 0x00000ff5;
2303 break;
2304 case WIRELESS_MODE_N_24G:
2305 case WIRELESS_MODE_N_5G:
2306 ratr_index = RATR_INX_WIRELESS_NGB;
2307 if (rtlphy->rf_type == RF_1T2R ||
2308 rtlphy->rf_type == RF_1T1R) {
2309 if (curtxbw_40mhz) {
2310 if (rssi_level == 1)
2311 ratr_bitmap &= 0x000f0000;
2312 else if (rssi_level == 2)
2313 ratr_bitmap &= 0x000ff000;
2314 else
2315 ratr_bitmap &= 0x000ff015;
2316 } else {
2317 if (rssi_level == 1)
2318 ratr_bitmap &= 0x000f0000;
2319 else if (rssi_level == 2)
2320 ratr_bitmap &= 0x000ff000;
2321 else
2322 ratr_bitmap &= 0x000ff005;
2323 }
2324 } else {
2325 if (curtxbw_40mhz) {
2326 if (rssi_level == 1)
2327 ratr_bitmap &= 0x0f8f0000;
2328 else if (rssi_level == 2)
2329 ratr_bitmap &= 0x0f8ff000;
2330 else
2331 ratr_bitmap &= 0x0f8ff015;
2332 } else {
2333 if (rssi_level == 1)
2334 ratr_bitmap &= 0x0f8f0000;
2335 else if (rssi_level == 2)
2336 ratr_bitmap &= 0x0f8ff000;
2337 else
2338 ratr_bitmap &= 0x0f8ff005;
2339 }
2340 }
2341 /*}*/
2342
2343 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2344 (!curtxbw_40mhz && curshortgi_20mhz)) {
2345
2346 if (macid == 0)
2347 b_shortgi = true;
2348 else if (macid == 1)
2349 b_shortgi = false;
2350 }
2351 break;
2352 default:
2353 ratr_index = RATR_INX_WIRELESS_NGB;
2354
2355 if (rtlphy->rf_type == RF_1T2R)
2356 ratr_bitmap &= 0x000ff0ff;
2357 else
2358 ratr_bitmap &= 0x0f0ff0ff;
2359 break;
2360 }
2361 sta_entry->ratr_index = ratr_index;
2362
2363 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2364 "ratr_bitmap :%x\n", ratr_bitmap);
2365 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2366 (ratr_index << 28);
2367 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2368 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2369 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2370 ratr_index, ratr_bitmap,
2371 rate_mask[0], rate_mask[1],
2372 rate_mask[2], rate_mask[3],
2373 rate_mask[4]);
2374 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2375 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2376 }
2377
2378 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2379 struct ieee80211_sta *sta, u8 rssi_level)
2380 {
2381 struct rtl_priv *rtlpriv = rtl_priv(hw);
2382
2383 if (rtlpriv->dm.useramask)
2384 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level);
2385 else
2386 rtl88ee_update_hal_rate_table(hw, sta);
2387 }
2388
2389 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2390 {
2391 struct rtl_priv *rtlpriv = rtl_priv(hw);
2392 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2393 u16 sifs_timer;
2394
2395 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2396 if (!mac->ht_enable)
2397 sifs_timer = 0x0a0a;
2398 else
2399 sifs_timer = 0x0e0e;
2400 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2401 }
2402
2403 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2404 {
2405 struct rtl_priv *rtlpriv = rtl_priv(hw);
2406 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2407 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2408 u32 u4tmp;
2409 bool b_actuallyset = false;
2410
2411 if (rtlpriv->rtlhal.being_init_adapter)
2412 return false;
2413
2414 if (ppsc->swrf_processing)
2415 return false;
2416
2417 spin_lock(&rtlpriv->locks.rf_ps_lock);
2418 if (ppsc->rfchange_inprogress) {
2419 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2420 return false;
2421 } else {
2422 ppsc->rfchange_inprogress = true;
2423 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2424 }
2425
2426 cur_rfstate = ppsc->rfpwr_state;
2427
2428 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2429 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2430
2431 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2432 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2433 "GPIOChangeRF - HW Radio ON, RF ON\n");
2434
2435 e_rfpowerstate_toset = ERFON;
2436 ppsc->hwradiooff = false;
2437 b_actuallyset = true;
2438 } else if ((!ppsc->hwradiooff) &&
2439 (e_rfpowerstate_toset == ERFOFF)) {
2440 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2441 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2442
2443 e_rfpowerstate_toset = ERFOFF;
2444 ppsc->hwradiooff = true;
2445 b_actuallyset = true;
2446 }
2447
2448 if (b_actuallyset) {
2449 spin_lock(&rtlpriv->locks.rf_ps_lock);
2450 ppsc->rfchange_inprogress = false;
2451 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2452 } else {
2453 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2454 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2455
2456 spin_lock(&rtlpriv->locks.rf_ps_lock);
2457 ppsc->rfchange_inprogress = false;
2458 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2459 }
2460
2461 *valid = 1;
2462 return !ppsc->hwradiooff;
2463
2464 }
2465
2466 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2467 u8 *p_macaddr, bool is_group, u8 enc_algo,
2468 bool is_wepkey, bool clear_all)
2469 {
2470 struct rtl_priv *rtlpriv = rtl_priv(hw);
2471 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2472 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2473 u8 *macaddr = p_macaddr;
2474 u32 entry_id = 0;
2475 bool is_pairwise = false;
2476 static u8 cam_const_addr[4][6] = {
2477 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2478 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2479 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2480 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2481 };
2482 static u8 cam_const_broad[] = {
2483 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2484 };
2485
2486 if (clear_all) {
2487 u8 idx = 0;
2488 u8 cam_offset = 0;
2489 u8 clear_number = 5;
2490
2491 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2492
2493 for (idx = 0; idx < clear_number; idx++) {
2494 rtl_cam_mark_invalid(hw, cam_offset + idx);
2495 rtl_cam_empty_entry(hw, cam_offset + idx);
2496
2497 if (idx < 5) {
2498 memset(rtlpriv->sec.key_buf[idx], 0,
2499 MAX_KEY_LEN);
2500 rtlpriv->sec.key_len[idx] = 0;
2501 }
2502 }
2503
2504 } else {
2505 switch (enc_algo) {
2506 case WEP40_ENCRYPTION:
2507 enc_algo = CAM_WEP40;
2508 break;
2509 case WEP104_ENCRYPTION:
2510 enc_algo = CAM_WEP104;
2511 break;
2512 case TKIP_ENCRYPTION:
2513 enc_algo = CAM_TKIP;
2514 break;
2515 case AESCCMP_ENCRYPTION:
2516 enc_algo = CAM_AES;
2517 break;
2518 default:
2519 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2520 "switch case not process\n");
2521 enc_algo = CAM_TKIP;
2522 break;
2523 }
2524
2525 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2526 macaddr = cam_const_addr[key_index];
2527 entry_id = key_index;
2528 } else {
2529 if (is_group) {
2530 macaddr = cam_const_broad;
2531 entry_id = key_index;
2532 } else {
2533 if (mac->opmode == NL80211_IFTYPE_AP ||
2534 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2535 entry_id =
2536 rtl_cam_get_free_entry(hw, p_macaddr);
2537 if (entry_id >= TOTAL_CAM_ENTRY) {
2538 RT_TRACE(rtlpriv, COMP_SEC,
2539 DBG_EMERG,
2540 "Can not find free hw security cam entry\n");
2541 return;
2542 }
2543 } else {
2544 entry_id = CAM_PAIRWISE_KEY_POSITION;
2545 }
2546 key_index = PAIRWISE_KEYIDX;
2547 is_pairwise = true;
2548 }
2549 }
2550
2551 if (rtlpriv->sec.key_len[key_index] == 0) {
2552 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2553 "delete one entry, entry_id is %d\n",
2554 entry_id);
2555 if (mac->opmode == NL80211_IFTYPE_AP ||
2556 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2557 rtl_cam_del_entry(hw, p_macaddr);
2558 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2559 } else {
2560 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2561 "add one entry\n");
2562 if (is_pairwise) {
2563 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2564 "set Pairwise key\n");
2565
2566 rtl_cam_add_one_entry(hw, macaddr, key_index,
2567 entry_id, enc_algo,
2568 CAM_CONFIG_NO_USEDK,
2569 rtlpriv->sec.key_buf[key_index]);
2570 } else {
2571 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2572 "set group key\n");
2573
2574 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2575 rtl_cam_add_one_entry(hw,
2576 rtlefuse->dev_addr,
2577 PAIRWISE_KEYIDX,
2578 CAM_PAIRWISE_KEY_POSITION,
2579 enc_algo,
2580 CAM_CONFIG_NO_USEDK,
2581 rtlpriv->sec.key_buf
2582 [entry_id]);
2583 }
2584
2585 rtl_cam_add_one_entry(hw, macaddr, key_index,
2586 entry_id, enc_algo,
2587 CAM_CONFIG_NO_USEDK,
2588 rtlpriv->sec.key_buf[entry_id]);
2589 }
2590
2591 }
2592 }
2593 }
2594
2595 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2596 {
2597 struct rtl_priv *rtlpriv = rtl_priv(hw);
2598
2599 rtlpriv->btcoexist.bt_coexistence =
2600 rtlpriv->btcoexist.eeprom_bt_coexist;
2601 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2602 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2603
2604 if (rtlpriv->btcoexist.reg_bt_iso == 2)
2605 rtlpriv->btcoexist.bt_ant_isolation =
2606 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2607 else
2608 rtlpriv->btcoexist.bt_ant_isolation =
2609 rtlpriv->btcoexist.reg_bt_iso;
2610
2611 rtlpriv->btcoexist.bt_radio_shared_type =
2612 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2613
2614 if (rtlpriv->btcoexist.bt_coexistence) {
2615 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2616 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2617 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2618 rtlpriv->btcoexist.bt_service = BT_SCO;
2619 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2620 rtlpriv->btcoexist.bt_service = BT_BUSY;
2621 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2622 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2623 else
2624 rtlpriv->btcoexist.bt_service = BT_IDLE;
2625
2626 rtlpriv->btcoexist.bt_edca_ul = 0;
2627 rtlpriv->btcoexist.bt_edca_dl = 0;
2628 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2629 }
2630 }
2631
2632 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2633 bool auto_load_fail, u8 *hwinfo)
2634 {
2635 struct rtl_priv *rtlpriv = rtl_priv(hw);
2636 u8 value;
2637
2638 if (!auto_load_fail) {
2639 rtlpriv->btcoexist.eeprom_bt_coexist =
2640 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2641 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2642 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2643 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2644 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2645 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2646 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2647 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2648 ((value & 0x20) >> 5);
2649 } else {
2650 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2651 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2652 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2653 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2654 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2655 }
2656
2657 rtl8188ee_bt_var_init(hw);
2658 }
2659
2660 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2661 {
2662 struct rtl_priv *rtlpriv = rtl_priv(hw);
2663
2664 /* 0:Low, 1:High, 2:From Efuse. */
2665 rtlpriv->btcoexist.reg_bt_iso = 2;
2666 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2667 rtlpriv->btcoexist.reg_bt_sco = 3;
2668 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2669 rtlpriv->btcoexist.reg_bt_sco = 0;
2670 }
2671
2672 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2673 {
2674 struct rtl_priv *rtlpriv = rtl_priv(hw);
2675 struct rtl_phy *rtlphy = &rtlpriv->phy;
2676 u8 u1_tmp;
2677
2678 if (rtlpriv->btcoexist.bt_coexistence &&
2679 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2680 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2681 if (rtlpriv->btcoexist.bt_ant_isolation)
2682 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2683
2684 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2685 BIT_OFFSET_LEN_MASK_32(0, 1);
2686 u1_tmp = u1_tmp |
2687 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2688 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2689 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2690 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2691 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2692
2693 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2694 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2695 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2696
2697 /* Config to 1T1R. */
2698 if (rtlphy->rf_type == RF_1T1R) {
2699 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2700 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2701 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2702
2703 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2704 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2705 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2706 }
2707 }
2708 }
2709
2710 void rtl88ee_suspend(struct ieee80211_hw *hw)
2711 {
2712 }
2713
2714 void rtl88ee_resume(struct ieee80211_hw *hw)
2715 {
2716 }
2717
2718 #line 117 "/work/ldvuser/andrianov/work/current--X--drivers/net/wireless/--X--defaultlinux-4.5-rc7--X--races--X--cpachecker/linux-4.5-rc7/csd_deg_dscv/376/dscv_tempdir/dscv/ri/races/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.o.c.prepared" 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../core.h"
28 #include "../pci.h"
29 #include "reg.h"
30 #include "def.h"
31 #include "phy.h"
32 #include "dm.h"
33 #include "hw.h"
34 #include "sw.h"
35 #include "trx.h"
36 #include "led.h"
37 #include "table.h"
38
39 #include <linux/vmalloc.h>
40 #include <linux/module.h>
41
42 static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
43 {
44 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
45
46 /*close ASPM for AMD defaultly */
47 rtlpci->const_amdpci_aspm = 0;
48
49 /* ASPM PS mode.
50 * 0 - Disable ASPM,
51 * 1 - Enable ASPM without Clock Req,
52 * 2 - Enable ASPM with Clock Req,
53 * 3 - Alwyas Enable ASPM with Clock Req,
54 * 4 - Always Enable ASPM without Clock Req.
55 * set defult to RTL8192CE:3 RTL8192E:2
56 */
57 rtlpci->const_pci_aspm = 3;
58
59 /*Setting for PCI-E device */
60 rtlpci->const_devicepci_aspm_setting = 0x03;
61
62 /*Setting for PCI-E bridge */
63 rtlpci->const_hostpci_aspm_setting = 0x02;
64
65 /* In Hw/Sw Radio Off situation.
66 * 0 - Default,
67 * 1 - From ASPM setting without low Mac Pwr,
68 * 2 - From ASPM setting with low Mac Pwr,
69 * 3 - Bus D3
70 * set default to RTL8192CE:0 RTL8192SE:2
71 */
72 rtlpci->const_hwsw_rfoff_d3 = 0;
73
74 /* This setting works for those device with
75 * backdoor ASPM setting such as EPHY setting.
76 * 0 - Not support ASPM,
77 * 1 - Support ASPM,
78 * 2 - According to chipset.
79 */
80 rtlpci->const_support_pciaspm = 1;
81 }
82
83 int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
84 {
85 int err = 0;
86 struct rtl_priv *rtlpriv = rtl_priv(hw);
87 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
88 u8 tid;
89
90 rtl8188ee_bt_reg_init(hw);
91 rtlpriv->dm.dm_initialgain_enable = 1;
92 rtlpriv->dm.dm_flag = 0;
93 rtlpriv->dm.disable_framebursting = 0;
94 rtlpriv->dm.thermalvalue = 0;
95 rtlpci->transmit_config = CFENDFORM | BIT(15);
96
97 /* compatible 5G band 88ce just 2.4G band & smsp */
98 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
99 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
100 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
101
102 rtlpci->receive_config = (RCR_APPFCS |
103 RCR_APP_MIC |
104 RCR_APP_ICV |
105 RCR_APP_PHYST_RXFF |
106 RCR_HTC_LOC_CTRL |
107 RCR_AMF |
108 RCR_ACF |
109 RCR_ADF |
110 RCR_AICV |
111 RCR_ACRC32 |
112 RCR_AB |
113 RCR_AM |
114 RCR_APM |
115 0);
116
117 rtlpci->irq_mask[0] =
118 (u32)(IMR_PSTIMEOUT |
119 IMR_HSISR_IND_ON_INT |
120 IMR_C2HCMD |
121 IMR_HIGHDOK |
122 IMR_MGNTDOK |
123 IMR_BKDOK |
124 IMR_BEDOK |
125 IMR_VIDOK |
126 IMR_VODOK |
127 IMR_RDU |
128 IMR_ROK |
129 0);
130 rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
131 rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
132
133 /* for debug level */
134 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
135 /* for LPS & IPS */
136 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
137 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
138 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
139 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
140 rtlpriv->cfg->mod_params->sw_crypto =
141 rtlpriv->cfg->mod_params->sw_crypto;
142 rtlpriv->cfg->mod_params->disable_watchdog =
143 rtlpriv->cfg->mod_params->disable_watchdog;
144 if (rtlpriv->cfg->mod_params->disable_watchdog)
145 pr_info("watchdog disabled\n");
146 if (!rtlpriv->psc.inactiveps)
147 pr_info("rtl8188ee: Power Save off (module option)\n");
148 if (!rtlpriv->psc.fwctrl_lps)
149 pr_info("rtl8188ee: FW Power Save off (module option)\n");
150 rtlpriv->psc.reg_fwctrl_lps = 3;
151 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
152 /* for ASPM, you can close aspm through
153 * set const_support_pciaspm = 0
154 */
155 rtl88e_init_aspm_vars(hw);
156
157 if (rtlpriv->psc.reg_fwctrl_lps == 1)
158 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
159 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
160 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
161 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
162 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
163
164 /* for firmware buf */
165 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
166 if (!rtlpriv->rtlhal.pfirmware) {
167 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
168 "Can't alloc buffer for fw.\n");
169 return 1;
170 }
171
172 rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
173 rtlpriv->max_fw_size = 0x8000;
174 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
175 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
176 rtlpriv->io.dev, GFP_KERNEL, hw,
177 rtl_fw_cb);
178 if (err) {
179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
180 "Failed to request firmware!\n");
181 return 1;
182 }
183
184 /* for early mode */
185 rtlpriv->rtlhal.earlymode_enable = false;
186 rtlpriv->rtlhal.max_earlymode_num = 10;
187 for (tid = 0; tid < 8; tid++)
188 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
189
190 /*low power */
191 rtlpriv->psc.low_power_enable = false;
192 if (rtlpriv->psc.low_power_enable) {
193 init_timer(&rtlpriv->works.fw_clockoff_timer);
194 setup_timer(&rtlpriv->works.fw_clockoff_timer,
195 rtl88ee_fw_clk_off_timer_callback,
196 (unsigned long)hw);
197 }
198
199 init_timer(&rtlpriv->works.fast_antenna_training_timer);
200 setup_timer(&rtlpriv->works.fast_antenna_training_timer,
201 rtl88e_dm_fast_antenna_training_callback,
202 (unsigned long)hw);
203 return err;
204 }
205
206 void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
207 {
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209
210 if (rtlpriv->rtlhal.pfirmware) {
211 vfree(rtlpriv->rtlhal.pfirmware);
212 rtlpriv->rtlhal.pfirmware = NULL;
213 }
214
215 if (rtlpriv->psc.low_power_enable)
216 del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
217
218 del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
219 }
220
221 /* get bt coexist status */
222 bool rtl88e_get_btc_status(void)
223 {
224 return false;
225 }
226
227 static struct rtl_hal_ops rtl8188ee_hal_ops = {
228 .init_sw_vars = rtl88e_init_sw_vars,
229 .deinit_sw_vars = rtl88e_deinit_sw_vars,
230 .read_eeprom_info = rtl88ee_read_eeprom_info,
231 .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
232 .hw_init = rtl88ee_hw_init,
233 .hw_disable = rtl88ee_card_disable,
234 .hw_suspend = rtl88ee_suspend,
235 .hw_resume = rtl88ee_resume,
236 .enable_interrupt = rtl88ee_enable_interrupt,
237 .disable_interrupt = rtl88ee_disable_interrupt,
238 .set_network_type = rtl88ee_set_network_type,
239 .set_chk_bssid = rtl88ee_set_check_bssid,
240 .set_qos = rtl88ee_set_qos,
241 .set_bcn_reg = rtl88ee_set_beacon_related_registers,
242 .set_bcn_intv = rtl88ee_set_beacon_interval,
243 .update_interrupt_mask = rtl88ee_update_interrupt_mask,
244 .get_hw_reg = rtl88ee_get_hw_reg,
245 .set_hw_reg = rtl88ee_set_hw_reg,
246 .update_rate_tbl = rtl88ee_update_hal_rate_tbl,
247 .fill_tx_desc = rtl88ee_tx_fill_desc,
248 .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
249 .query_rx_desc = rtl88ee_rx_query_desc,
250 .set_channel_access = rtl88ee_update_channel_access_setting,
251 .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
252 .set_bw_mode = rtl88e_phy_set_bw_mode,
253 .switch_channel = rtl88e_phy_sw_chnl,
254 .dm_watchdog = rtl88e_dm_watchdog,
255 .scan_operation_backup = rtl88e_phy_scan_operation_backup,
256 .set_rf_power_state = rtl88e_phy_set_rf_power_state,
257 .led_control = rtl88ee_led_control,
258 .set_desc = rtl88ee_set_desc,
259 .get_desc = rtl88ee_get_desc,
260 .is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
261 .tx_polling = rtl88ee_tx_polling,
262 .enable_hw_sec = rtl88ee_enable_hw_security_config,
263 .set_key = rtl88ee_set_key,
264 .init_sw_leds = rtl88ee_init_sw_leds,
265 .get_bbreg = rtl88e_phy_query_bb_reg,
266 .set_bbreg = rtl88e_phy_set_bb_reg,
267 .get_rfreg = rtl88e_phy_query_rf_reg,
268 .set_rfreg = rtl88e_phy_set_rf_reg,
269 .get_btc_status = rtl88e_get_btc_status,
270 .rx_command_packet = rtl88ee_rx_command_packet,
271
272 };
273
274 static struct rtl_mod_params rtl88ee_mod_params = {
275 .sw_crypto = false,
276 .inactiveps = false,
277 .swctrl_lps = false,
278 .fwctrl_lps = false,
279 .msi_support = true,
280 .debug = DBG_EMERG,
281 };
282
283 static struct rtl_hal_cfg rtl88ee_hal_cfg = {
284 .bar_id = 2,
285 .write_readback = true,
286 .name = "rtl88e_pci",
287 .fw_name = "rtlwifi/rtl8188efw.bin",
288 .ops = &rtl8188ee_hal_ops,
289 .mod_params = &rtl88ee_mod_params,
290
291 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
292 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
293 .maps[SYS_CLK] = REG_SYS_CLKR,
294 .maps[MAC_RCR_AM] = AM,
295 .maps[MAC_RCR_AB] = AB,
296 .maps[MAC_RCR_ACRC32] = ACRC32,
297 .maps[MAC_RCR_ACF] = ACF,
298 .maps[MAC_RCR_AAP] = AAP,
299 .maps[MAC_HIMR] = REG_HIMR,
300 .maps[MAC_HIMRE] = REG_HIMRE,
301 .maps[MAC_HSISR] = REG_HSISR,
302
303 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
304
305 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
306 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
307 .maps[EFUSE_CLK] = 0,
308 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
309 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
310 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
311 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
312 .maps[EFUSE_ANA8M] = ANA8M,
313 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
314 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
315 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
316 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
317
318 .maps[RWCAM] = REG_CAMCMD,
319 .maps[WCAMI] = REG_CAMWRITE,
320 .maps[RCAMO] = REG_CAMREAD,
321 .maps[CAMDBG] = REG_CAMDBG,
322 .maps[SECR] = REG_SECCFG,
323 .maps[SEC_CAM_NONE] = CAM_NONE,
324 .maps[SEC_CAM_WEP40] = CAM_WEP40,
325 .maps[SEC_CAM_TKIP] = CAM_TKIP,
326 .maps[SEC_CAM_AES] = CAM_AES,
327 .maps[SEC_CAM_WEP104] = CAM_WEP104,
328
329 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
330 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
331 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
332 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
333 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
334 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
335 /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
336 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
337 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
338 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
339 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
340 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
341 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
342 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
343 /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
344 /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
345
346 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
347 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
348 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
349 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
350 .maps[RTL_IMR_RDU] = IMR_RDU,
351 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
352 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
353 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
354 .maps[RTL_IMR_TBDER] = IMR_TBDER,
355 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
356 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
357 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
358 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
359 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
360 .maps[RTL_IMR_VODOK] = IMR_VODOK,
361 .maps[RTL_IMR_ROK] = IMR_ROK,
362 .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
363 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
364
365 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
366 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
367 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
368 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
369 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
370 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
371 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
372 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
373 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
374 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
375 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
376 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
377
378 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
379 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
380 };
381
382 static struct pci_device_id rtl88ee_pci_ids[] = {
383 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
384 {},
385 };
386
387 MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
388
389 MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>");
390 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
391 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
392 MODULE_LICENSE("GPL");
393 MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
394 MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
395
396 module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
397 module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
398 module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
399 module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
400 module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
401 module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
402 module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
403 bool, 0444);
404 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
405 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
406 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
407 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
408 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
409 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
410 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
411
412 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
413
414 static struct pci_driver rtl88ee_driver = {
415 .name = KBUILD_MODNAME,
416 .id_table = rtl88ee_pci_ids,
417 .probe = rtl_pci_probe,
418 .remove = rtl_pci_disconnect,
419 .driver.pm = &rtlwifi_pm_ops,
420 };
421
422 module_pci_driver(rtl88ee_driver); 1
2 #include <linux/kernel.h>
3 #include <linux/mutex.h>
4 #include <linux/spinlock.h>
5 #include <linux/errno.h>
6 #include <verifier/rcv.h>
7 #include <linux/list.h>
8
9 /* mutexes */
10 extern int mutex_lock_interruptible(struct mutex *lock);
11 extern int mutex_lock_killable(struct mutex *lock);
12 extern void mutex_lock(struct mutex *lock);
13
14 /* mutex model functions */
15 extern void ldv_mutex_lock(struct mutex *lock, char *sign);
16 extern int ldv_mutex_is_locked(struct mutex *lock, char *sign);
17 extern void ldv_mutex_unlock(struct mutex *lock, char *sign);
18
19
20 /* Spin locks */
21 extern void __ldv_spin_lock(spinlock_t *lock);
22 extern void __ldv_spin_unlock(spinlock_t *lock);
23 extern int __ldv_spin_trylock(spinlock_t *lock);
24 extern void __ldv_spin_unlock_wait(spinlock_t *lock);
25 extern void __ldv_spin_can_lock(spinlock_t *lock);
26 extern int __ldv_atomic_dec_and_lock(spinlock_t *lock);
27
28 /* spin model functions */
29 extern void ldv_spin_lock(spinlock_t *lock, char *sign);
30 extern void ldv_spin_unlock(spinlock_t *lock, char *sign);
31 extern int ldv_spin_is_locked(spinlock_t *lock, char *sign);
32
33 /* Support for list binder functions */
34 static inline struct list_head *ldv_list_get_first(struct list_head *head) {
35 return head->next;
36 }
37
38 static inline int ldv_list_is_stop(struct list_head *pos, struct list_head *head) {
39 return pos==head;
40 }
41
42 static inline struct list_head *ldv_list_get_next(struct list_head *pos) {
43 return pos->next;
44 }
45
46 #include <linux/mutex.h>
47 #include <linux/slab.h>
48 #include <verifier/rcv.h>
49 #include <linux/timer.h>
50 #include <linux/gfp.h>
51 struct timer_list * ldv_timer_list_4;
52 int ldv_timer_1_3;
53 int pci_counter;
54 struct timer_list * ldv_timer_list_2_0;
55 struct timer_list * ldv_timer_list_3;
56 int ldv_timer_2_1;
57 int ldv_state_variable_0;
58 int ldv_state_variable_5;
59 int ldv_timer_state_3 = 0;
60 int ldv_timer_2_2;
61 int ldv_timer_2_3;
62 int ldv_timer_1_0;
63 struct pci_dev *rtl88ee_driver_group1;
64 int ldv_timer_state_4 = 0;
65 int ref_cnt;
66 int ldv_state_variable_1;
67 int ldv_state_variable_7;
68 struct timer_list * ldv_timer_list_1_3;
69 struct sk_buff *rtl8188ee_hal_ops_group0;
70 struct timer_list * ldv_timer_list_1_1;
71 struct timer_list * ldv_timer_list_2_1;
72 struct ieee80211_hw *rtl8188ee_hal_ops_group1;
73 struct timer_list * ldv_timer_list_1_0;
74 int ldv_state_variable_6;
75 int ldv_timer_1_2;
76 int ldv_timer_2_0;
77 struct ieee80211_sta *rtl8188ee_hal_ops_group2;
78 int ldv_timer_1_1;
79 int ldv_state_variable_2;
80 struct timer_list * ldv_timer_list_1_2;
81 int LDV_IN_INTERRUPT = 1;
82 int __VERIFIER_nondet_int(void);
83 struct device *rtlwifi_pm_ops_group1;
84 struct mutex fs_mutex;
85 int ldv_state_variable_3;
86 struct timer_list * ldv_timer_list_2_3;
87 struct mutex ar_mutex;
88 struct timer_list * ldv_timer_list_2_2;
89 int ldv_state_variable_4;
90 void ldv_pci_driver_5(void);
91 void choose_timer_2(void);
92 int reg_timer_2(struct timer_list * timer, void (*function)(unsigned long), unsigned long data);
93 void activate_pending_timer_2(struct timer_list * timer, unsigned long data, int pending_flag);
94 void choose_timer_3(struct timer_list * timer);
95 void activate_pending_timer_4(struct timer_list * timer, unsigned long data, int pending_flag);
96 void activate_pending_timer_1(struct timer_list * timer, unsigned long data, int pending_flag);
97 void choose_timer_4(struct timer_list * timer);
98 void timer_init_2(void);
99 void timer_init_1(void);
100 void disable_suitable_timer_3(struct timer_list * timer);
101 void disable_suitable_timer_4(struct timer_list * timer);
102 void ldv_dev_pm_ops_6(void);
103 int reg_timer_1(struct timer_list * timer, void (*function)(unsigned long), unsigned long data);
104 int reg_timer_4(struct timer_list * timer);
105 void disable_suitable_timer_2(struct timer_list * timer);
106 void disable_suitable_timer_1(struct timer_list * timer);
107 void activate_suitable_timer_1(struct timer_list * timer, unsigned long data);
108 void activate_pending_timer_3(struct timer_list * timer, unsigned long data, int pending_flag);
109 int evil_hack_fs_lock(void);
110 int __VERIFIER_nondet_int(void);
111 int reg_timer_3(struct timer_list * timer);
112 void ldv_initialyze_rtl_hal_ops_7(void);
113 void choose_timer_1(void);
114 void ldv_timer_1(int state, struct timer_list * timer);
115 void activate_suitable_timer_2(struct timer_list * timer, unsigned long data);
116 int evil_hack_ar_lock(void);
117 void ldv_timer_2(int state, struct timer_list * timer);
118 #line 1 "/work/ldvuser/andrianov/work/current--X--drivers/net/wireless/--X--defaultlinux-4.5-rc7--X--races--X--cpachecker/linux-4.5-rc7/csd_deg_dscv/376/dscv_tempdir/dscv/ri/races/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c"
119 /******************************************************************************
120 *
121 * Copyright(c) 2009-2013 Realtek Corporation.
122 *
123 * This program is free software; you can redistribute it and/or modify it
124 * under the terms of version 2 of the GNU General Public License as
125 * published by the Free Software Foundation.
126 *
127 * This program is distributed in the hope that it will be useful, but WITHOUT
128 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
129 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
130 * more details.
131 *
132 * The full GNU General Public License is included in this distribution in the
133 * file called LICENSE.
134 *
135 * Contact Information:
136 * wlanfae <wlanfae@realtek.com>
137 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
138 * Hsinchu 300, Taiwan.
139 *
140 * Larry Finger <Larry.Finger@lwfinger.net>
141 *
142 *****************************************************************************/
143
144 #include "../wifi.h"
145 #include "../core.h"
146 #include "../pci.h"
147 #include "reg.h"
148 #include "def.h"
149 #include "phy.h"
150 #include "dm.h"
151 #include "hw.h"
152 #include "sw.h"
153 #include "trx.h"
154 #include "led.h"
155 #include "table.h"
156
157 #include <linux/vmalloc.h>
158 #include <linux/module.h>
159
160 static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw)
161 {
162 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
163
164 /*close ASPM for AMD defaultly */
165 rtlpci->const_amdpci_aspm = 0;
166
167 /* ASPM PS mode.
168 * 0 - Disable ASPM,
169 * 1 - Enable ASPM without Clock Req,
170 * 2 - Enable ASPM with Clock Req,
171 * 3 - Alwyas Enable ASPM with Clock Req,
172 * 4 - Always Enable ASPM without Clock Req.
173 * set defult to RTL8192CE:3 RTL8192E:2
174 */
175 rtlpci->const_pci_aspm = 3;
176
177 /*Setting for PCI-E device */
178 rtlpci->const_devicepci_aspm_setting = 0x03;
179
180 /*Setting for PCI-E bridge */
181 rtlpci->const_hostpci_aspm_setting = 0x02;
182
183 /* In Hw/Sw Radio Off situation.
184 * 0 - Default,
185 * 1 - From ASPM setting without low Mac Pwr,
186 * 2 - From ASPM setting with low Mac Pwr,
187 * 3 - Bus D3
188 * set default to RTL8192CE:0 RTL8192SE:2
189 */
190 rtlpci->const_hwsw_rfoff_d3 = 0;
191
192 /* This setting works for those device with
193 * backdoor ASPM setting such as EPHY setting.
194 * 0 - Not support ASPM,
195 * 1 - Support ASPM,
196 * 2 - According to chipset.
197 */
198 rtlpci->const_support_pciaspm = 1;
199 }
200
201 int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
202 {
203 int err = 0;
204 struct rtl_priv *rtlpriv = rtl_priv(hw);
205 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
206 u8 tid;
207
208 rtl8188ee_bt_reg_init(hw);
209 rtlpriv->dm.dm_initialgain_enable = 1;
210 rtlpriv->dm.dm_flag = 0;
211 rtlpriv->dm.disable_framebursting = 0;
212 rtlpriv->dm.thermalvalue = 0;
213 rtlpci->transmit_config = CFENDFORM | BIT(15);
214
215 /* compatible 5G band 88ce just 2.4G band & smsp */
216 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
217 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
218 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
219
220 rtlpci->receive_config = (RCR_APPFCS |
221 RCR_APP_MIC |
222 RCR_APP_ICV |
223 RCR_APP_PHYST_RXFF |
224 RCR_HTC_LOC_CTRL |
225 RCR_AMF |
226 RCR_ACF |
227 RCR_ADF |
228 RCR_AICV |
229 RCR_ACRC32 |
230 RCR_AB |
231 RCR_AM |
232 RCR_APM |
233 0);
234
235 rtlpci->irq_mask[0] =
236 (u32)(IMR_PSTIMEOUT |
237 IMR_HSISR_IND_ON_INT |
238 IMR_C2HCMD |
239 IMR_HIGHDOK |
240 IMR_MGNTDOK |
241 IMR_BKDOK |
242 IMR_BEDOK |
243 IMR_VIDOK |
244 IMR_VODOK |
245 IMR_RDU |
246 IMR_ROK |
247 0);
248 rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
249 rtlpci->sys_irq_mask = (u32) (HSIMR_PDN_INT_EN | HSIMR_RON_INT_EN);
250
251 /* for debug level */
252 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
253 /* for LPS & IPS */
254 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
255 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
256 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
257 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
258 rtlpriv->cfg->mod_params->sw_crypto =
259 rtlpriv->cfg->mod_params->sw_crypto;
260 rtlpriv->cfg->mod_params->disable_watchdog =
261 rtlpriv->cfg->mod_params->disable_watchdog;
262 if (rtlpriv->cfg->mod_params->disable_watchdog)
263 pr_info("watchdog disabled\n");
264 if (!rtlpriv->psc.inactiveps)
265 pr_info("rtl8188ee: Power Save off (module option)\n");
266 if (!rtlpriv->psc.fwctrl_lps)
267 pr_info("rtl8188ee: FW Power Save off (module option)\n");
268 rtlpriv->psc.reg_fwctrl_lps = 3;
269 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
270 /* for ASPM, you can close aspm through
271 * set const_support_pciaspm = 0
272 */
273 rtl88e_init_aspm_vars(hw);
274
275 if (rtlpriv->psc.reg_fwctrl_lps == 1)
276 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
277 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
278 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
279 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
280 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
281
282 /* for firmware buf */
283 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
284 if (!rtlpriv->rtlhal.pfirmware) {
285 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
286 "Can't alloc buffer for fw.\n");
287 return 1;
288 }
289
290 rtlpriv->cfg->fw_name = "rtlwifi/rtl8188efw.bin";
291 rtlpriv->max_fw_size = 0x8000;
292 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
293 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
294 rtlpriv->io.dev, GFP_KERNEL, hw,
295 rtl_fw_cb);
296 if (err) {
297 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
298 "Failed to request firmware!\n");
299 return 1;
300 }
301
302 /* for early mode */
303 rtlpriv->rtlhal.earlymode_enable = false;
304 rtlpriv->rtlhal.max_earlymode_num = 10;
305 for (tid = 0; tid < 8; tid++)
306 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
307
308 /*low power */
309 rtlpriv->psc.low_power_enable = false;
310 if (rtlpriv->psc.low_power_enable) {
311 init_timer(&rtlpriv->works.fw_clockoff_timer);
312 setup_timer(&rtlpriv->works.fw_clockoff_timer,
313 rtl88ee_fw_clk_off_timer_callback,
314 (unsigned long)hw);
315 }
316
317 init_timer(&rtlpriv->works.fast_antenna_training_timer);
318 setup_timer(&rtlpriv->works.fast_antenna_training_timer,
319 rtl88e_dm_fast_antenna_training_callback,
320 (unsigned long)hw);
321 return err;
322 }
323
324 void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
325 {
326 struct rtl_priv *rtlpriv = rtl_priv(hw);
327
328 if (rtlpriv->rtlhal.pfirmware) {
329 vfree(rtlpriv->rtlhal.pfirmware);
330 rtlpriv->rtlhal.pfirmware = NULL;
331 }
332
333 if (rtlpriv->psc.low_power_enable)
334 del_timer_sync(&rtlpriv->works.fw_clockoff_timer);
335
336 del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
337 }
338
339 /* get bt coexist status */
340 bool rtl88e_get_btc_status(void)
341 {
342 return false;
343 }
344
345 static struct rtl_hal_ops rtl8188ee_hal_ops = {
346 .init_sw_vars = rtl88e_init_sw_vars,
347 .deinit_sw_vars = rtl88e_deinit_sw_vars,
348 .read_eeprom_info = rtl88ee_read_eeprom_info,
349 .interrupt_recognized = rtl88ee_interrupt_recognized,/*need check*/
350 .hw_init = rtl88ee_hw_init,
351 .hw_disable = rtl88ee_card_disable,
352 .hw_suspend = rtl88ee_suspend,
353 .hw_resume = rtl88ee_resume,
354 .enable_interrupt = rtl88ee_enable_interrupt,
355 .disable_interrupt = rtl88ee_disable_interrupt,
356 .set_network_type = rtl88ee_set_network_type,
357 .set_chk_bssid = rtl88ee_set_check_bssid,
358 .set_qos = rtl88ee_set_qos,
359 .set_bcn_reg = rtl88ee_set_beacon_related_registers,
360 .set_bcn_intv = rtl88ee_set_beacon_interval,
361 .update_interrupt_mask = rtl88ee_update_interrupt_mask,
362 .get_hw_reg = rtl88ee_get_hw_reg,
363 .set_hw_reg = rtl88ee_set_hw_reg,
364 .update_rate_tbl = rtl88ee_update_hal_rate_tbl,
365 .fill_tx_desc = rtl88ee_tx_fill_desc,
366 .fill_tx_cmddesc = rtl88ee_tx_fill_cmddesc,
367 .query_rx_desc = rtl88ee_rx_query_desc,
368 .set_channel_access = rtl88ee_update_channel_access_setting,
369 .radio_onoff_checking = rtl88ee_gpio_radio_on_off_checking,
370 .set_bw_mode = rtl88e_phy_set_bw_mode,
371 .switch_channel = rtl88e_phy_sw_chnl,
372 .dm_watchdog = rtl88e_dm_watchdog,
373 .scan_operation_backup = rtl88e_phy_scan_operation_backup,
374 .set_rf_power_state = rtl88e_phy_set_rf_power_state,
375 .led_control = rtl88ee_led_control,
376 .set_desc = rtl88ee_set_desc,
377 .get_desc = rtl88ee_get_desc,
378 .is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
379 .tx_polling = rtl88ee_tx_polling,
380 .enable_hw_sec = rtl88ee_enable_hw_security_config,
381 .set_key = rtl88ee_set_key,
382 .init_sw_leds = rtl88ee_init_sw_leds,
383 .get_bbreg = rtl88e_phy_query_bb_reg,
384 .set_bbreg = rtl88e_phy_set_bb_reg,
385 .get_rfreg = rtl88e_phy_query_rf_reg,
386 .set_rfreg = rtl88e_phy_set_rf_reg,
387 .get_btc_status = rtl88e_get_btc_status,
388 .rx_command_packet = rtl88ee_rx_command_packet,
389
390 };
391
392 static struct rtl_mod_params rtl88ee_mod_params = {
393 .sw_crypto = false,
394 .inactiveps = false,
395 .swctrl_lps = false,
396 .fwctrl_lps = false,
397 .msi_support = true,
398 .debug = DBG_EMERG,
399 };
400
401 static struct rtl_hal_cfg rtl88ee_hal_cfg = {
402 .bar_id = 2,
403 .write_readback = true,
404 .name = "rtl88e_pci",
405 .fw_name = "rtlwifi/rtl8188efw.bin",
406 .ops = &rtl8188ee_hal_ops,
407 .mod_params = &rtl88ee_mod_params,
408
409 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
410 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
411 .maps[SYS_CLK] = REG_SYS_CLKR,
412 .maps[MAC_RCR_AM] = AM,
413 .maps[MAC_RCR_AB] = AB,
414 .maps[MAC_RCR_ACRC32] = ACRC32,
415 .maps[MAC_RCR_ACF] = ACF,
416 .maps[MAC_RCR_AAP] = AAP,
417 .maps[MAC_HIMR] = REG_HIMR,
418 .maps[MAC_HIMRE] = REG_HIMRE,
419 .maps[MAC_HSISR] = REG_HSISR,
420
421 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
422
423 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
424 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
425 .maps[EFUSE_CLK] = 0,
426 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
427 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
428 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
429 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
430 .maps[EFUSE_ANA8M] = ANA8M,
431 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
432 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
433 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
434 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
435
436 .maps[RWCAM] = REG_CAMCMD,
437 .maps[WCAMI] = REG_CAMWRITE,
438 .maps[RCAMO] = REG_CAMREAD,
439 .maps[CAMDBG] = REG_CAMDBG,
440 .maps[SECR] = REG_SECCFG,
441 .maps[SEC_CAM_NONE] = CAM_NONE,
442 .maps[SEC_CAM_WEP40] = CAM_WEP40,
443 .maps[SEC_CAM_TKIP] = CAM_TKIP,
444 .maps[SEC_CAM_AES] = CAM_AES,
445 .maps[SEC_CAM_WEP104] = CAM_WEP104,
446
447 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
448 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
449 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
450 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
451 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
452 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
453 /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
454 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
455 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
456 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
457 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
458 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
459 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
460 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
461 /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
462 /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
463
464 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
465 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
466 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
467 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
468 .maps[RTL_IMR_RDU] = IMR_RDU,
469 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
470 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
471 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
472 .maps[RTL_IMR_TBDER] = IMR_TBDER,
473 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
474 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
475 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
476 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
477 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
478 .maps[RTL_IMR_VODOK] = IMR_VODOK,
479 .maps[RTL_IMR_ROK] = IMR_ROK,
480 .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
481 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
482
483 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
484 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
485 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
486 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
487 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
488 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
489 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
490 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
491 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
492 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
493 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
494 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
495
496 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
497 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
498 };
499
500 static struct pci_device_id rtl88ee_pci_ids[] = {
501 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
502 {},
503 };
504
505 MODULE_DEVICE_TABLE(pci, rtl88ee_pci_ids);
506
507 MODULE_AUTHOR("zhiyuan_yang <zhiyuan_yang@realsil.com.cn>");
508 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
509 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
510 MODULE_LICENSE("GPL");
511 MODULE_DESCRIPTION("Realtek 8188E 802.11n PCI wireless");
512 MODULE_FIRMWARE("rtlwifi/rtl8188efw.bin");
513
514 module_param_named(swenc, rtl88ee_mod_params.sw_crypto, bool, 0444);
515 module_param_named(debug, rtl88ee_mod_params.debug, int, 0444);
516 module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
517 module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
518 module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
519 module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
520 module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
521 bool, 0444);
522 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
523 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
524 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
525 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
526 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
527 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
528 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
529
530 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
531
532 static struct pci_driver rtl88ee_driver = {
533 .name = KBUILD_MODNAME,
534 .id_table = rtl88ee_pci_ids,
535 .probe = rtl_pci_probe,
536 .remove = rtl_pci_disconnect,
537 .driver.pm = &rtlwifi_pm_ops,
538 };
539
540 module_pci_driver(rtl88ee_driver);
541
542 #line 118 "/work/ldvuser/andrianov/work/current--X--drivers/net/wireless/--X--defaultlinux-4.5-rc7--X--races--X--cpachecker/linux-4.5-rc7/csd_deg_dscv/376/dscv_tempdir/dscv/ri/races/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.o.c.prepared"
543
544 int ldv_retval_20;
545 int ldv_retval_18;
546 int ldv_suspend_noirq_6(void);
547 int ldv_retval_2;
548 int ldv_retval_5;
549 int ldv_retval_0;
550 int ldv_retval_11;
551 int ldv_retval_1;
552 int ldv_thaw_noirq_6(void);
553 int ldv_retval_15;
554 int ldv_shutdown_5(void);
555 int ldv_retval_16;
556 int ldv_restore_early_6(void);
557 int ldv_freeze_late_6(void);
558 int ldv_prepare_6(void);
559 int ldv_restore_noirq_6(void);
560 void ldv_check_final_state(void);
561 int ldv_probe_7(void);
562 int ldv_retval_8;
563 int ldv_release_7(void);
564 int ldv_retval_7;
565 int ldv_retval_19;
566 int ldv_freeze_noirq_6(void);
567 int ldv_retval_14;
568 int ldv_poweroff_late_6(void);
569 int ldv_retval_17;
570 int ldv_retval_12;
571 void ldv_initialize(void);
572 int ldv_retval_6;
573 int ldv_complete_6(void);
574 int ldv_poweroff_noirq_6(void);
575 int ldv_thaw_early_6(void);
576 int ldv_retval_13;
577 int ldv_retval_9;
578 int ldv_retval_10;
579 int ldv_resume_early_6(void);
580 int ldv_suspend_late_6(void);
581 int ldv_resume_noirq_6(void);
582 int ldv_retval_4;
583 int ldv_retval_3;
584
585
586 void ldv_pci_driver_5(void){
587 rtl88ee_driver_group1 = ldv_undef_ptr();
588 }
589
590
591 void choose_timer_2(void){
592 switch(__VERIFIER_nondet_int()){
593 case 0: {
594 if(ldv_timer_2_0 == 1){
595 ldv_timer_2_0 = 2;
596 ldv_timer_2(ldv_timer_2_0, ldv_timer_list_2_0);
597 }
598 }
599 break;
600 case 1: {
601 if(ldv_timer_2_1 == 1){
602 ldv_timer_2_1 = 2;
603 ldv_timer_2(ldv_timer_2_1, ldv_timer_list_2_1);
604 }
605 }
606 break;
607 case 2: {
608 if(ldv_timer_2_2 == 1){
609 ldv_timer_2_2 = 2;
610 ldv_timer_2(ldv_timer_2_2, ldv_timer_list_2_2);
611 }
612 }
613 break;
614 case 3: {
615 if(ldv_timer_2_3 == 1){
616 ldv_timer_2_3 = 2;
617 ldv_timer_2(ldv_timer_2_3, ldv_timer_list_2_3);
618 }
619 }
620 break;
621 default: ldv_assume(0);
622 }
623 return;
624 }
625
626
627 int reg_timer_2(struct timer_list * timer, void (*function)(unsigned long), unsigned long data){
628 if(function == rtl88e_dm_fast_antenna_training_callback){
629 activate_suitable_timer_2(timer, data);
630 }
631 }
632
633
634 void activate_pending_timer_2(struct timer_list * timer, unsigned long data, int pending_flag){
635 if(ldv_timer_list_2_0 == timer){
636 if(ldv_timer_2_0 == 2 || pending_flag){
637 ldv_timer_list_2_0 = timer;
638 ldv_timer_list_2_0->data = data;
639 ldv_timer_2_0 = 1;
640 }
641 return;
642 }
643
644 if(ldv_timer_list_2_1 == timer){
645 if(ldv_timer_2_1 == 2 || pending_flag){
646 ldv_timer_list_2_1 = timer;
647 ldv_timer_list_2_1->data = data;
648 ldv_timer_2_1 = 1;
649 }
650 return;
651 }
652
653 if(ldv_timer_list_2_2 == timer){
654 if(ldv_timer_2_2 == 2 || pending_flag){
655 ldv_timer_list_2_2 = timer;
656 ldv_timer_list_2_2->data = data;
657 ldv_timer_2_2= 1;
658 }
659 return;
660 }
661
662 if(ldv_timer_list_2_3 == timer){
663 if(ldv_timer_2_3 == 2 || pending_flag){
664 ldv_timer_list_2_3 = timer;
665 ldv_timer_list_2_3->data = data;
666 ldv_timer_2_3 = 1;
667 }
668 return;
669 }
670 activate_suitable_timer_2(timer, data);
671 }
672
673
674 void choose_timer_3(struct timer_list * timer){
675 LDV_IN_INTERRUPT=2;
676 (timer->function)(timer->data);
677 LDV_IN_INTERRUPT=1;
678 ldv_timer_state_3 = 2;
679 }
680
681
682 void activate_pending_timer_4(struct timer_list * timer, unsigned long data, int pending_flag){ if(ldv_timer_list_4 == timer){
683 if(ldv_timer_state_4 == 2 || pending_flag){
684 ldv_timer_list_4 = timer;
685 ldv_timer_list_4->data = data;
686 ldv_timer_state_4 = 1;
687 }
688 return;
689 }
690 reg_timer_4(timer);
691 ldv_timer_list_4->data = data;
692 }
693
694
695 void activate_pending_timer_1(struct timer_list * timer, unsigned long data, int pending_flag){
696 if(ldv_timer_list_1_0 == timer){
697 if(ldv_timer_1_0 == 2 || pending_flag){
698 ldv_timer_list_1_0 = timer;
699 ldv_timer_list_1_0->data = data;
700 ldv_timer_1_0 = 1;
701 }
702 return;
703 }
704
705 if(ldv_timer_list_1_1 == timer){
706 if(ldv_timer_1_1 == 2 || pending_flag){
707 ldv_timer_list_1_1 = timer;
708 ldv_timer_list_1_1->data = data;
709 ldv_timer_1_1 = 1;
710 }
711 return;
712 }
713
714 if(ldv_timer_list_1_2 == timer){
715 if(ldv_timer_1_2 == 2 || pending_flag){
716 ldv_timer_list_1_2 = timer;
717 ldv_timer_list_1_2->data = data;
718 ldv_timer_1_2= 1;
719 }
720 return;
721 }
722
723 if(ldv_timer_list_1_3 == timer){
724 if(ldv_timer_1_3 == 2 || pending_flag){
725 ldv_timer_list_1_3 = timer;
726 ldv_timer_list_1_3->data = data;
727 ldv_timer_1_3 = 1;
728 }
729 return;
730 }
731 activate_suitable_timer_1(timer, data);
732 }
733
734
735 void choose_timer_4(struct timer_list * timer){
736 LDV_IN_INTERRUPT=2;
737 (timer->function)(timer->data);
738 LDV_IN_INTERRUPT=1;
739 ldv_timer_state_4 = 2;
740 }
741
742
743 void timer_init_2(void){
744 ldv_timer_2_0 = 0;
745 ldv_timer_2_1 = 0;
746 ldv_timer_2_2 = 0;
747 ldv_timer_2_3 = 0;
748 }
749
750
751 void timer_init_1(void){
752 ldv_timer_1_0 = 0;
753 ldv_timer_1_1 = 0;
754 ldv_timer_1_2 = 0;
755 ldv_timer_1_3 = 0;
756 }
757
758
759 void disable_suitable_timer_3(struct timer_list * timer){
760 if(timer == ldv_timer_list_3){
761 ldv_timer_state_3 = 0;
762 return;
763 }
764 }
765
766
767 void disable_suitable_timer_4(struct timer_list * timer){
768 if(timer == ldv_timer_list_4){
769 ldv_timer_state_4 = 0;
770 return;
771 }
772 }
773
774
775 void ldv_dev_pm_ops_6(void){
776 rtlwifi_pm_ops_group1 = ldv_undef_ptr();
777 }
778
779
780 int reg_timer_1(struct timer_list * timer, void (*function)(unsigned long), unsigned long data){
781 if(function == rtl88ee_fw_clk_off_timer_callback){
782 activate_suitable_timer_1(timer, data);
783 }
784 }
785
786
787 int reg_timer_4(struct timer_list * timer){
788 ldv_timer_list_4 = timer;
789 ldv_timer_state_4 = 1;
790 }
791
792
793 void disable_suitable_timer_2(struct timer_list * timer){
794 if(ldv_timer_2_0 != 0 && timer == ldv_timer_list_2_0){
795 ldv_timer_2_0 = 0;
796 return;
797 }
798 if(ldv_timer_2_1 != 0 && timer == ldv_timer_list_2_1){
799 ldv_timer_2_1 = 0;
800 return;
801 }
802 if(ldv_timer_2_2 != 0 && timer == ldv_timer_list_2_2){
803 ldv_timer_2_2 = 0;
804 return;
805 }
806 if(ldv_timer_2_3 != 0 && timer == ldv_timer_list_2_3){
807 ldv_timer_2_3 = 0;
808 return;
809 }
810 return;
811 }
812
813
814 void disable_suitable_timer_1(struct timer_list * timer){
815 if(ldv_timer_1_0 != 0 && timer == ldv_timer_list_1_0){
816 ldv_timer_1_0 = 0;
817 return;
818 }
819 if(ldv_timer_1_1 != 0 && timer == ldv_timer_list_1_1){
820 ldv_timer_1_1 = 0;
821 return;
822 }
823 if(ldv_timer_1_2 != 0 && timer == ldv_timer_list_1_2){
824 ldv_timer_1_2 = 0;
825 return;
826 }
827 if(ldv_timer_1_3 != 0 && timer == ldv_timer_list_1_3){
828 ldv_timer_1_3 = 0;
829 return;
830 }
831 return;
832 }
833
834
835 void activate_suitable_timer_1(struct timer_list * timer, unsigned long data){
836 if(ldv_timer_1_0 == 0 || ldv_timer_1_0 == 2){
837 ldv_timer_list_1_0 = timer;
838 ldv_timer_list_1_0->data = data;
839 ldv_timer_1_0 = 1;
840 return;
841 }
842 if(ldv_timer_1_1 == 0 || ldv_timer_1_1 == 2){
843 ldv_timer_list_1_1 = timer;
844 ldv_timer_list_1_1->data = data;
845 ldv_timer_1_1 = 1;
846 return;
847 }
848 if(ldv_timer_1_2 == 0 || ldv_timer_1_2 == 2){
849 ldv_timer_list_1_2 = timer;
850 ldv_timer_list_1_2->data = data;
851 ldv_timer_1_2 = 1;
852 return;
853 }
854 if(ldv_timer_1_3 == 0 || ldv_timer_1_3 == 2){
855 ldv_timer_list_1_3 = timer;
856 ldv_timer_list_1_3->data = data;
857 ldv_timer_1_3 = 1;
858 return;
859 }
860 return;
861 }
862
863
864 void activate_pending_timer_3(struct timer_list * timer, unsigned long data, int pending_flag){ if(ldv_timer_list_3 == timer){
865 if(ldv_timer_state_3 == 2 || pending_flag){
866 ldv_timer_list_3 = timer;
867 ldv_timer_list_3->data = data;
868 ldv_timer_state_3 = 1;
869 }
870 return;
871 }
872 reg_timer_3(timer);
873 ldv_timer_list_3->data = data;
874 }
875
876
877 int evil_hack_fs_lock(void){
878 mutex_lock(&fs_mutex);
879 return 1;
880 }
881
882 int __VERIFIER_nondet_int(void);
883
884 int reg_timer_3(struct timer_list * timer){
885 ldv_timer_list_3 = timer;
886 ldv_timer_state_3 = 1;
887 }
888
889
890 void ldv_initialyze_rtl_hal_ops_7(void){
891 rtl8188ee_hal_ops_group0 = ldv_undef_ptr();
892 rtl8188ee_hal_ops_group1 = ldv_undef_ptr();
893 rtl8188ee_hal_ops_group2 = ldv_undef_ptr();
894 }
895
896 void choose_timer_1(void){
897 switch(__VERIFIER_nondet_int()){
898 case 0: {
899 if(ldv_timer_1_0 == 1){
900 ldv_timer_1_0 = 2;
901 ldv_timer_1(ldv_timer_1_0, ldv_timer_list_1_0);
902 }
903 }
904 break;
905 case 1: {
906 if(ldv_timer_1_1 == 1){
907 ldv_timer_1_1 = 2;
908 ldv_timer_1(ldv_timer_1_1, ldv_timer_list_1_1);
909 }
910 }
911 break;
912 case 2: {
913 if(ldv_timer_1_2 == 1){
914 ldv_timer_1_2 = 2;
915 ldv_timer_1(ldv_timer_1_2, ldv_timer_list_1_2);
916 }
917 }
918 break;
919 case 3: {
920 if(ldv_timer_1_3 == 1){
921 ldv_timer_1_3 = 2;
922 ldv_timer_1(ldv_timer_1_3, ldv_timer_list_1_3);
923 }
924 }
925 break;
926 default: ldv_assume(0);
927 }
928 return;
929 }
930
931
932 void ldv_timer_1(int state, struct timer_list * timer){
933 LDV_IN_INTERRUPT=2;
934 (rtl88ee_fw_clk_off_timer_callback)(timer->data);
935 LDV_IN_INTERRUPT=1;
936 }
937
938
939 void activate_suitable_timer_2(struct timer_list * timer, unsigned long data){
940 if(ldv_timer_2_0 == 0 || ldv_timer_2_0 == 2){
941 ldv_timer_list_2_0 = timer;
942 ldv_timer_list_2_0->data = data;
943 ldv_timer_2_0 = 1;
944 return;
945 }
946 if(ldv_timer_2_1 == 0 || ldv_timer_2_1 == 2){
947 ldv_timer_list_2_1 = timer;
948 ldv_timer_list_2_1->data = data;
949 ldv_timer_2_1 = 1;
950 return;
951 }
952 if(ldv_timer_2_2 == 0 || ldv_timer_2_2 == 2){
953 ldv_timer_list_2_2 = timer;
954 ldv_timer_list_2_2->data = data;
955 ldv_timer_2_2 = 1;
956 return;
957 }
958 if(ldv_timer_2_3 == 0 || ldv_timer_2_3 == 2){
959 ldv_timer_list_2_3 = timer;
960 ldv_timer_list_2_3->data = data;
961 ldv_timer_2_3 = 1;
962 return;
963 }
964 return;
965 }
966
967
968 int evil_hack_ar_lock(void){
969 mutex_lock(&ar_mutex);
970 return 1;
971 }
972
973
974 void ldv_timer_2(int state, struct timer_list * timer){
975 LDV_IN_INTERRUPT=2;
976 (rtl88e_dm_fast_antenna_training_callback)(timer->data);
977 LDV_IN_INTERRUPT=1;
978 }
979
980
981 /* DEG-ENVIRONMENT-BEGIN */
982 extern void ldv_main_exported_6(void);
983 extern void ldv_main_exported_0(void);
984 extern void ldv_main_exported_7(void);
985 extern void ldv_main_exported_5(void);
986
987 //********************* LDV MAIN *********************
988 //main
989 void entry_point(void){
990 ldv_initialize();
991 //args for callbacks
992 u8 ldvarg18;
993 u32 ldvarg11;
994 bool ldvarg51;
995 u8 ldvarg32;
996 u32 ldvarg7;
997 u32 ldvarg23;
998 u32 *ldvarg43;
999 enum nl80211_iftype ldvarg42;
1000 enum radio_path ldvarg12;
1001 u8 *ldvarg56;
1002 u32 ldvarg50;
1003 u8 ldvarg46;
1004 struct ieee80211_rx_status *ldvarg1;
1005 bool ldvarg37;
1006 u32 ldvarg53;
1007 u8 ldvarg29;
1008 u32 *ldvarg44;
1009 u32 ldvarg24;
1010 u32 ldvarg35;
1011 u8 *ldvarg0;
1012 u8 *ldvarg38;
1013 u8 ldvarg5;
1014 bool ldvarg33;
1015 enum rf_pwrstate ldvarg16;
1016 u32 ldvarg6;
1017 u8 *ldvarg48;
1018 u16 ldvarg4;
1019 u8 ldvarg14;
1020 u8 *ldvarg34;
1021 struct ieee80211_hdr *ldvarg28;
1022 struct rtl_stats *ldvarg2;
1023 bool ldvarg47;
1024 u8 ldvarg39;
1025 bool ldvarg20;
1026 struct ieee80211_tx_info *ldvarg31;
1027 enum led_ctl_mode ldvarg41;
1028 u8 ldvarg3;
1029 bool ldvarg49;
1030 u8 ldvarg57;
1031 enum radio_path ldvarg8;
1032 u32 ldvarg13;
1033 u32 ldvarg55;
1034 u32 ldvarg36;
1035 u32 ldvarg10;
1036 u8 *ldvarg40;
1037 struct rtl_stats ldvarg9;
1038 bool ldvarg45;
1039 u8 *ldvarg26;
1040 struct rtl_tcb_desc *ldvarg27;
1041 enum nl80211_channel_type ldvarg15;
1042 u8 *ldvarg30;
1043 bool ldvarg21;
1044 u32 ldvarg54;
1045 u8 *ldvarg17;
1046 u8 *ldvarg25;
1047 u8 *ldvarg22;
1048 int ldvarg19;
1049 u8 ldvarg52;
1050 struct pci_device_id const *ldvarg58;
1051 //initialization of machine states
1052 ldv_state_variable_6=0;
1053
1054 ldv_state_variable_3=1;
1055 ldv_state_variable_7=0;
1056
1057 timer_init_2();
1058
1059 ldv_state_variable_2=1;
1060
1061 timer_init_1();
1062
1063 ldv_state_variable_1=1;
1064
1065 ldv_state_variable_4=1;
1066 ref_cnt=0;
1067 ldv_state_variable_0=1;
1068 ldv_state_variable_5=0;
1069 while(1){
1070 switch(__VERIFIER_nondet_int()){
1071 case 0:{
1072 /*DEG-struct: handlers from structure rtlwifi_pm_ops*/
1073 /*DEG-CHECK: checking registration of rtlwifi_pm_ops structure*/
1074 if(ldv_state_variable_6 != 0){
1075 switch(__VERIFIER_nondet_int()){
1076 case 0:{
1077 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1078 if(ldv_state_variable_6 == 2){
1079 /*DEG-CALL: handler suspend from rtlwifi_pm_ops*/
1080 ldv_retval_18=(& rtl_pci_suspend)(rtlwifi_pm_ops_group1);
1081 if(ldv_retval_18==0){
1082 ldv_state_variable_6 = 3;
1083 }
1084 }
1085 }
1086 break;
1087 case 1:{
1088 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1089 if(ldv_state_variable_6 == 2){
1090 /*DEG-CALL: handler poweroff from rtlwifi_pm_ops*/
1091 ldv_retval_17=(& rtl_pci_suspend)(rtlwifi_pm_ops_group1);
1092 if(ldv_retval_17==0){
1093 ldv_state_variable_6 = 4;
1094 }
1095 }
1096 }
1097 break;
1098 case 2:{
1099 /*DEG-state: state 12 (look at corresponding state-chart diagram for details)*/
1100 if(ldv_state_variable_6 == 12){
1101 /*DEG-CALL: handler resume from rtlwifi_pm_ops*/
1102 ldv_retval_16=(& rtl_pci_resume)(rtlwifi_pm_ops_group1);
1103 if(ldv_retval_16==0){
1104 ldv_state_variable_6 = 15;
1105 }
1106 }
1107 }
1108 break;
1109 case 3:{
1110 /*DEG-state: state 14 (look at corresponding state-chart diagram for details)*/
1111 if(ldv_state_variable_6 == 14){
1112 /*DEG-CALL: handler thaw from rtlwifi_pm_ops*/
1113 ldv_retval_15=(& rtl_pci_resume)(rtlwifi_pm_ops_group1);
1114 if(ldv_retval_15==0){
1115 ldv_state_variable_6 = 15;
1116 }
1117 }
1118 }
1119 break;
1120 case 4:{
1121 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1122 if(ldv_state_variable_6 == 2){
1123 /*DEG-CALL: handler freeze from rtlwifi_pm_ops*/
1124 ldv_retval_14=(& rtl_pci_suspend)(rtlwifi_pm_ops_group1);
1125 if(ldv_retval_14==0){
1126 ldv_state_variable_6 = 5;
1127 }
1128 }
1129 }
1130 break;
1131 case 5:{
1132 /*DEG-state: state 13 (look at corresponding state-chart diagram for details)*/
1133 if(ldv_state_variable_6 == 13){
1134 /*DEG-CALL: handler restore from rtlwifi_pm_ops*/
1135 ldv_retval_13=(& rtl_pci_resume)(rtlwifi_pm_ops_group1);
1136 if(ldv_retval_13==0){
1137 ldv_state_variable_6 = 15;
1138 }
1139 }
1140 }
1141 break;
1142 case 6:{
1143 /*DEG-state: state 3 (look at corresponding state-chart diagram for details)*/
1144 if(ldv_state_variable_6 == 3){
1145 /*DEG-CALL: handler suspend_late from rtlwifi_pm_ops*/
1146 ldv_retval_12=ldv_suspend_late_6();
1147 if(ldv_retval_12==0){
1148 ldv_state_variable_6 = 6;
1149 }
1150 }
1151 }
1152 break;
1153 case 7:{
1154 /*DEG-state: state 9 (look at corresponding state-chart diagram for details)*/
1155 if(ldv_state_variable_6 == 9){
1156 /*DEG-CALL: handler restore_early from rtlwifi_pm_ops*/
1157 ldv_retval_11=ldv_restore_early_6();
1158 if(ldv_retval_11==0){
1159 ldv_state_variable_6 = 13;
1160 }
1161 }
1162 }
1163 break;
1164 case 8:{
1165 /*DEG-state: state 6 (look at corresponding state-chart diagram for details)*/
1166 if(ldv_state_variable_6 == 6){
1167 /*DEG-CALL: handler resume_early from rtlwifi_pm_ops*/
1168 ldv_retval_10=ldv_resume_early_6();
1169 if(ldv_retval_10==0){
1170 ldv_state_variable_6 = 12;
1171 }
1172 }
1173 }
1174 break;
1175 case 9:{
1176 /*DEG-state: state 11 (look at corresponding state-chart diagram for details)*/
1177 if(ldv_state_variable_6 == 11){
1178 /*DEG-CALL: handler thaw_early from rtlwifi_pm_ops*/
1179 ldv_retval_9=ldv_thaw_early_6();
1180 if(ldv_retval_9==0){
1181 ldv_state_variable_6 = 14;
1182 }
1183 }
1184 }
1185 break;
1186 case 10:{
1187 /*DEG-state: state 7 (look at corresponding state-chart diagram for details)*/
1188 if(ldv_state_variable_6 == 7){
1189 /*DEG-CALL: handler resume_noirq from rtlwifi_pm_ops*/
1190 ldv_retval_8=ldv_resume_noirq_6();
1191 if(ldv_retval_8==0){
1192 ldv_state_variable_6 = 12;
1193 }
1194 }
1195 }
1196 break;
1197 case 11:{
1198 /*DEG-state: state 5 (look at corresponding state-chart diagram for details)*/
1199 if(ldv_state_variable_6 == 5){
1200 /*DEG-CALL: handler freeze_noirq from rtlwifi_pm_ops*/
1201 ldv_retval_7=ldv_freeze_noirq_6();
1202 if(ldv_retval_7==0){
1203 ldv_state_variable_6 = 10;
1204 }
1205 }
1206 }
1207 break;
1208 case 12:{
1209 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1210 if(ldv_state_variable_6 == 1){
1211 /*DEG-CALL: handler prepare from rtlwifi_pm_ops*/
1212 ldv_retval_6=ldv_prepare_6();
1213 if(ldv_retval_6==0){
1214 ldv_state_variable_6 = 2;
1215 ref_cnt++;
1216 }
1217 }
1218 }
1219 break;
1220 case 13:{
1221 /*DEG-state: state 5 (look at corresponding state-chart diagram for details)*/
1222 if(ldv_state_variable_6 == 5){
1223 /*DEG-CALL: handler freeze_late from rtlwifi_pm_ops*/
1224 ldv_retval_5=ldv_freeze_late_6();
1225 if(ldv_retval_5==0){
1226 ldv_state_variable_6 = 11;
1227 }
1228 }
1229 }
1230 break;
1231 case 14:{
1232 /*DEG-state: state 10 (look at corresponding state-chart diagram for details)*/
1233 if(ldv_state_variable_6 == 10){
1234 /*DEG-CALL: handler thaw_noirq from rtlwifi_pm_ops*/
1235 ldv_retval_4=ldv_thaw_noirq_6();
1236 if(ldv_retval_4==0){
1237 ldv_state_variable_6 = 14;
1238 }
1239 }
1240 }
1241 break;
1242 case 15:{
1243 /*DEG-state: state 4 (look at corresponding state-chart diagram for details)*/
1244 if(ldv_state_variable_6 == 4){
1245 /*DEG-CALL: handler poweroff_noirq from rtlwifi_pm_ops*/
1246 ldv_retval_3=ldv_poweroff_noirq_6();
1247 if(ldv_retval_3==0){
1248 ldv_state_variable_6 = 8;
1249 }
1250 }
1251 }
1252 break;
1253 case 16:{
1254 /*DEG-state: state 4 (look at corresponding state-chart diagram for details)*/
1255 if(ldv_state_variable_6 == 4){
1256 /*DEG-CALL: handler poweroff_late from rtlwifi_pm_ops*/
1257 ldv_retval_2=ldv_poweroff_late_6();
1258 if(ldv_retval_2==0){
1259 ldv_state_variable_6 = 9;
1260 }
1261 }
1262 }
1263 break;
1264 case 17:{
1265 /*DEG-state: state 8 (look at corresponding state-chart diagram for details)*/
1266 if(ldv_state_variable_6 == 8){
1267 /*DEG-CALL: handler restore_noirq from rtlwifi_pm_ops*/
1268 ldv_retval_1=ldv_restore_noirq_6();
1269 if(ldv_retval_1==0){
1270 ldv_state_variable_6 = 13;
1271 }
1272 }
1273 }
1274 break;
1275 case 18:{
1276 /*DEG-state: state 3 (look at corresponding state-chart diagram for details)*/
1277 if(ldv_state_variable_6 == 3){
1278 /*DEG-CALL: handler suspend_noirq from rtlwifi_pm_ops*/
1279 ldv_retval_0=ldv_suspend_noirq_6();
1280 if(ldv_retval_0==0){
1281 ldv_state_variable_6 = 7;
1282 }
1283 }
1284 }
1285 break;
1286 case 19:{
1287 /*DEG-state: state 15 (look at corresponding state-chart diagram for details)*/
1288 if(ldv_state_variable_6 == 15){
1289 /*DEG-CALL: handler complete from rtlwifi_pm_ops*/
1290 ldv_complete_6();
1291 ldv_state_variable_6 = 1;
1292 ref_cnt--;
1293 }
1294 }
1295 break;
1296 default: ldv_assume(0);
1297 }
1298 }
1299 }
1300 break;
1301 case 1:{
1302 /*DEG-struct: handlers from structure ldv_init_timer_1*/
1303 /*DEG-CHECK: checking registration of ldv_init_timer_1 structure*/
1304 if(ldv_state_variable_3 != 0){
1305 choose_timer_3(ldv_timer_list_3);
1306 }
1307 }
1308 break;
1309 case 2:{
1310 /*DEG-struct: handlers from structure rtl8188ee_hal_ops*/
1311 /*DEG-CHECK: checking registration of rtl8188ee_hal_ops structure*/
1312 if(ldv_state_variable_7 != 0){
1313 switch(__VERIFIER_nondet_int()){
1314 case 0:{
1315 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1316 if(ldv_state_variable_7 == 2){
1317 /*DEG-CALL: handler get_hw_reg from rtl8188ee_hal_ops*/
1318 (& rtl88ee_get_hw_reg)(rtl8188ee_hal_ops_group1,ldvarg57,ldvarg56);
1319 /*DEG-postcall: default*/
1320 ldv_state_variable_7 = 2;
1321 }
1322 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1323 if(ldv_state_variable_7 == 1){
1324 /*DEG-CALL: handler get_hw_reg from rtl8188ee_hal_ops*/
1325 (& rtl88ee_get_hw_reg)(rtl8188ee_hal_ops_group1,ldvarg57,ldvarg56);
1326 /*DEG-postcall: default*/
1327 ldv_state_variable_7 = 1;
1328 }
1329 }
1330 break;
1331 case 1:{
1332 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1333 if(ldv_state_variable_7 == 2){
1334 /*DEG-CALL: handler set_bbreg from rtl8188ee_hal_ops*/
1335 (& rtl88e_phy_set_bb_reg)(rtl8188ee_hal_ops_group1,ldvarg54,ldvarg53,ldvarg55);
1336 /*DEG-postcall: default*/
1337 ldv_state_variable_7 = 2;
1338 }
1339 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1340 if(ldv_state_variable_7 == 1){
1341 /*DEG-CALL: handler set_bbreg from rtl8188ee_hal_ops*/
1342 (& rtl88e_phy_set_bb_reg)(rtl8188ee_hal_ops_group1,ldvarg54,ldvarg53,ldvarg55);
1343 /*DEG-postcall: default*/
1344 ldv_state_variable_7 = 1;
1345 }
1346 }
1347 break;
1348 case 2:{
1349 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1350 if(ldv_state_variable_7 == 2){
1351 /*DEG-CALL: handler set_key from rtl8188ee_hal_ops*/
1352 (& rtl88ee_set_key)(rtl8188ee_hal_ops_group1,ldvarg50,ldvarg48,ldvarg51,ldvarg52,ldvarg47,ldvarg49);
1353 /*DEG-postcall: default*/
1354 ldv_state_variable_7 = 2;
1355 }
1356 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1357 if(ldv_state_variable_7 == 1){
1358 /*DEG-CALL: handler set_key from rtl8188ee_hal_ops*/
1359 (& rtl88ee_set_key)(rtl8188ee_hal_ops_group1,ldvarg50,ldvarg48,ldvarg51,ldvarg52,ldvarg47,ldvarg49);
1360 /*DEG-postcall: default*/
1361 ldv_state_variable_7 = 1;
1362 }
1363 }
1364 break;
1365 case 3:{
1366 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1367 if(ldv_state_variable_7 == 2){
1368 /*DEG-CALL: handler disable_interrupt from rtl8188ee_hal_ops*/
1369 (& rtl88ee_disable_interrupt)(rtl8188ee_hal_ops_group1);
1370 /*DEG-postcall: default*/
1371 ldv_state_variable_7 = 2;
1372 }
1373 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1374 if(ldv_state_variable_7 == 1){
1375 /*DEG-CALL: handler disable_interrupt from rtl8188ee_hal_ops*/
1376 (& rtl88ee_disable_interrupt)(rtl8188ee_hal_ops_group1);
1377 /*DEG-postcall: default*/
1378 ldv_state_variable_7 = 1;
1379 }
1380 }
1381 break;
1382 case 4:{
1383 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1384 if(ldv_state_variable_7 == 2){
1385 /*DEG-CALL: handler update_rate_tbl from rtl8188ee_hal_ops*/
1386 (& rtl88ee_update_hal_rate_tbl)(rtl8188ee_hal_ops_group1,rtl8188ee_hal_ops_group2,ldvarg46);
1387 /*DEG-postcall: default*/
1388 ldv_state_variable_7 = 2;
1389 }
1390 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1391 if(ldv_state_variable_7 == 1){
1392 /*DEG-CALL: handler update_rate_tbl from rtl8188ee_hal_ops*/
1393 (& rtl88ee_update_hal_rate_tbl)(rtl8188ee_hal_ops_group1,rtl8188ee_hal_ops_group2,ldvarg46);
1394 /*DEG-postcall: default*/
1395 ldv_state_variable_7 = 1;
1396 }
1397 }
1398 break;
1399 case 5:{
1400 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1401 if(ldv_state_variable_7 == 2){
1402 /*DEG-CALL: handler read_eeprom_info from rtl8188ee_hal_ops*/
1403 (& rtl88ee_read_eeprom_info)(rtl8188ee_hal_ops_group1);
1404 /*DEG-postcall: default*/
1405 ldv_state_variable_7 = 2;
1406 }
1407 }
1408 break;
1409 case 6:{
1410 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1411 if(ldv_state_variable_7 == 2){
1412 /*DEG-CALL: handler set_chk_bssid from rtl8188ee_hal_ops*/
1413 (& rtl88ee_set_check_bssid)(rtl8188ee_hal_ops_group1,ldvarg45);
1414 /*DEG-postcall: default*/
1415 ldv_state_variable_7 = 2;
1416 }
1417 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1418 if(ldv_state_variable_7 == 1){
1419 /*DEG-CALL: handler set_chk_bssid from rtl8188ee_hal_ops*/
1420 (& rtl88ee_set_check_bssid)(rtl8188ee_hal_ops_group1,ldvarg45);
1421 /*DEG-postcall: default*/
1422 ldv_state_variable_7 = 1;
1423 }
1424 }
1425 break;
1426 case 7:{
1427 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1428 if(ldv_state_variable_7 == 2){
1429 /*DEG-CALL: handler interrupt_recognized from rtl8188ee_hal_ops*/
1430 (& rtl88ee_interrupt_recognized)(rtl8188ee_hal_ops_group1,ldvarg44,ldvarg43);
1431 /*DEG-postcall: default*/
1432 ldv_state_variable_7 = 2;
1433 }
1434 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1435 if(ldv_state_variable_7 == 1){
1436 /*DEG-CALL: handler interrupt_recognized from rtl8188ee_hal_ops*/
1437 (& rtl88ee_interrupt_recognized)(rtl8188ee_hal_ops_group1,ldvarg44,ldvarg43);
1438 /*DEG-postcall: default*/
1439 ldv_state_variable_7 = 1;
1440 }
1441 }
1442 break;
1443 case 8:{
1444 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1445 if(ldv_state_variable_7 == 2){
1446 /*DEG-CALL: handler set_network_type from rtl8188ee_hal_ops*/
1447 (& rtl88ee_set_network_type)(rtl8188ee_hal_ops_group1,ldvarg42);
1448 /*DEG-postcall: default*/
1449 ldv_state_variable_7 = 2;
1450 }
1451 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1452 if(ldv_state_variable_7 == 1){
1453 /*DEG-CALL: handler set_network_type from rtl8188ee_hal_ops*/
1454 (& rtl88ee_set_network_type)(rtl8188ee_hal_ops_group1,ldvarg42);
1455 /*DEG-postcall: default*/
1456 ldv_state_variable_7 = 1;
1457 }
1458 }
1459 break;
1460 case 9:{
1461 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1462 if(ldv_state_variable_7 == 2){
1463 /*DEG-CALL: handler set_channel_access from rtl8188ee_hal_ops*/
1464 (& rtl88ee_update_channel_access_setting)(rtl8188ee_hal_ops_group1);
1465 /*DEG-postcall: default*/
1466 ldv_state_variable_7 = 2;
1467 }
1468 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1469 if(ldv_state_variable_7 == 1){
1470 /*DEG-CALL: handler set_channel_access from rtl8188ee_hal_ops*/
1471 (& rtl88ee_update_channel_access_setting)(rtl8188ee_hal_ops_group1);
1472 /*DEG-postcall: default*/
1473 ldv_state_variable_7 = 1;
1474 }
1475 }
1476 break;
1477 case 10:{
1478 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1479 if(ldv_state_variable_7 == 2){
1480 /*DEG-CALL: handler hw_resume from rtl8188ee_hal_ops*/
1481 (& rtl88ee_resume)(rtl8188ee_hal_ops_group1);
1482 /*DEG-postcall: default*/
1483 ldv_state_variable_7 = 2;
1484 }
1485 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1486 if(ldv_state_variable_7 == 1){
1487 /*DEG-CALL: handler hw_resume from rtl8188ee_hal_ops*/
1488 (& rtl88ee_resume)(rtl8188ee_hal_ops_group1);
1489 /*DEG-postcall: default*/
1490 ldv_state_variable_7 = 1;
1491 }
1492 }
1493 break;
1494 case 11:{
1495 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1496 if(ldv_state_variable_7 == 2){
1497 /*DEG-CALL: handler hw_init from rtl8188ee_hal_ops*/
1498 (& rtl88ee_hw_init)(rtl8188ee_hal_ops_group1);
1499 /*DEG-postcall: default*/
1500 ldv_state_variable_7 = 2;
1501 }
1502 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1503 if(ldv_state_variable_7 == 1){
1504 /*DEG-CALL: handler hw_init from rtl8188ee_hal_ops*/
1505 (& rtl88ee_hw_init)(rtl8188ee_hal_ops_group1);
1506 /*DEG-postcall: default*/
1507 ldv_state_variable_7 = 1;
1508 }
1509 }
1510 break;
1511 case 12:{
1512 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1513 if(ldv_state_variable_7 == 2){
1514 /*DEG-CALL: handler hw_disable from rtl8188ee_hal_ops*/
1515 (& rtl88ee_card_disable)(rtl8188ee_hal_ops_group1);
1516 /*DEG-postcall: default*/
1517 ldv_state_variable_7 = 2;
1518 }
1519 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1520 if(ldv_state_variable_7 == 1){
1521 /*DEG-CALL: handler hw_disable from rtl8188ee_hal_ops*/
1522 (& rtl88ee_card_disable)(rtl8188ee_hal_ops_group1);
1523 /*DEG-postcall: default*/
1524 ldv_state_variable_7 = 1;
1525 }
1526 }
1527 break;
1528 case 13:{
1529 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1530 if(ldv_state_variable_7 == 2){
1531 /*DEG-CALL: handler led_control from rtl8188ee_hal_ops*/
1532 (& rtl88ee_led_control)(rtl8188ee_hal_ops_group1,ldvarg41);
1533 /*DEG-postcall: default*/
1534 ldv_state_variable_7 = 2;
1535 }
1536 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1537 if(ldv_state_variable_7 == 1){
1538 /*DEG-CALL: handler led_control from rtl8188ee_hal_ops*/
1539 (& rtl88ee_led_control)(rtl8188ee_hal_ops_group1,ldvarg41);
1540 /*DEG-postcall: default*/
1541 ldv_state_variable_7 = 1;
1542 }
1543 }
1544 break;
1545 case 14:{
1546 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1547 if(ldv_state_variable_7 == 2){
1548 /*DEG-CALL: handler set_desc from rtl8188ee_hal_ops*/
1549 (& rtl88ee_set_desc)(rtl8188ee_hal_ops_group1,ldvarg38,ldvarg37,ldvarg39,ldvarg40);
1550 /*DEG-postcall: default*/
1551 ldv_state_variable_7 = 2;
1552 }
1553 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1554 if(ldv_state_variable_7 == 1){
1555 /*DEG-CALL: handler set_desc from rtl8188ee_hal_ops*/
1556 (& rtl88ee_set_desc)(rtl8188ee_hal_ops_group1,ldvarg38,ldvarg37,ldvarg39,ldvarg40);
1557 /*DEG-postcall: default*/
1558 ldv_state_variable_7 = 1;
1559 }
1560 }
1561 break;
1562 case 15:{
1563 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1564 if(ldv_state_variable_7 == 2){
1565 /*DEG-CALL: handler update_interrupt_mask from rtl8188ee_hal_ops*/
1566 (& rtl88ee_update_interrupt_mask)(rtl8188ee_hal_ops_group1,ldvarg36,ldvarg35);
1567 /*DEG-postcall: default*/
1568 ldv_state_variable_7 = 2;
1569 }
1570 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1571 if(ldv_state_variable_7 == 1){
1572 /*DEG-CALL: handler update_interrupt_mask from rtl8188ee_hal_ops*/
1573 (& rtl88ee_update_interrupt_mask)(rtl8188ee_hal_ops_group1,ldvarg36,ldvarg35);
1574 /*DEG-postcall: default*/
1575 ldv_state_variable_7 = 1;
1576 }
1577 }
1578 break;
1579 case 16:{
1580 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1581 if(ldv_state_variable_7 == 2){
1582 /*DEG-CALL: handler get_desc from rtl8188ee_hal_ops*/
1583 (& rtl88ee_get_desc)(ldvarg34,ldvarg33,ldvarg32);
1584 /*DEG-postcall: default*/
1585 ldv_state_variable_7 = 2;
1586 }
1587 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1588 if(ldv_state_variable_7 == 1){
1589 /*DEG-CALL: handler get_desc from rtl8188ee_hal_ops*/
1590 (& rtl88ee_get_desc)(ldvarg34,ldvarg33,ldvarg32);
1591 /*DEG-postcall: default*/
1592 ldv_state_variable_7 = 1;
1593 }
1594 }
1595 break;
1596 case 17:{
1597 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1598 if(ldv_state_variable_7 == 2){
1599 /*DEG-CALL: handler fill_tx_desc from rtl8188ee_hal_ops*/
1600 (& rtl88ee_tx_fill_desc)(rtl8188ee_hal_ops_group1,ldvarg28,ldvarg26,ldvarg30,ldvarg31,rtl8188ee_hal_ops_group2,rtl8188ee_hal_ops_group0,ldvarg29,ldvarg27);
1601 /*DEG-postcall: default*/
1602 ldv_state_variable_7 = 2;
1603 }
1604 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1605 if(ldv_state_variable_7 == 1){
1606 /*DEG-CALL: handler fill_tx_desc from rtl8188ee_hal_ops*/
1607 (& rtl88ee_tx_fill_desc)(rtl8188ee_hal_ops_group1,ldvarg28,ldvarg26,ldvarg30,ldvarg31,rtl8188ee_hal_ops_group2,rtl8188ee_hal_ops_group0,ldvarg29,ldvarg27);
1608 /*DEG-postcall: default*/
1609 ldv_state_variable_7 = 1;
1610 }
1611 }
1612 break;
1613 case 18:{
1614 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1615 if(ldv_state_variable_7 == 2){
1616 /*DEG-CALL: handler deinit_sw_vars from rtl8188ee_hal_ops*/
1617 (& rtl88e_deinit_sw_vars)(rtl8188ee_hal_ops_group1);
1618 /*DEG-postcall: default*/
1619 ldv_state_variable_7 = 2;
1620 }
1621 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1622 if(ldv_state_variable_7 == 1){
1623 /*DEG-CALL: handler deinit_sw_vars from rtl8188ee_hal_ops*/
1624 (& rtl88e_deinit_sw_vars)(rtl8188ee_hal_ops_group1);
1625 /*DEG-postcall: default*/
1626 ldv_state_variable_7 = 1;
1627 }
1628 }
1629 break;
1630 case 19:{
1631 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1632 if(ldv_state_variable_7 == 2){
1633 /*DEG-CALL: handler radio_onoff_checking from rtl8188ee_hal_ops*/
1634 (& rtl88ee_gpio_radio_on_off_checking)(rtl8188ee_hal_ops_group1,ldvarg25);
1635 /*DEG-postcall: default*/
1636 ldv_state_variable_7 = 2;
1637 }
1638 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1639 if(ldv_state_variable_7 == 1){
1640 /*DEG-CALL: handler radio_onoff_checking from rtl8188ee_hal_ops*/
1641 (& rtl88ee_gpio_radio_on_off_checking)(rtl8188ee_hal_ops_group1,ldvarg25);
1642 /*DEG-postcall: default*/
1643 ldv_state_variable_7 = 1;
1644 }
1645 }
1646 break;
1647 case 20:{
1648 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1649 if(ldv_state_variable_7 == 2){
1650 /*DEG-CALL: handler get_bbreg from rtl8188ee_hal_ops*/
1651 (& rtl88e_phy_query_bb_reg)(rtl8188ee_hal_ops_group1,ldvarg24,ldvarg23);
1652 /*DEG-postcall: default*/
1653 ldv_state_variable_7 = 2;
1654 }
1655 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1656 if(ldv_state_variable_7 == 1){
1657 /*DEG-CALL: handler get_bbreg from rtl8188ee_hal_ops*/
1658 (& rtl88e_phy_query_bb_reg)(rtl8188ee_hal_ops_group1,ldvarg24,ldvarg23);
1659 /*DEG-postcall: default*/
1660 ldv_state_variable_7 = 1;
1661 }
1662 }
1663 break;
1664 case 21:{
1665 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1666 if(ldv_state_variable_7 == 2){
1667 /*DEG-CALL: handler fill_tx_cmddesc from rtl8188ee_hal_ops*/
1668 (& rtl88ee_tx_fill_cmddesc)(rtl8188ee_hal_ops_group1,ldvarg22,ldvarg21,ldvarg20,rtl8188ee_hal_ops_group0);
1669 /*DEG-postcall: default*/
1670 ldv_state_variable_7 = 2;
1671 }
1672 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1673 if(ldv_state_variable_7 == 1){
1674 /*DEG-CALL: handler fill_tx_cmddesc from rtl8188ee_hal_ops*/
1675 (& rtl88ee_tx_fill_cmddesc)(rtl8188ee_hal_ops_group1,ldvarg22,ldvarg21,ldvarg20,rtl8188ee_hal_ops_group0);
1676 /*DEG-postcall: default*/
1677 ldv_state_variable_7 = 1;
1678 }
1679 }
1680 break;
1681 case 22:{
1682 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1683 if(ldv_state_variable_7 == 2){
1684 /*DEG-CALL: handler set_qos from rtl8188ee_hal_ops*/
1685 (& rtl88ee_set_qos)(rtl8188ee_hal_ops_group1,ldvarg19);
1686 /*DEG-postcall: default*/
1687 ldv_state_variable_7 = 2;
1688 }
1689 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1690 if(ldv_state_variable_7 == 1){
1691 /*DEG-CALL: handler set_qos from rtl8188ee_hal_ops*/
1692 (& rtl88ee_set_qos)(rtl8188ee_hal_ops_group1,ldvarg19);
1693 /*DEG-postcall: default*/
1694 ldv_state_variable_7 = 1;
1695 }
1696 }
1697 break;
1698 case 23:{
1699 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1700 if(ldv_state_variable_7 == 2){
1701 /*DEG-CALL: handler set_hw_reg from rtl8188ee_hal_ops*/
1702 (& rtl88ee_set_hw_reg)(rtl8188ee_hal_ops_group1,ldvarg18,ldvarg17);
1703 /*DEG-postcall: default*/
1704 ldv_state_variable_7 = 2;
1705 }
1706 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1707 if(ldv_state_variable_7 == 1){
1708 /*DEG-CALL: handler set_hw_reg from rtl8188ee_hal_ops*/
1709 (& rtl88ee_set_hw_reg)(rtl8188ee_hal_ops_group1,ldvarg18,ldvarg17);
1710 /*DEG-postcall: default*/
1711 ldv_state_variable_7 = 1;
1712 }
1713 }
1714 break;
1715 case 24:{
1716 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1717 if(ldv_state_variable_7 == 2){
1718 /*DEG-CALL: handler set_rf_power_state from rtl8188ee_hal_ops*/
1719 (& rtl88e_phy_set_rf_power_state)(rtl8188ee_hal_ops_group1,ldvarg16);
1720 /*DEG-postcall: default*/
1721 ldv_state_variable_7 = 2;
1722 }
1723 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1724 if(ldv_state_variable_7 == 1){
1725 /*DEG-CALL: handler set_rf_power_state from rtl8188ee_hal_ops*/
1726 (& rtl88e_phy_set_rf_power_state)(rtl8188ee_hal_ops_group1,ldvarg16);
1727 /*DEG-postcall: default*/
1728 ldv_state_variable_7 = 1;
1729 }
1730 }
1731 break;
1732 case 25:{
1733 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1734 if(ldv_state_variable_7 == 2){
1735 /*DEG-CALL: handler set_bw_mode from rtl8188ee_hal_ops*/
1736 (& rtl88e_phy_set_bw_mode)(rtl8188ee_hal_ops_group1,ldvarg15);
1737 /*DEG-postcall: default*/
1738 ldv_state_variable_7 = 2;
1739 }
1740 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1741 if(ldv_state_variable_7 == 1){
1742 /*DEG-CALL: handler set_bw_mode from rtl8188ee_hal_ops*/
1743 (& rtl88e_phy_set_bw_mode)(rtl8188ee_hal_ops_group1,ldvarg15);
1744 /*DEG-postcall: default*/
1745 ldv_state_variable_7 = 1;
1746 }
1747 }
1748 break;
1749 case 26:{
1750 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1751 if(ldv_state_variable_7 == 2){
1752 /*DEG-CALL: handler init_sw_leds from rtl8188ee_hal_ops*/
1753 (& rtl88ee_init_sw_leds)(rtl8188ee_hal_ops_group1);
1754 /*DEG-postcall: default*/
1755 ldv_state_variable_7 = 2;
1756 }
1757 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1758 if(ldv_state_variable_7 == 1){
1759 /*DEG-CALL: handler init_sw_leds from rtl8188ee_hal_ops*/
1760 (& rtl88ee_init_sw_leds)(rtl8188ee_hal_ops_group1);
1761 /*DEG-postcall: default*/
1762 ldv_state_variable_7 = 1;
1763 }
1764 }
1765 break;
1766 case 27:{
1767 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1768 if(ldv_state_variable_7 == 2){
1769 /*DEG-CALL: handler enable_interrupt from rtl8188ee_hal_ops*/
1770 (& rtl88ee_enable_interrupt)(rtl8188ee_hal_ops_group1);
1771 /*DEG-postcall: default*/
1772 ldv_state_variable_7 = 2;
1773 }
1774 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1775 if(ldv_state_variable_7 == 1){
1776 /*DEG-CALL: handler enable_interrupt from rtl8188ee_hal_ops*/
1777 (& rtl88ee_enable_interrupt)(rtl8188ee_hal_ops_group1);
1778 /*DEG-postcall: default*/
1779 ldv_state_variable_7 = 1;
1780 }
1781 }
1782 break;
1783 case 28:{
1784 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1785 if(ldv_state_variable_7 == 2){
1786 /*DEG-CALL: handler tx_polling from rtl8188ee_hal_ops*/
1787 (& rtl88ee_tx_polling)(rtl8188ee_hal_ops_group1,ldvarg14);
1788 /*DEG-postcall: default*/
1789 ldv_state_variable_7 = 2;
1790 }
1791 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1792 if(ldv_state_variable_7 == 1){
1793 /*DEG-CALL: handler tx_polling from rtl8188ee_hal_ops*/
1794 (& rtl88ee_tx_polling)(rtl8188ee_hal_ops_group1,ldvarg14);
1795 /*DEG-postcall: default*/
1796 ldv_state_variable_7 = 1;
1797 }
1798 }
1799 break;
1800 case 29:{
1801 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1802 if(ldv_state_variable_7 == 2){
1803 /*DEG-CALL: handler set_bcn_reg from rtl8188ee_hal_ops*/
1804 (& rtl88ee_set_beacon_related_registers)(rtl8188ee_hal_ops_group1);
1805 /*DEG-postcall: default*/
1806 ldv_state_variable_7 = 2;
1807 }
1808 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1809 if(ldv_state_variable_7 == 1){
1810 /*DEG-CALL: handler set_bcn_reg from rtl8188ee_hal_ops*/
1811 (& rtl88ee_set_beacon_related_registers)(rtl8188ee_hal_ops_group1);
1812 /*DEG-postcall: default*/
1813 ldv_state_variable_7 = 1;
1814 }
1815 }
1816 break;
1817 case 30:{
1818 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1819 if(ldv_state_variable_7 == 2){
1820 /*DEG-CALL: handler dm_watchdog from rtl8188ee_hal_ops*/
1821 (& rtl88e_dm_watchdog)(rtl8188ee_hal_ops_group1);
1822 /*DEG-postcall: default*/
1823 ldv_state_variable_7 = 2;
1824 }
1825 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1826 if(ldv_state_variable_7 == 1){
1827 /*DEG-CALL: handler dm_watchdog from rtl8188ee_hal_ops*/
1828 (& rtl88e_dm_watchdog)(rtl8188ee_hal_ops_group1);
1829 /*DEG-postcall: default*/
1830 ldv_state_variable_7 = 1;
1831 }
1832 }
1833 break;
1834 case 31:{
1835 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1836 if(ldv_state_variable_7 == 2){
1837 /*DEG-CALL: handler switch_channel from rtl8188ee_hal_ops*/
1838 (& rtl88e_phy_sw_chnl)(rtl8188ee_hal_ops_group1);
1839 /*DEG-postcall: default*/
1840 ldv_state_variable_7 = 2;
1841 }
1842 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1843 if(ldv_state_variable_7 == 1){
1844 /*DEG-CALL: handler switch_channel from rtl8188ee_hal_ops*/
1845 (& rtl88e_phy_sw_chnl)(rtl8188ee_hal_ops_group1);
1846 /*DEG-postcall: default*/
1847 ldv_state_variable_7 = 1;
1848 }
1849 }
1850 break;
1851 case 32:{
1852 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1853 if(ldv_state_variable_7 == 2){
1854 /*DEG-CALL: handler set_rfreg from rtl8188ee_hal_ops*/
1855 (& rtl88e_phy_set_rf_reg)(rtl8188ee_hal_ops_group1,ldvarg12,ldvarg11,ldvarg10,ldvarg13);
1856 /*DEG-postcall: default*/
1857 ldv_state_variable_7 = 2;
1858 }
1859 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1860 if(ldv_state_variable_7 == 1){
1861 /*DEG-CALL: handler set_rfreg from rtl8188ee_hal_ops*/
1862 (& rtl88e_phy_set_rf_reg)(rtl8188ee_hal_ops_group1,ldvarg12,ldvarg11,ldvarg10,ldvarg13);
1863 /*DEG-postcall: default*/
1864 ldv_state_variable_7 = 1;
1865 }
1866 }
1867 break;
1868 case 33:{
1869 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1870 if(ldv_state_variable_7 == 2){
1871 /*DEG-CALL: handler enable_hw_sec from rtl8188ee_hal_ops*/
1872 (& rtl88ee_enable_hw_security_config)(rtl8188ee_hal_ops_group1);
1873 /*DEG-postcall: default*/
1874 ldv_state_variable_7 = 2;
1875 }
1876 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1877 if(ldv_state_variable_7 == 1){
1878 /*DEG-CALL: handler enable_hw_sec from rtl8188ee_hal_ops*/
1879 (& rtl88ee_enable_hw_security_config)(rtl8188ee_hal_ops_group1);
1880 /*DEG-postcall: default*/
1881 ldv_state_variable_7 = 1;
1882 }
1883 }
1884 break;
1885 case 34:{
1886 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1887 if(ldv_state_variable_7 == 2){
1888 /*DEG-CALL: handler get_btc_status from rtl8188ee_hal_ops*/
1889 (& rtl88e_get_btc_status)();
1890 /*DEG-postcall: default*/
1891 ldv_state_variable_7 = 2;
1892 }
1893 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1894 if(ldv_state_variable_7 == 1){
1895 /*DEG-CALL: handler get_btc_status from rtl8188ee_hal_ops*/
1896 (& rtl88e_get_btc_status)();
1897 /*DEG-postcall: default*/
1898 ldv_state_variable_7 = 1;
1899 }
1900 }
1901 break;
1902 case 35:{
1903 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1904 if(ldv_state_variable_7 == 2){
1905 /*DEG-CALL: handler rx_command_packet from rtl8188ee_hal_ops*/
1906 (& rtl88ee_rx_command_packet)(rtl8188ee_hal_ops_group1,ldvarg9,rtl8188ee_hal_ops_group0);
1907 /*DEG-postcall: default*/
1908 ldv_state_variable_7 = 2;
1909 }
1910 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1911 if(ldv_state_variable_7 == 1){
1912 /*DEG-CALL: handler rx_command_packet from rtl8188ee_hal_ops*/
1913 (& rtl88ee_rx_command_packet)(rtl8188ee_hal_ops_group1,ldvarg9,rtl8188ee_hal_ops_group0);
1914 /*DEG-postcall: default*/
1915 ldv_state_variable_7 = 1;
1916 }
1917 }
1918 break;
1919 case 36:{
1920 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1921 if(ldv_state_variable_7 == 2){
1922 /*DEG-CALL: handler init_sw_vars from rtl8188ee_hal_ops*/
1923 (& rtl88e_init_sw_vars)(rtl8188ee_hal_ops_group1);
1924 /*DEG-postcall: default*/
1925 ldv_state_variable_7 = 2;
1926 }
1927 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1928 if(ldv_state_variable_7 == 1){
1929 /*DEG-CALL: handler init_sw_vars from rtl8188ee_hal_ops*/
1930 (& rtl88e_init_sw_vars)(rtl8188ee_hal_ops_group1);
1931 /*DEG-postcall: default*/
1932 ldv_state_variable_7 = 1;
1933 }
1934 }
1935 break;
1936 case 37:{
1937 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1938 if(ldv_state_variable_7 == 2){
1939 /*DEG-CALL: handler hw_suspend from rtl8188ee_hal_ops*/
1940 (& rtl88ee_suspend)(rtl8188ee_hal_ops_group1);
1941 /*DEG-postcall: default*/
1942 ldv_state_variable_7 = 2;
1943 }
1944 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1945 if(ldv_state_variable_7 == 1){
1946 /*DEG-CALL: handler hw_suspend from rtl8188ee_hal_ops*/
1947 (& rtl88ee_suspend)(rtl8188ee_hal_ops_group1);
1948 /*DEG-postcall: default*/
1949 ldv_state_variable_7 = 1;
1950 }
1951 }
1952 break;
1953 case 38:{
1954 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1955 if(ldv_state_variable_7 == 2){
1956 /*DEG-CALL: handler get_rfreg from rtl8188ee_hal_ops*/
1957 (& rtl88e_phy_query_rf_reg)(rtl8188ee_hal_ops_group1,ldvarg8,ldvarg7,ldvarg6);
1958 /*DEG-postcall: default*/
1959 ldv_state_variable_7 = 2;
1960 }
1961 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1962 if(ldv_state_variable_7 == 1){
1963 /*DEG-CALL: handler get_rfreg from rtl8188ee_hal_ops*/
1964 (& rtl88e_phy_query_rf_reg)(rtl8188ee_hal_ops_group1,ldvarg8,ldvarg7,ldvarg6);
1965 /*DEG-postcall: default*/
1966 ldv_state_variable_7 = 1;
1967 }
1968 }
1969 break;
1970 case 39:{
1971 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1972 if(ldv_state_variable_7 == 2){
1973 /*DEG-CALL: handler set_bcn_intv from rtl8188ee_hal_ops*/
1974 (& rtl88ee_set_beacon_interval)(rtl8188ee_hal_ops_group1);
1975 /*DEG-postcall: default*/
1976 ldv_state_variable_7 = 2;
1977 }
1978 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1979 if(ldv_state_variable_7 == 1){
1980 /*DEG-CALL: handler set_bcn_intv from rtl8188ee_hal_ops*/
1981 (& rtl88ee_set_beacon_interval)(rtl8188ee_hal_ops_group1);
1982 /*DEG-postcall: default*/
1983 ldv_state_variable_7 = 1;
1984 }
1985 }
1986 break;
1987 case 40:{
1988 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
1989 if(ldv_state_variable_7 == 2){
1990 /*DEG-CALL: handler is_tx_desc_closed from rtl8188ee_hal_ops*/
1991 (& rtl88ee_is_tx_desc_closed)(rtl8188ee_hal_ops_group1,ldvarg5,ldvarg4);
1992 /*DEG-postcall: default*/
1993 ldv_state_variable_7 = 2;
1994 }
1995 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
1996 if(ldv_state_variable_7 == 1){
1997 /*DEG-CALL: handler is_tx_desc_closed from rtl8188ee_hal_ops*/
1998 (& rtl88ee_is_tx_desc_closed)(rtl8188ee_hal_ops_group1,ldvarg5,ldvarg4);
1999 /*DEG-postcall: default*/
2000 ldv_state_variable_7 = 1;
2001 }
2002 }
2003 break;
2004 case 41:{
2005 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
2006 if(ldv_state_variable_7 == 2){
2007 /*DEG-CALL: handler scan_operation_backup from rtl8188ee_hal_ops*/
2008 (& rtl88e_phy_scan_operation_backup)(rtl8188ee_hal_ops_group1,ldvarg3);
2009 /*DEG-postcall: default*/
2010 ldv_state_variable_7 = 2;
2011 }
2012 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
2013 if(ldv_state_variable_7 == 1){
2014 /*DEG-CALL: handler scan_operation_backup from rtl8188ee_hal_ops*/
2015 (& rtl88e_phy_scan_operation_backup)(rtl8188ee_hal_ops_group1,ldvarg3);
2016 /*DEG-postcall: default*/
2017 ldv_state_variable_7 = 1;
2018 }
2019 }
2020 break;
2021 case 42:{
2022 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
2023 if(ldv_state_variable_7 == 2){
2024 /*DEG-CALL: handler query_rx_desc from rtl8188ee_hal_ops*/
2025 (& rtl88ee_rx_query_desc)(rtl8188ee_hal_ops_group1,ldvarg2,ldvarg1,ldvarg0,rtl8188ee_hal_ops_group0);
2026 /*DEG-postcall: default*/
2027 ldv_state_variable_7 = 2;
2028 }
2029 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
2030 if(ldv_state_variable_7 == 1){
2031 /*DEG-CALL: handler query_rx_desc from rtl8188ee_hal_ops*/
2032 (& rtl88ee_rx_query_desc)(rtl8188ee_hal_ops_group1,ldvarg2,ldvarg1,ldvarg0,rtl8188ee_hal_ops_group0);
2033 /*DEG-postcall: default*/
2034 ldv_state_variable_7 = 1;
2035 }
2036 }
2037 break;
2038 case 43:{
2039 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
2040 if(ldv_state_variable_7 == 2){
2041 /*DEG-CALL: handler release from rtl8188ee_hal_ops*/
2042 ldv_release_7();
2043 /*DEG-postcall: module put*/
2044 ldv_state_variable_7 = 1;
2045 ref_cnt--;
2046 }
2047 }
2048 break;
2049 case 44:{
2050 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
2051 if(ldv_state_variable_7 == 1){
2052 /*DEG-CALL: handler probe from rtl8188ee_hal_ops*/
2053 ldv_probe_7();
2054 /*DEG-postcall: get module*/
2055 ldv_state_variable_7 = 2;
2056 ref_cnt++;
2057 }
2058 }
2059 break;
2060 default: ldv_assume(0);
2061 }
2062 }
2063 }
2064 break;
2065 case 3:{
2066 /*DEG-struct: handlers from structure ldv_setup_timer_2*/
2067 /*DEG-CHECK: checking registration of ldv_setup_timer_2 structure*/
2068 if(ldv_state_variable_2 != 0){
2069 choose_timer_2();
2070 }
2071 }
2072 break;
2073 case 4:{
2074 /*DEG-struct: handlers from structure ldv_setup_timer_3*/
2075 /*DEG-CHECK: checking registration of ldv_setup_timer_3 structure*/
2076 if(ldv_state_variable_1 != 0){
2077 choose_timer_1();
2078 }
2079 }
2080 break;
2081 case 5:{
2082 /*DEG-struct: handlers from structure ldv_init_timer_0*/
2083 /*DEG-CHECK: checking registration of ldv_init_timer_0 structure*/
2084 if(ldv_state_variable_4 != 0){
2085 choose_timer_4(ldv_timer_list_4);
2086 }
2087 }
2088 break;
2089 case 6:{
2090 /*DEG-struct: handlers from structure module*/
2091 /*DEG-CHECK: checking registration of module structure*/
2092 if(ldv_state_variable_0 != 0){
2093 switch(__VERIFIER_nondet_int()){
2094 case 0:{
2095 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
2096 if(ldv_state_variable_0 == 2 && ref_cnt==0){
2097 /*DEG-CALL: handler module_exit from module*/
2098 rtl88ee_driver_exit();
2099 ldv_state_variable_0 = 3;
2100 goto ldv_final;
2101 }
2102 }
2103 break;
2104 case 1:{
2105 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
2106 if(ldv_state_variable_0 == 1){
2107 /*DEG-CALL: handler module_init from module*/
2108 ldv_retval_19=rtl88ee_driver_init();
2109 if(ldv_retval_19!=0){
2110 ldv_state_variable_0 = 3;
2111 goto ldv_final;
2112 }
2113 /*DEG-postcall: if success*/
2114 if(ldv_retval_19==0){
2115 ldv_state_variable_0 = 2;
2116 ldv_state_variable_7 = 1;
2117 ldv_initialyze_rtl_hal_ops_7();
2118 ldv_state_variable_6 = 1;
2119 ldv_dev_pm_ops_6();
2120 }
2121 }
2122 }
2123 break;
2124 default: ldv_assume(0);
2125 }
2126 }
2127 }
2128 break;
2129 case 7:{
2130 /*DEG-struct: handlers from structure rtl88ee_driver*/
2131 /*DEG-CHECK: checking registration of rtl88ee_driver structure*/
2132 if(ldv_state_variable_5 != 0){
2133 switch(__VERIFIER_nondet_int()){
2134 case 0:{
2135 /*DEG-state: state 1 (look at corresponding state-chart diagram for details)*/
2136 if(ldv_state_variable_5 == 1){
2137 /*DEG-CALL: handler probe from rtl88ee_driver*/
2138 ldv_retval_20=(& rtl_pci_probe)(rtl88ee_driver_group1,ldvarg58);
2139 if(ldv_retval_20==0){
2140 ldv_state_variable_5 = 2;
2141 ref_cnt++;
2142 }
2143 }
2144 }
2145 break;
2146 case 1:{
2147 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
2148 if(ldv_state_variable_5 == 2){
2149 /*DEG-CALL: handler remove from rtl88ee_driver*/
2150 (& rtl_pci_disconnect)(rtl88ee_driver_group1);
2151 ldv_state_variable_5 = 1;
2152 }
2153 }
2154 break;
2155 case 2:{
2156 /*DEG-state: state 2 (look at corresponding state-chart diagram for details)*/
2157 if(ldv_state_variable_5 == 2){
2158 /*DEG-CALL: handler shutdown from rtl88ee_driver*/
2159 ldv_shutdown_5();
2160 ldv_state_variable_5 = 2;
2161 }
2162 }
2163 break;
2164 default: ldv_assume(0);
2165 }
2166 }
2167 }
2168 break;
2169 default: ldv_assume(0);
2170 }
2171 }
2172 ldv_final:
2173 ldv_check_final_state();
2174 return;
2175 }
2176 /* DEG-ENVIRONMENT-END */ 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../pci.h"
28 #include "../base.h"
29 #include "../stats.h"
30 #include "reg.h"
31 #include "def.h"
32 #include "phy.h"
33 #include "trx.h"
34 #include "led.h"
35 #include "dm.h"
36 #include "phy.h"
37
38 static u8 _rtl88ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
39 {
40 __le16 fc = rtl_get_fc(skb);
41
42 if (unlikely(ieee80211_is_beacon(fc)))
43 return QSLT_BEACON;
44 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
45 return QSLT_MGNT;
46
47 return skb->priority;
48 }
49
50 static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
51 struct rtl_stats *pstatus, u8 *pdesc,
52 struct rx_fwinfo_88e *p_drvinfo,
53 bool bpacket_match_bssid,
54 bool bpacket_toself, bool packet_beacon)
55 {
56 struct rtl_priv *rtlpriv = rtl_priv(hw);
57 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
58 struct phy_sts_cck_8192s_t *cck_buf;
59 struct phy_status_rpt *phystrpt =
60 (struct phy_status_rpt *)p_drvinfo;
61 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
62 char rx_pwr_all = 0, rx_pwr[4];
63 u8 rf_rx_num = 0, evm, pwdb_all;
64 u8 i, max_spatial_stream;
65 u32 rssi, total_rssi = 0;
66 bool is_cck = pstatus->is_cck;
67 u8 lan_idx, vga_idx;
68
69 /* Record it for next packet processing */
70 pstatus->packet_matchbssid = bpacket_match_bssid;
71 pstatus->packet_toself = bpacket_toself;
72 pstatus->packet_beacon = packet_beacon;
73 pstatus->rx_mimo_signalquality[0] = -1;
74 pstatus->rx_mimo_signalquality[1] = -1;
75
76 if (is_cck) {
77 u8 cck_highpwr;
78 u8 cck_agc_rpt;
79 /* CCK Driver info Structure is not the same as OFDM packet. */
80 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
81 cck_agc_rpt = cck_buf->cck_agc_rpt;
82
83 /* (1)Hardware does not provide RSSI for CCK
84 * (2)PWDB, Average PWDB cacluated by
85 * hardware (for rate adaptive)
86 */
87 if (ppsc->rfpwr_state == ERFON)
88 cck_highpwr =
89 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
90 BIT(9));
91 else
92 cck_highpwr = false;
93
94 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
95 vga_idx = (cck_agc_rpt & 0x1f);
96 switch (lan_idx) {
97 case 7:
98 if (vga_idx <= 27)
99 /*VGA_idx = 27~2*/
100 rx_pwr_all = -100 + 2*(27-vga_idx);
101 else
102 rx_pwr_all = -100;
103 break;
104 case 6:
105 /*VGA_idx = 2~0*/
106 rx_pwr_all = -48 + 2*(2-vga_idx);
107 break;
108 case 5:
109 /*VGA_idx = 7~5*/
110 rx_pwr_all = -42 + 2*(7-vga_idx);
111 break;
112 case 4:
113 /*VGA_idx = 7~4*/
114 rx_pwr_all = -36 + 2*(7-vga_idx);
115 break;
116 case 3:
117 /*VGA_idx = 7~0*/
118 rx_pwr_all = -24 + 2*(7-vga_idx);
119 break;
120 case 2:
121 if (cck_highpwr)
122 /*VGA_idx = 5~0*/
123 rx_pwr_all = -12 + 2*(5-vga_idx);
124 else
125 rx_pwr_all = -6 + 2*(5-vga_idx);
126 break;
127 case 1:
128 rx_pwr_all = 8-2*vga_idx;
129 break;
130 case 0:
131 rx_pwr_all = 14-2*vga_idx;
132 break;
133 default:
134 break;
135 }
136 rx_pwr_all += 6;
137 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
138 /* CCK gain is smaller than OFDM/MCS gain, */
139 /* so we add gain diff by experiences, the val is 6 */
140 pwdb_all += 6;
141 if (pwdb_all > 100)
142 pwdb_all = 100;
143 /* modify the offset to make the same
144 * gain index with OFDM.
145 */
146 if (pwdb_all > 34 && pwdb_all <= 42)
147 pwdb_all -= 2;
148 else if (pwdb_all > 26 && pwdb_all <= 34)
149 pwdb_all -= 6;
150 else if (pwdb_all > 14 && pwdb_all <= 26)
151 pwdb_all -= 8;
152 else if (pwdb_all > 4 && pwdb_all <= 14)
153 pwdb_all -= 4;
154 if (!cck_highpwr) {
155 if (pwdb_all >= 80)
156 pwdb_all = ((pwdb_all-80)<<1) +
157 ((pwdb_all-80)>>1) + 80;
158 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
159 pwdb_all += 3;
160 if (pwdb_all > 100)
161 pwdb_all = 100;
162 }
163
164 pstatus->rx_pwdb_all = pwdb_all;
165 pstatus->recvsignalpower = rx_pwr_all;
166
167 /* (3) Get Signal Quality (EVM) */
168 if (bpacket_match_bssid) {
169 u8 sq;
170
171 if (pstatus->rx_pwdb_all > 40)
172 sq = 100;
173 else {
174 sq = cck_buf->sq_rpt;
175 if (sq > 64)
176 sq = 0;
177 else if (sq < 20)
178 sq = 100;
179 else
180 sq = ((64 - sq) * 100) / 44;
181 }
182
183 pstatus->signalquality = sq;
184 pstatus->rx_mimo_signalquality[0] = sq;
185 pstatus->rx_mimo_signalquality[1] = -1;
186 }
187 } else {
188 rtlpriv->dm.rfpath_rxenable[0] =
189 rtlpriv->dm.rfpath_rxenable[1] = true;
190
191 /* (1)Get RSSI for HT rate */
192 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
193 /* we will judge RF RX path now. */
194 if (rtlpriv->dm.rfpath_rxenable[i])
195 rf_rx_num++;
196
197 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] &
198 0x3f) * 2) - 110;
199
200 /* Translate DBM to percentage. */
201 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
202 total_rssi += rssi;
203
204 /* Get Rx snr value in DB */
205 rtlpriv->stats.rx_snr_db[i] =
206 (long)(p_drvinfo->rxsnr[i] / 2);
207
208 /* Record Signal Strength for next packet */
209 if (bpacket_match_bssid)
210 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
211 }
212
213 /* (2)PWDB, Average PWDB cacluated by
214 * hardware (for rate adaptive)
215 */
216 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
217
218 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
219 pstatus->rx_pwdb_all = pwdb_all;
220 pstatus->rxpower = rx_pwr_all;
221 pstatus->recvsignalpower = rx_pwr_all;
222
223 /* (3)EVM of HT rate */
224 if (pstatus->is_ht && pstatus->rate >= DESC92C_RATEMCS8 &&
225 pstatus->rate <= DESC92C_RATEMCS15)
226 max_spatial_stream = 2;
227 else
228 max_spatial_stream = 1;
229
230 for (i = 0; i < max_spatial_stream; i++) {
231 evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]);
232
233 if (bpacket_match_bssid) {
234 /* Fill value in RFD, Get the first
235 * spatial stream onlyi
236 */
237 if (i == 0)
238 pstatus->signalquality =
239 (u8)(evm & 0xff);
240 pstatus->rx_mimo_signalquality[i] =
241 (u8)(evm & 0xff);
242 }
243 }
244 }
245
246 /* UI BSS List signal strength(in percentage),
247 * make it good looking, from 0~100.
248 */
249 if (is_cck)
250 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
251 pwdb_all));
252 else if (rf_rx_num != 0)
253 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
254 total_rssi /= rf_rx_num));
255 /*HW antenna diversity*/
256 rtldm->fat_table.antsel_rx_keep_0 = phystrpt->ant_sel;
257 rtldm->fat_table.antsel_rx_keep_1 = phystrpt->ant_sel_b;
258 rtldm->fat_table.antsel_rx_keep_2 = phystrpt->antsel_rx_keep_2;
259 }
260
261 static void _rtl88ee_smart_antenna(struct ieee80211_hw *hw,
262 struct rtl_stats *pstatus)
263 {
264 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
265 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
266 u8 antsel_tr_mux;
267 struct fast_ant_training *pfat_table = &rtldm->fat_table;
268
269 if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV) {
270 if (pfat_table->fat_state == FAT_TRAINING_STATE) {
271 if (pstatus->packet_toself) {
272 antsel_tr_mux =
273 (pfat_table->antsel_rx_keep_2 << 2) |
274 (pfat_table->antsel_rx_keep_1 << 1) |
275 pfat_table->antsel_rx_keep_0;
276 pfat_table->ant_sum[antsel_tr_mux] +=
277 pstatus->rx_pwdb_all;
278 pfat_table->ant_cnt[antsel_tr_mux]++;
279 }
280 }
281 } else if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
282 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)) {
283 if (pstatus->packet_toself || pstatus->packet_matchbssid) {
284 antsel_tr_mux = (pfat_table->antsel_rx_keep_2 << 2) |
285 (pfat_table->antsel_rx_keep_1 << 1) |
286 pfat_table->antsel_rx_keep_0;
287 rtl88e_dm_ant_sel_statistics(hw, antsel_tr_mux, 0,
288 pstatus->rx_pwdb_all);
289 }
290
291 }
292 }
293
294 static void _rtl88ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
295 struct sk_buff *skb,
296 struct rtl_stats *pstatus,
297 u8 *pdesc,
298 struct rx_fwinfo_88e *p_drvinfo)
299 {
300 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
301 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
302 struct ieee80211_hdr *hdr;
303 u8 *tmp_buf;
304 u8 *praddr;
305 u8 *psaddr;
306 __le16 fc;
307 bool packet_matchbssid, packet_toself, packet_beacon;
308
309 tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
310
311 hdr = (struct ieee80211_hdr *)tmp_buf;
312 fc = hdr->frame_control;
313 praddr = hdr->addr1;
314 psaddr = ieee80211_get_SA(hdr);
315 memcpy(pstatus->psaddr, psaddr, ETH_ALEN);
316
317 packet_matchbssid = ((!ieee80211_is_ctl(fc)) &&
318 (ether_addr_equal(mac->bssid, ieee80211_has_tods(fc) ?
319 hdr->addr1 : ieee80211_has_fromds(fc) ?
320 hdr->addr2 : hdr->addr3)) &&
321 (!pstatus->hwerror) &&
322 (!pstatus->crc) && (!pstatus->icv));
323
324 packet_toself = packet_matchbssid &&
325 (ether_addr_equal(praddr, rtlefuse->dev_addr));
326
327 if (ieee80211_is_beacon(hdr->frame_control))
328 packet_beacon = true;
329 else
330 packet_beacon = false;
331
332 _rtl88ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
333 packet_matchbssid, packet_toself,
334 packet_beacon);
335 _rtl88ee_smart_antenna(hw, pstatus);
336 rtl_process_phyinfo(hw, tmp_buf, pstatus);
337 }
338
339 static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
340 u8 *virtualaddress)
341 {
342 u32 dwtmp = 0;
343 memset(virtualaddress, 0, 8);
344
345 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
346 if (ptcb_desc->empkt_num == 1) {
347 dwtmp = ptcb_desc->empkt_len[0];
348 } else {
349 dwtmp = ptcb_desc->empkt_len[0];
350 dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
351 dwtmp += ptcb_desc->empkt_len[1];
352 }
353 SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
354
355 if (ptcb_desc->empkt_num <= 3) {
356 dwtmp = ptcb_desc->empkt_len[2];
357 } else {
358 dwtmp = ptcb_desc->empkt_len[2];
359 dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
360 dwtmp += ptcb_desc->empkt_len[3];
361 }
362 SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
363 if (ptcb_desc->empkt_num <= 5) {
364 dwtmp = ptcb_desc->empkt_len[4];
365 } else {
366 dwtmp = ptcb_desc->empkt_len[4];
367 dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
368 dwtmp += ptcb_desc->empkt_len[5];
369 }
370 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
371 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
372 if (ptcb_desc->empkt_num <= 7) {
373 dwtmp = ptcb_desc->empkt_len[6];
374 } else {
375 dwtmp = ptcb_desc->empkt_len[6];
376 dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
377 dwtmp += ptcb_desc->empkt_len[7];
378 }
379 SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
380 if (ptcb_desc->empkt_num <= 9) {
381 dwtmp = ptcb_desc->empkt_len[8];
382 } else {
383 dwtmp = ptcb_desc->empkt_len[8];
384 dwtmp += ((dwtmp%4) ? (4-dwtmp%4) : 0)+4;
385 dwtmp += ptcb_desc->empkt_len[9];
386 }
387 SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
388 }
389
390 bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
391 struct rtl_stats *status,
392 struct ieee80211_rx_status *rx_status,
393 u8 *pdesc, struct sk_buff *skb)
394 {
395 struct rtl_priv *rtlpriv = rtl_priv(hw);
396 struct rx_fwinfo_88e *p_drvinfo;
397 struct ieee80211_hdr *hdr;
398
399 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
400 status->packet_report_type = (u8)GET_RX_STATUS_DESC_RPT_SEL(pdesc);
401 if (status->packet_report_type == TX_REPORT2)
402 status->length = (u16)GET_RX_RPT2_DESC_PKT_LEN(pdesc);
403 else
404 status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
405 status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
406 RX_DRV_INFO_SIZE_UNIT;
407 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
408 status->icv = (u16)GET_RX_DESC_ICV(pdesc);
409 status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
410 status->hwerror = (status->crc | status->icv);
411 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
412 status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
413 status->shortpreamble = (u16)GET_RX_DESC_SPLCP(pdesc);
414 status->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
415 status->isfirst_ampdu = (bool)((GET_RX_DESC_PAGGR(pdesc) == 1) &&
416 (GET_RX_DESC_FAGGR(pdesc) == 1));
417 if (status->packet_report_type == NORMAL_RX)
418 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
419 status->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
420 status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
421
422 status->is_cck = RTL8188_RX_HAL_IS_CCK_RATE(status->rate);
423
424 status->macid = GET_RX_DESC_MACID(pdesc);
425 if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
426 status->wake_match = BIT(2);
427 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
428 status->wake_match = BIT(1);
429 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
430 status->wake_match = BIT(0);
431 else
432 status->wake_match = 0;
433 if (status->wake_match)
434 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
435 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
436 status->wake_match);
437 rx_status->freq = hw->conf.chandef.chan->center_freq;
438 rx_status->band = hw->conf.chandef.chan->band;
439
440 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size
441 + status->rx_bufshift);
442
443 if (status->crc)
444 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
445
446 if (status->rx_is40Mhzpacket)
447 rx_status->flag |= RX_FLAG_40MHZ;
448
449 if (status->is_ht)
450 rx_status->flag |= RX_FLAG_HT;
451
452 rx_status->flag |= RX_FLAG_MACTIME_START;
453
454 /* hw will set status->decrypted true, if it finds the
455 * frame is open data frame or mgmt frame.
456 * So hw will not decryption robust managment frame
457 * for IEEE80211w but still set status->decrypted
458 * true, so here we should set it back to undecrypted
459 * for IEEE80211w frame, and mac80211 sw will help
460 * to decrypt it
461 */
462 if (status->decrypted) {
463 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
464 (ieee80211_has_protected(hdr->frame_control)))
465 rx_status->flag |= RX_FLAG_DECRYPTED;
466 else
467 rx_status->flag &= ~RX_FLAG_DECRYPTED;
468 }
469
470 /* rate_idx: index of data rate into band's
471 * supported rates or MCS index if HT rates
472 * are use (RX_FLAG_HT)
473 * Notice: this is diff with windows define
474 */
475 rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
476 false, status->rate);
477
478 rx_status->mactime = status->timestamp_low;
479 if (phystatus == true) {
480 p_drvinfo = (struct rx_fwinfo_88e *)(skb->data +
481 status->rx_bufshift);
482
483 _rtl88ee_translate_rx_signal_stuff(hw,
484 skb, status, pdesc,
485 p_drvinfo);
486 }
487 rx_status->signal = status->recvsignalpower + 10;
488 if (status->packet_report_type == TX_REPORT2) {
489 status->macid_valid_entry[0] =
490 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
491 status->macid_valid_entry[1] =
492 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
493 }
494 return true;
495 }
496
497 void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
498 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
499 u8 *txbd, struct ieee80211_tx_info *info,
500 struct ieee80211_sta *sta,
501 struct sk_buff *skb,
502 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
503
504 {
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
507 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
508 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
509 u8 *pdesc = (u8 *)pdesc_tx;
510 u16 seq_number;
511 __le16 fc = hdr->frame_control;
512 unsigned int buf_len = 0;
513 unsigned int skb_len = skb->len;
514 u8 fw_qsel = _rtl88ee_map_hwqueue_to_fwqueue(skb, hw_queue);
515 bool firstseg = ((hdr->seq_ctrl &
516 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
517 bool lastseg = ((hdr->frame_control &
518 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
519 dma_addr_t mapping;
520 u8 bw_40 = 0;
521 u8 short_gi = 0;
522
523 if (mac->opmode == NL80211_IFTYPE_STATION) {
524 bw_40 = mac->bw_40;
525 } else if (mac->opmode == NL80211_IFTYPE_AP ||
526 mac->opmode == NL80211_IFTYPE_ADHOC) {
527 if (sta)
528 bw_40 = sta->ht_cap.cap &
529 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
530 }
531 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
532 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
533 /* reserve 8 byte for AMPDU early mode */
534 if (rtlhal->earlymode_enable) {
535 skb_push(skb, EM_HDR_LEN);
536 memset(skb->data, 0, EM_HDR_LEN);
537 }
538 buf_len = skb->len;
539 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
540 PCI_DMA_TODEVICE);
541 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
542 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
543 "DMA mapping error");
544 return;
545 }
546 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_88e));
547 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
548 firstseg = true;
549 lastseg = true;
550 }
551 if (firstseg) {
552 if (rtlhal->earlymode_enable) {
553 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
554 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
555 EM_HDR_LEN);
556 if (ptcb_desc->empkt_num) {
557 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
558 "Insert 8 byte.pTcb->EMPktNum:%d\n",
559 ptcb_desc->empkt_num);
560 _rtl88ee_insert_emcontent(ptcb_desc,
561 (u8 *)(skb->data));
562 }
563 } else {
564 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
565 }
566
567 ptcb_desc->use_driver_rate = true;
568 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
569 if (ptcb_desc->hw_rate > DESC92C_RATEMCS0)
570 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
571 else
572 short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
573
574 SET_TX_DESC_DATA_SHORTGI(pdesc, short_gi);
575
576 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
577 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
578 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
579 }
580 SET_TX_DESC_SEQ(pdesc, seq_number);
581 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
582 !ptcb_desc->cts_enable) ? 1 : 0));
583 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
584 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
585 SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
586
587 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
588 SET_TX_DESC_RTS_BW(pdesc, 0);
589 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
590 SET_TX_DESC_RTS_SHORT(pdesc,
591 ((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
592 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
593 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
594
595 if (ptcb_desc->tx_enable_sw_calc_duration)
596 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
597
598 if (bw_40) {
599 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
600 SET_TX_DESC_DATA_BW(pdesc, 1);
601 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
602 } else {
603 SET_TX_DESC_DATA_BW(pdesc, 0);
604 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
605 mac->cur_40_prime_sc);
606 }
607 } else {
608 SET_TX_DESC_DATA_BW(pdesc, 0);
609 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
610 }
611
612 SET_TX_DESC_LINIP(pdesc, 0);
613 SET_TX_DESC_PKT_SIZE(pdesc, (u16)skb_len);
614 if (sta) {
615 u8 ampdu_density = sta->ht_cap.ampdu_density;
616 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
617 }
618 if (info->control.hw_key) {
619 struct ieee80211_key_conf *keyconf;
620
621 keyconf = info->control.hw_key;
622 switch (keyconf->cipher) {
623 case WLAN_CIPHER_SUITE_WEP40:
624 case WLAN_CIPHER_SUITE_WEP104:
625 case WLAN_CIPHER_SUITE_TKIP:
626 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
627 break;
628 case WLAN_CIPHER_SUITE_CCMP:
629 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
630 break;
631 default:
632 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
633 break;
634
635 }
636 }
637
638 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
639 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
640 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
641 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
642 1 : 0);
643 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
644
645 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
646 /* Set TxRate and RTSRate in TxDesc */
647 /* This prevent Tx initial rate of new-coming packets */
648 /* from being overwritten by retried packet rate.*/
649 if (!ptcb_desc->use_driver_rate) {
650 /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
651 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
652 }
653 if (ieee80211_is_data_qos(fc)) {
654 if (mac->rdg_en) {
655 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
656 "Enable RDG function.\n");
657 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
658 SET_TX_DESC_HTC(pdesc, 1);
659 }
660 }
661 }
662
663 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
664 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
665 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)buf_len);
666 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
667 if (rtlpriv->dm.useramask) {
668 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
669 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
670 } else {
671 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
672 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
673 }
674 if (ieee80211_is_data_qos(fc))
675 SET_TX_DESC_QOS(pdesc, 1);
676
677 if (!ieee80211_is_data_qos(fc))
678 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
679 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
680 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
681 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
682 SET_TX_DESC_BMC(pdesc, 1);
683 }
684
685 rtl88e_dm_set_tx_ant_by_tx_info(hw, pdesc, ptcb_desc->mac_id);
686 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
687 }
688
689 void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
690 u8 *pdesc, bool firstseg,
691 bool lastseg, struct sk_buff *skb)
692 {
693 struct rtl_priv *rtlpriv = rtl_priv(hw);
694 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
695 u8 fw_queue = QSLT_BEACON;
696
697 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
698 skb->data, skb->len,
699 PCI_DMA_TODEVICE);
700
701 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
702 __le16 fc = hdr->frame_control;
703
704 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
705 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
706 "DMA mapping error");
707 return;
708 }
709 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
710
711 if (firstseg)
712 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
713
714 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
715
716 SET_TX_DESC_SEQ(pdesc, 0);
717
718 SET_TX_DESC_LINIP(pdesc, 0);
719
720 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
721
722 SET_TX_DESC_FIRST_SEG(pdesc, 1);
723 SET_TX_DESC_LAST_SEG(pdesc, 1);
724
725 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
726
727 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
728
729 SET_TX_DESC_RATE_ID(pdesc, 7);
730 SET_TX_DESC_MACID(pdesc, 0);
731
732 SET_TX_DESC_OWN(pdesc, 1);
733
734 SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len));
735
736 SET_TX_DESC_FIRST_SEG(pdesc, 1);
737 SET_TX_DESC_LAST_SEG(pdesc, 1);
738
739 SET_TX_DESC_OFFSET(pdesc, 0x20);
740
741 SET_TX_DESC_USE_RATE(pdesc, 1);
742
743 if (!ieee80211_is_data_qos(fc))
744 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
745
746 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
747 "H2C Tx Cmd Content\n",
748 pdesc, TX_DESC_SIZE);
749 }
750
751 void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
752 bool istx, u8 desc_name, u8 *val)
753 {
754 if (istx == true) {
755 switch (desc_name) {
756 case HW_DESC_OWN:
757 SET_TX_DESC_OWN(pdesc, 1);
758 break;
759 case HW_DESC_TX_NEXTDESC_ADDR:
760 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
761 break;
762 default:
763 RT_ASSERT(false, "ERR txdesc :%d not process\n",
764 desc_name);
765 break;
766 }
767 } else {
768 switch (desc_name) {
769 case HW_DESC_RXOWN:
770 SET_RX_DESC_OWN(pdesc, 1);
771 break;
772 case HW_DESC_RXBUFF_ADDR:
773 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *)val);
774 break;
775 case HW_DESC_RXPKT_LEN:
776 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *)val);
777 break;
778 case HW_DESC_RXERO:
779 SET_RX_DESC_EOR(pdesc, 1);
780 break;
781 default:
782 RT_ASSERT(false, "ERR rxdesc :%d not process\n",
783 desc_name);
784 break;
785 }
786 }
787 }
788
789 u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
790 {
791 u32 ret = 0;
792
793 if (istx == true) {
794 switch (desc_name) {
795 case HW_DESC_OWN:
796 ret = GET_TX_DESC_OWN(pdesc);
797 break;
798 case HW_DESC_TXBUFF_ADDR:
799 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc);
800 break;
801 default:
802 RT_ASSERT(false, "ERR txdesc :%d not process\n",
803 desc_name);
804 break;
805 }
806 } else {
807 switch (desc_name) {
808 case HW_DESC_OWN:
809 ret = GET_RX_DESC_OWN(pdesc);
810 break;
811 case HW_DESC_RXPKT_LEN:
812 ret = GET_RX_DESC_PKT_LEN(pdesc);
813 break;
814 case HW_DESC_RXBUFF_ADDR:
815 ret = GET_RX_DESC_BUFF_ADDR(pdesc);
816 break;
817 default:
818 RT_ASSERT(false, "ERR rxdesc :%d not process\n",
819 desc_name);
820 break;
821 }
822 }
823 return ret;
824 }
825
826 bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
827 {
828 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
829 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
830 u8 *entry = (u8 *)(&ring->desc[ring->idx]);
831 u8 own = (u8)rtl88ee_get_desc(entry, true, HW_DESC_OWN);
832
833 /*beacon packet will only use the first
834 *descriptor defautly,and the own may not
835 *be cleared by the hardware
836 */
837 if (own)
838 return false;
839 return true;
840 }
841
842 void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
843 {
844 struct rtl_priv *rtlpriv = rtl_priv(hw);
845 if (hw_queue == BEACON_QUEUE) {
846 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
847 } else {
848 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
849 BIT(0) << (hw_queue));
850 }
851 }
852
853 u32 rtl88ee_rx_command_packet(struct ieee80211_hw *hw,
854 struct rtl_stats status,
855 struct sk_buff *skb)
856 {
857 return 0;
858 } 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
38 #include "debug.h"
39
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
51
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
55
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
67
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
71
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
77
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
81
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
84
85 /* QoS related. */
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
88 /*aci: 0x10 Video*/
89 /*aci: 0x11 Voice*/
90 /*Max: define total number.*/
91 #define AC0_BE 0
92 #define AC1_BK 1
93 #define AC2_VI 2
94 #define AC3_VO 3
95 #define AC_MAX 4
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102
103 #define TOTAL_CAM_ENTRY 32
104
105 /*slot time for 11g. */
106 #define RTL_SLOT_TIME_9 9
107 #define RTL_SLOT_TIME_20 20
108
109 /*related to tcp/ip. */
110 #define SNAP_SIZE 6
111 #define PROTOC_TYPE_SIZE 2
112
113 /*related with 802.11 frame*/
114 #define MAC80211_3ADDR_LEN 24
115 #define MAC80211_4ADDR_LEN 30
116
117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
118 #define CHANNEL_MAX_NUMBER_2G 14
119 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
120 *"phy_GetChnlGroup8812A" and
121 * "Hal_ReadTxPowerInfo8812A"
122 */
123 #define CHANNEL_MAX_NUMBER_5G_80M 7
124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
125 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
126 *"phy_GetChnlGroup8812A" and
127 * "Hal_ReadTxPowerInfo8812A"
128 */
129 #define CHANNEL_MAX_NUMBER_5G_80M 7
130 #define MAX_PG_GROUP 13
131 #define CHANNEL_GROUP_MAX_2G 3
132 #define CHANNEL_GROUP_IDX_5GL 3
133 #define CHANNEL_GROUP_IDX_5GM 6
134 #define CHANNEL_GROUP_IDX_5GH 9
135 #define CHANNEL_GROUP_MAX_5G 9
136 #define CHANNEL_MAX_NUMBER_2G 14
137 #define AVG_THERMAL_NUM 8
138 #define AVG_THERMAL_NUM_88E 4
139 #define AVG_THERMAL_NUM_8723BE 4
140 #define MAX_TID_COUNT 9
141
142 /* for early mode */
143 #define FCS_LEN 4
144 #define EM_HDR_LEN 8
145
146 enum rtl8192c_h2c_cmd {
147 H2C_AP_OFFLOAD = 0,
148 H2C_SETPWRMODE = 1,
149 H2C_JOINBSSRPT = 2,
150 H2C_RSVDPAGE = 3,
151 H2C_RSSI_REPORT = 5,
152 H2C_RA_MASK = 6,
153 H2C_MACID_PS_MODE = 7,
154 H2C_P2P_PS_OFFLOAD = 8,
155 H2C_MAC_MODE_SEL = 9,
156 H2C_PWRM = 15,
157 H2C_P2P_PS_CTW_CMD = 24,
158 MAX_H2CCMD
159 };
160
161 #define MAX_TX_COUNT 4
162 #define MAX_REGULATION_NUM 4
163 #define MAX_RF_PATH_NUM 4
164 #define MAX_RATE_SECTION_NUM 6
165 #define MAX_2_4G_BANDWITH_NUM 4
166 #define MAX_5G_BANDWITH_NUM 4
167 #define MAX_RF_PATH 4
168 #define MAX_CHNL_GROUP_24G 6
169 #define MAX_CHNL_GROUP_5G 14
170
171 #define TX_PWR_BY_RATE_NUM_BAND 2
172 #define TX_PWR_BY_RATE_NUM_RF 4
173 #define TX_PWR_BY_RATE_NUM_SECTION 12
174 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
175 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
176
177 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
178
179 #define DEL_SW_IDX_SZ 30
180 #define BAND_NUM 3
181
182 /* For now, it's just for 8192ee
183 * but not OK yet, keep it 0
184 */
185 #define DMA_IS_64BIT 0
186 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
187
188 enum rf_tx_num {
189 RF_1TX = 0,
190 RF_2TX,
191 RF_MAX_TX_NUM,
192 RF_TX_NUM_NONIMPLEMENT,
193 };
194
195 #define PACKET_NORMAL 0
196 #define PACKET_DHCP 1
197 #define PACKET_ARP 2
198 #define PACKET_EAPOL 3
199
200 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
201 #define RSVD_WOL_PATTERN_NUM 1
202 #define WKFMCAM_ADDR_NUM 6
203 #define WKFMCAM_SIZE 24
204
205 #define MAX_WOL_BIT_MASK_SIZE 16
206 /* MIN LEN keeps 13 here */
207 #define MIN_WOL_PATTERN_SIZE 13
208 #define MAX_WOL_PATTERN_SIZE 128
209
210 #define WAKE_ON_MAGIC_PACKET BIT(0)
211 #define WAKE_ON_PATTERN_MATCH BIT(1)
212
213 #define WOL_REASON_PTK_UPDATE BIT(0)
214 #define WOL_REASON_GTK_UPDATE BIT(1)
215 #define WOL_REASON_DISASSOC BIT(2)
216 #define WOL_REASON_DEAUTH BIT(3)
217 #define WOL_REASON_AP_LOST BIT(4)
218 #define WOL_REASON_MAGIC_PKT BIT(5)
219 #define WOL_REASON_UNICAST_PKT BIT(6)
220 #define WOL_REASON_PATTERN_PKT BIT(7)
221 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
222 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
223 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
224
225 struct rtlwifi_firmware_header {
226 __le16 signature;
227 u8 category;
228 u8 function;
229 __le16 version;
230 u8 subversion;
231 u8 rsvd1;
232 u8 month;
233 u8 date;
234 u8 hour;
235 u8 minute;
236 __le16 ramcodeSize;
237 __le16 rsvd2;
238 __le32 svnindex;
239 __le32 rsvd3;
240 __le32 rsvd4;
241 __le32 rsvd5;
242 };
243
244 struct txpower_info_2g {
245 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
246 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
247 /*If only one tx, only BW20 and OFDM are used.*/
248 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
249 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
250 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
251 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
252 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
253 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
254 };
255
256 struct txpower_info_5g {
257 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
258 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
259 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
260 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
261 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
262 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
263 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
264 };
265
266 enum rate_section {
267 CCK = 0,
268 OFDM,
269 HT_MCS0_MCS7,
270 HT_MCS8_MCS15,
271 VHT_1SSMCS0_1SSMCS9,
272 VHT_2SSMCS0_2SSMCS9,
273 };
274
275 enum intf_type {
276 INTF_PCI = 0,
277 INTF_USB = 1,
278 };
279
280 enum radio_path {
281 RF90_PATH_A = 0,
282 RF90_PATH_B = 1,
283 RF90_PATH_C = 2,
284 RF90_PATH_D = 3,
285 };
286
287 enum regulation_txpwr_lmt {
288 TXPWR_LMT_FCC = 0,
289 TXPWR_LMT_MKK = 1,
290 TXPWR_LMT_ETSI = 2,
291 TXPWR_LMT_WW = 3,
292
293 TXPWR_LMT_MAX_REGULATION_NUM = 4
294 };
295
296 enum rt_eeprom_type {
297 EEPROM_93C46,
298 EEPROM_93C56,
299 EEPROM_BOOT_EFUSE,
300 };
301
302 enum ttl_status {
303 RTL_STATUS_INTERFACE_START = 0,
304 };
305
306 enum hardware_type {
307 HARDWARE_TYPE_RTL8192E,
308 HARDWARE_TYPE_RTL8192U,
309 HARDWARE_TYPE_RTL8192SE,
310 HARDWARE_TYPE_RTL8192SU,
311 HARDWARE_TYPE_RTL8192CE,
312 HARDWARE_TYPE_RTL8192CU,
313 HARDWARE_TYPE_RTL8192DE,
314 HARDWARE_TYPE_RTL8192DU,
315 HARDWARE_TYPE_RTL8723AE,
316 HARDWARE_TYPE_RTL8723U,
317 HARDWARE_TYPE_RTL8188EE,
318 HARDWARE_TYPE_RTL8723BE,
319 HARDWARE_TYPE_RTL8192EE,
320 HARDWARE_TYPE_RTL8821AE,
321 HARDWARE_TYPE_RTL8812AE,
322
323 /* keep it last */
324 HARDWARE_TYPE_NUM
325 };
326
327 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
328 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
329 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
330 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
331 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
332 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
333 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
334 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
335 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
336 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
337 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
338 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
339 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
340 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
341 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
342 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
343 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
344 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
345 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
346 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
347 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
348 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
349 #define IS_HARDWARE_TYPE_8723(rtlhal) \
350 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
351
352 #define RX_HAL_IS_CCK_RATE(rxmcs) \
353 ((rxmcs) == DESC_RATE1M || \
354 (rxmcs) == DESC_RATE2M || \
355 (rxmcs) == DESC_RATE5_5M || \
356 (rxmcs) == DESC_RATE11M)
357
358 enum scan_operation_backup_opt {
359 SCAN_OPT_BACKUP = 0,
360 SCAN_OPT_BACKUP_BAND0 = 0,
361 SCAN_OPT_BACKUP_BAND1,
362 SCAN_OPT_RESTORE,
363 SCAN_OPT_MAX
364 };
365
366 /*RF state.*/
367 enum rf_pwrstate {
368 ERFON,
369 ERFSLEEP,
370 ERFOFF
371 };
372
373 struct bb_reg_def {
374 u32 rfintfs;
375 u32 rfintfi;
376 u32 rfintfo;
377 u32 rfintfe;
378 u32 rf3wire_offset;
379 u32 rflssi_select;
380 u32 rftxgain_stage;
381 u32 rfhssi_para1;
382 u32 rfhssi_para2;
383 u32 rfsw_ctrl;
384 u32 rfagc_control1;
385 u32 rfagc_control2;
386 u32 rfrxiq_imbal;
387 u32 rfrx_afe;
388 u32 rftxiq_imbal;
389 u32 rftx_afe;
390 u32 rf_rb; /* rflssi_readback */
391 u32 rf_rbpi; /* rflssi_readbackpi */
392 };
393
394 enum io_type {
395 IO_CMD_PAUSE_DM_BY_SCAN = 0,
396 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
397 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
398 IO_CMD_RESUME_DM_BY_SCAN = 2,
399 };
400
401 enum hw_variables {
402 HW_VAR_ETHER_ADDR,
403 HW_VAR_MULTICAST_REG,
404 HW_VAR_BASIC_RATE,
405 HW_VAR_BSSID,
406 HW_VAR_MEDIA_STATUS,
407 HW_VAR_SECURITY_CONF,
408 HW_VAR_BEACON_INTERVAL,
409 HW_VAR_ATIM_WINDOW,
410 HW_VAR_LISTEN_INTERVAL,
411 HW_VAR_CS_COUNTER,
412 HW_VAR_DEFAULTKEY0,
413 HW_VAR_DEFAULTKEY1,
414 HW_VAR_DEFAULTKEY2,
415 HW_VAR_DEFAULTKEY3,
416 HW_VAR_SIFS,
417 HW_VAR_R2T_SIFS,
418 HW_VAR_DIFS,
419 HW_VAR_EIFS,
420 HW_VAR_SLOT_TIME,
421 HW_VAR_ACK_PREAMBLE,
422 HW_VAR_CW_CONFIG,
423 HW_VAR_CW_VALUES,
424 HW_VAR_RATE_FALLBACK_CONTROL,
425 HW_VAR_CONTENTION_WINDOW,
426 HW_VAR_RETRY_COUNT,
427 HW_VAR_TR_SWITCH,
428 HW_VAR_COMMAND,
429 HW_VAR_WPA_CONFIG,
430 HW_VAR_AMPDU_MIN_SPACE,
431 HW_VAR_SHORTGI_DENSITY,
432 HW_VAR_AMPDU_FACTOR,
433 HW_VAR_MCS_RATE_AVAILABLE,
434 HW_VAR_AC_PARAM,
435 HW_VAR_ACM_CTRL,
436 HW_VAR_DIS_Req_Qsize,
437 HW_VAR_CCX_CHNL_LOAD,
438 HW_VAR_CCX_NOISE_HISTOGRAM,
439 HW_VAR_CCX_CLM_NHM,
440 HW_VAR_TxOPLimit,
441 HW_VAR_TURBO_MODE,
442 HW_VAR_RF_STATE,
443 HW_VAR_RF_OFF_BY_HW,
444 HW_VAR_BUS_SPEED,
445 HW_VAR_SET_DEV_POWER,
446
447 HW_VAR_RCR,
448 HW_VAR_RATR_0,
449 HW_VAR_RRSR,
450 HW_VAR_CPU_RST,
451 HW_VAR_CHECK_BSSID,
452 HW_VAR_LBK_MODE,
453 HW_VAR_AES_11N_FIX,
454 HW_VAR_USB_RX_AGGR,
455 HW_VAR_USER_CONTROL_TURBO_MODE,
456 HW_VAR_RETRY_LIMIT,
457 HW_VAR_INIT_TX_RATE,
458 HW_VAR_TX_RATE_REG,
459 HW_VAR_EFUSE_USAGE,
460 HW_VAR_EFUSE_BYTES,
461 HW_VAR_AUTOLOAD_STATUS,
462 HW_VAR_RF_2R_DISABLE,
463 HW_VAR_SET_RPWM,
464 HW_VAR_H2C_FW_PWRMODE,
465 HW_VAR_H2C_FW_JOINBSSRPT,
466 HW_VAR_H2C_FW_MEDIASTATUSRPT,
467 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
468 HW_VAR_FW_PSMODE_STATUS,
469 HW_VAR_INIT_RTS_RATE,
470 HW_VAR_RESUME_CLK_ON,
471 HW_VAR_FW_LPS_ACTION,
472 HW_VAR_1X1_RECV_COMBINE,
473 HW_VAR_STOP_SEND_BEACON,
474 HW_VAR_TSF_TIMER,
475 HW_VAR_IO_CMD,
476
477 HW_VAR_RF_RECOVERY,
478 HW_VAR_H2C_FW_UPDATE_GTK,
479 HW_VAR_WF_MASK,
480 HW_VAR_WF_CRC,
481 HW_VAR_WF_IS_MAC_ADDR,
482 HW_VAR_H2C_FW_OFFLOAD,
483 HW_VAR_RESET_WFCRC,
484
485 HW_VAR_HANDLE_FW_C2H,
486 HW_VAR_DL_FW_RSVD_PAGE,
487 HW_VAR_AID,
488 HW_VAR_HW_SEQ_ENABLE,
489 HW_VAR_CORRECT_TSF,
490 HW_VAR_BCN_VALID,
491 HW_VAR_FWLPS_RF_ON,
492 HW_VAR_DUAL_TSF_RST,
493 HW_VAR_SWITCH_EPHY_WoWLAN,
494 HW_VAR_INT_MIGRATION,
495 HW_VAR_INT_AC,
496 HW_VAR_RF_TIMING,
497
498 HAL_DEF_WOWLAN,
499 HW_VAR_MRC,
500 HW_VAR_KEEP_ALIVE,
501 HW_VAR_NAV_UPPER,
502
503 HW_VAR_MGT_FILTER,
504 HW_VAR_CTRL_FILTER,
505 HW_VAR_DATA_FILTER,
506 };
507
508 enum rt_media_status {
509 RT_MEDIA_DISCONNECT = 0,
510 RT_MEDIA_CONNECT = 1
511 };
512
513 enum rt_oem_id {
514 RT_CID_DEFAULT = 0,
515 RT_CID_8187_ALPHA0 = 1,
516 RT_CID_8187_SERCOMM_PS = 2,
517 RT_CID_8187_HW_LED = 3,
518 RT_CID_8187_NETGEAR = 4,
519 RT_CID_WHQL = 5,
520 RT_CID_819X_CAMEO = 6,
521 RT_CID_819X_RUNTOP = 7,
522 RT_CID_819X_SENAO = 8,
523 RT_CID_TOSHIBA = 9,
524 RT_CID_819X_NETCORE = 10,
525 RT_CID_NETTRONIX = 11,
526 RT_CID_DLINK = 12,
527 RT_CID_PRONET = 13,
528 RT_CID_COREGA = 14,
529 RT_CID_819X_ALPHA = 15,
530 RT_CID_819X_SITECOM = 16,
531 RT_CID_CCX = 17,
532 RT_CID_819X_LENOVO = 18,
533 RT_CID_819X_QMI = 19,
534 RT_CID_819X_EDIMAX_BELKIN = 20,
535 RT_CID_819X_SERCOMM_BELKIN = 21,
536 RT_CID_819X_CAMEO1 = 22,
537 RT_CID_819X_MSI = 23,
538 RT_CID_819X_ACER = 24,
539 RT_CID_819X_HP = 27,
540 RT_CID_819X_CLEVO = 28,
541 RT_CID_819X_ARCADYAN_BELKIN = 29,
542 RT_CID_819X_SAMSUNG = 30,
543 RT_CID_819X_WNC_COREGA = 31,
544 RT_CID_819X_FOXCOON = 32,
545 RT_CID_819X_DELL = 33,
546 RT_CID_819X_PRONETS = 34,
547 RT_CID_819X_EDIMAX_ASUS = 35,
548 RT_CID_NETGEAR = 36,
549 RT_CID_PLANEX = 37,
550 RT_CID_CC_C = 38,
551 };
552
553 enum hw_descs {
554 HW_DESC_OWN,
555 HW_DESC_RXOWN,
556 HW_DESC_TX_NEXTDESC_ADDR,
557 HW_DESC_TXBUFF_ADDR,
558 HW_DESC_RXBUFF_ADDR,
559 HW_DESC_RXPKT_LEN,
560 HW_DESC_RXERO,
561 HW_DESC_RX_PREPARE,
562 };
563
564 enum prime_sc {
565 PRIME_CHNL_OFFSET_DONT_CARE = 0,
566 PRIME_CHNL_OFFSET_LOWER = 1,
567 PRIME_CHNL_OFFSET_UPPER = 2,
568 };
569
570 enum rf_type {
571 RF_1T1R = 0,
572 RF_1T2R = 1,
573 RF_2T2R = 2,
574 RF_2T2R_GREEN = 3,
575 };
576
577 enum ht_channel_width {
578 HT_CHANNEL_WIDTH_20 = 0,
579 HT_CHANNEL_WIDTH_20_40 = 1,
580 HT_CHANNEL_WIDTH_80 = 2,
581 };
582
583 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
584 Cipher Suites Encryption Algorithms */
585 enum rt_enc_alg {
586 NO_ENCRYPTION = 0,
587 WEP40_ENCRYPTION = 1,
588 TKIP_ENCRYPTION = 2,
589 RSERVED_ENCRYPTION = 3,
590 AESCCMP_ENCRYPTION = 4,
591 WEP104_ENCRYPTION = 5,
592 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
593 };
594
595 enum rtl_hal_state {
596 _HAL_STATE_STOP = 0,
597 _HAL_STATE_START = 1,
598 };
599
600 enum rtl_desc92_rate {
601 DESC_RATE1M = 0x00,
602 DESC_RATE2M = 0x01,
603 DESC_RATE5_5M = 0x02,
604 DESC_RATE11M = 0x03,
605
606 DESC_RATE6M = 0x04,
607 DESC_RATE9M = 0x05,
608 DESC_RATE12M = 0x06,
609 DESC_RATE18M = 0x07,
610 DESC_RATE24M = 0x08,
611 DESC_RATE36M = 0x09,
612 DESC_RATE48M = 0x0a,
613 DESC_RATE54M = 0x0b,
614
615 DESC_RATEMCS0 = 0x0c,
616 DESC_RATEMCS1 = 0x0d,
617 DESC_RATEMCS2 = 0x0e,
618 DESC_RATEMCS3 = 0x0f,
619 DESC_RATEMCS4 = 0x10,
620 DESC_RATEMCS5 = 0x11,
621 DESC_RATEMCS6 = 0x12,
622 DESC_RATEMCS7 = 0x13,
623 DESC_RATEMCS8 = 0x14,
624 DESC_RATEMCS9 = 0x15,
625 DESC_RATEMCS10 = 0x16,
626 DESC_RATEMCS11 = 0x17,
627 DESC_RATEMCS12 = 0x18,
628 DESC_RATEMCS13 = 0x19,
629 DESC_RATEMCS14 = 0x1a,
630 DESC_RATEMCS15 = 0x1b,
631 DESC_RATEMCS15_SG = 0x1c,
632 DESC_RATEMCS32 = 0x20,
633
634 DESC_RATEVHT1SS_MCS0 = 0x2c,
635 DESC_RATEVHT1SS_MCS1 = 0x2d,
636 DESC_RATEVHT1SS_MCS2 = 0x2e,
637 DESC_RATEVHT1SS_MCS3 = 0x2f,
638 DESC_RATEVHT1SS_MCS4 = 0x30,
639 DESC_RATEVHT1SS_MCS5 = 0x31,
640 DESC_RATEVHT1SS_MCS6 = 0x32,
641 DESC_RATEVHT1SS_MCS7 = 0x33,
642 DESC_RATEVHT1SS_MCS8 = 0x34,
643 DESC_RATEVHT1SS_MCS9 = 0x35,
644 DESC_RATEVHT2SS_MCS0 = 0x36,
645 DESC_RATEVHT2SS_MCS1 = 0x37,
646 DESC_RATEVHT2SS_MCS2 = 0x38,
647 DESC_RATEVHT2SS_MCS3 = 0x39,
648 DESC_RATEVHT2SS_MCS4 = 0x3a,
649 DESC_RATEVHT2SS_MCS5 = 0x3b,
650 DESC_RATEVHT2SS_MCS6 = 0x3c,
651 DESC_RATEVHT2SS_MCS7 = 0x3d,
652 DESC_RATEVHT2SS_MCS8 = 0x3e,
653 DESC_RATEVHT2SS_MCS9 = 0x3f,
654 };
655
656 enum rtl_var_map {
657 /*reg map */
658 SYS_ISO_CTRL = 0,
659 SYS_FUNC_EN,
660 SYS_CLK,
661 MAC_RCR_AM,
662 MAC_RCR_AB,
663 MAC_RCR_ACRC32,
664 MAC_RCR_ACF,
665 MAC_RCR_AAP,
666 MAC_HIMR,
667 MAC_HIMRE,
668 MAC_HSISR,
669
670 /*efuse map */
671 EFUSE_TEST,
672 EFUSE_CTRL,
673 EFUSE_CLK,
674 EFUSE_CLK_CTRL,
675 EFUSE_PWC_EV12V,
676 EFUSE_FEN_ELDR,
677 EFUSE_LOADER_CLK_EN,
678 EFUSE_ANA8M,
679 EFUSE_HWSET_MAX_SIZE,
680 EFUSE_MAX_SECTION_MAP,
681 EFUSE_REAL_CONTENT_SIZE,
682 EFUSE_OOB_PROTECT_BYTES_LEN,
683 EFUSE_ACCESS,
684
685 /*CAM map */
686 RWCAM,
687 WCAMI,
688 RCAMO,
689 CAMDBG,
690 SECR,
691 SEC_CAM_NONE,
692 SEC_CAM_WEP40,
693 SEC_CAM_TKIP,
694 SEC_CAM_AES,
695 SEC_CAM_WEP104,
696
697 /*IMR map */
698 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
699 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
700 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
701 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
702 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
703 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
704 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
705 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
706 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
707 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
708 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
709 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
710 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
711 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
712 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
713 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
714 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
715 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
716 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
717 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
718 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
719 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
720 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
721 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
722 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
723 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
724 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
725 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
726 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
727 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
728 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
729 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
730 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
731 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
732 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
733 * RTL_IMR_TBDER) */
734 RTL_IMR_C2HCMD, /*fw interrupt*/
735
736 /*CCK Rates, TxHT = 0 */
737 RTL_RC_CCK_RATE1M,
738 RTL_RC_CCK_RATE2M,
739 RTL_RC_CCK_RATE5_5M,
740 RTL_RC_CCK_RATE11M,
741
742 /*OFDM Rates, TxHT = 0 */
743 RTL_RC_OFDM_RATE6M,
744 RTL_RC_OFDM_RATE9M,
745 RTL_RC_OFDM_RATE12M,
746 RTL_RC_OFDM_RATE18M,
747 RTL_RC_OFDM_RATE24M,
748 RTL_RC_OFDM_RATE36M,
749 RTL_RC_OFDM_RATE48M,
750 RTL_RC_OFDM_RATE54M,
751
752 RTL_RC_HT_RATEMCS7,
753 RTL_RC_HT_RATEMCS15,
754
755 RTL_RC_VHT_RATE_1SS_MCS7,
756 RTL_RC_VHT_RATE_1SS_MCS8,
757 RTL_RC_VHT_RATE_1SS_MCS9,
758 RTL_RC_VHT_RATE_2SS_MCS7,
759 RTL_RC_VHT_RATE_2SS_MCS8,
760 RTL_RC_VHT_RATE_2SS_MCS9,
761
762 /*keep it last */
763 RTL_VAR_MAP_MAX,
764 };
765
766 /*Firmware PS mode for control LPS.*/
767 enum _fw_ps_mode {
768 FW_PS_ACTIVE_MODE = 0,
769 FW_PS_MIN_MODE = 1,
770 FW_PS_MAX_MODE = 2,
771 FW_PS_DTIM_MODE = 3,
772 FW_PS_VOIP_MODE = 4,
773 FW_PS_UAPSD_WMM_MODE = 5,
774 FW_PS_UAPSD_MODE = 6,
775 FW_PS_IBSS_MODE = 7,
776 FW_PS_WWLAN_MODE = 8,
777 FW_PS_PM_Radio_Off = 9,
778 FW_PS_PM_Card_Disable = 10,
779 };
780
781 enum rt_psmode {
782 EACTIVE, /*Active/Continuous access. */
783 EMAXPS, /*Max power save mode. */
784 EFASTPS, /*Fast power save mode. */
785 EAUTOPS, /*Auto power save mode. */
786 };
787
788 /*LED related.*/
789 enum led_ctl_mode {
790 LED_CTL_POWER_ON = 1,
791 LED_CTL_LINK = 2,
792 LED_CTL_NO_LINK = 3,
793 LED_CTL_TX = 4,
794 LED_CTL_RX = 5,
795 LED_CTL_SITE_SURVEY = 6,
796 LED_CTL_POWER_OFF = 7,
797 LED_CTL_START_TO_LINK = 8,
798 LED_CTL_START_WPS = 9,
799 LED_CTL_STOP_WPS = 10,
800 };
801
802 enum rtl_led_pin {
803 LED_PIN_GPIO0,
804 LED_PIN_LED0,
805 LED_PIN_LED1,
806 LED_PIN_LED2
807 };
808
809 /*QoS related.*/
810 /*acm implementation method.*/
811 enum acm_method {
812 eAcmWay0_SwAndHw = 0,
813 eAcmWay1_HW = 1,
814 EACMWAY2_SW = 2,
815 };
816
817 enum macphy_mode {
818 SINGLEMAC_SINGLEPHY = 0,
819 DUALMAC_DUALPHY,
820 DUALMAC_SINGLEPHY,
821 };
822
823 enum band_type {
824 BAND_ON_2_4G = 0,
825 BAND_ON_5G,
826 BAND_ON_BOTH,
827 BANDMAX
828 };
829
830 /*aci/aifsn Field.
831 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
832 union aci_aifsn {
833 u8 char_data;
834
835 struct {
836 u8 aifsn:4;
837 u8 acm:1;
838 u8 aci:2;
839 u8 reserved:1;
840 } f; /* Field */
841 };
842
843 /*mlme related.*/
844 enum wireless_mode {
845 WIRELESS_MODE_UNKNOWN = 0x00,
846 WIRELESS_MODE_A = 0x01,
847 WIRELESS_MODE_B = 0x02,
848 WIRELESS_MODE_G = 0x04,
849 WIRELESS_MODE_AUTO = 0x08,
850 WIRELESS_MODE_N_24G = 0x10,
851 WIRELESS_MODE_N_5G = 0x20,
852 WIRELESS_MODE_AC_5G = 0x40,
853 WIRELESS_MODE_AC_24G = 0x80,
854 WIRELESS_MODE_AC_ONLY = 0x100,
855 WIRELESS_MODE_MAX = 0x800
856 };
857
858 #define IS_WIRELESS_MODE_A(wirelessmode) \
859 (wirelessmode == WIRELESS_MODE_A)
860 #define IS_WIRELESS_MODE_B(wirelessmode) \
861 (wirelessmode == WIRELESS_MODE_B)
862 #define IS_WIRELESS_MODE_G(wirelessmode) \
863 (wirelessmode == WIRELESS_MODE_G)
864 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
865 (wirelessmode == WIRELESS_MODE_N_24G)
866 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
867 (wirelessmode == WIRELESS_MODE_N_5G)
868
869 enum ratr_table_mode {
870 RATR_INX_WIRELESS_NGB = 0,
871 RATR_INX_WIRELESS_NG = 1,
872 RATR_INX_WIRELESS_NB = 2,
873 RATR_INX_WIRELESS_N = 3,
874 RATR_INX_WIRELESS_GB = 4,
875 RATR_INX_WIRELESS_G = 5,
876 RATR_INX_WIRELESS_B = 6,
877 RATR_INX_WIRELESS_MC = 7,
878 RATR_INX_WIRELESS_A = 8,
879 RATR_INX_WIRELESS_AC_5N = 8,
880 RATR_INX_WIRELESS_AC_24N = 9,
881 };
882
883 enum rtl_link_state {
884 MAC80211_NOLINK = 0,
885 MAC80211_LINKING = 1,
886 MAC80211_LINKED = 2,
887 MAC80211_LINKED_SCANNING = 3,
888 };
889
890 enum act_category {
891 ACT_CAT_QOS = 1,
892 ACT_CAT_DLS = 2,
893 ACT_CAT_BA = 3,
894 ACT_CAT_HT = 7,
895 ACT_CAT_WMM = 17,
896 };
897
898 enum ba_action {
899 ACT_ADDBAREQ = 0,
900 ACT_ADDBARSP = 1,
901 ACT_DELBA = 2,
902 };
903
904 enum rt_polarity_ctl {
905 RT_POLARITY_LOW_ACT = 0,
906 RT_POLARITY_HIGH_ACT = 1,
907 };
908
909 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
910 enum fw_wow_reason_v2 {
911 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
912 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
913 FW_WOW_V2_DISASSOC_EVENT = 0x04,
914 FW_WOW_V2_DEAUTH_EVENT = 0x08,
915 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
916 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
917 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
918 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
919 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
920 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
921 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
922 FW_WOW_V2_REASON_MAX = 0xff,
923 };
924
925 enum wolpattern_type {
926 UNICAST_PATTERN = 0,
927 MULTICAST_PATTERN = 1,
928 BROADCAST_PATTERN = 2,
929 DONT_CARE_DA = 3,
930 UNKNOWN_TYPE = 4,
931 };
932
933 struct octet_string {
934 u8 *octet;
935 u16 length;
936 };
937
938 struct rtl_hdr_3addr {
939 __le16 frame_ctl;
940 __le16 duration_id;
941 u8 addr1[ETH_ALEN];
942 u8 addr2[ETH_ALEN];
943 u8 addr3[ETH_ALEN];
944 __le16 seq_ctl;
945 u8 payload[0];
946 } __packed;
947
948 struct rtl_info_element {
949 u8 id;
950 u8 len;
951 u8 data[0];
952 } __packed;
953
954 struct rtl_probe_rsp {
955 struct rtl_hdr_3addr header;
956 u32 time_stamp[2];
957 __le16 beacon_interval;
958 __le16 capability;
959 /*SSID, supported rates, FH params, DS params,
960 CF params, IBSS params, TIM (if beacon), RSN */
961 struct rtl_info_element info_element[0];
962 } __packed;
963
964 /*LED related.*/
965 /*ledpin Identify how to implement this SW led.*/
966 struct rtl_led {
967 void *hw;
968 enum rtl_led_pin ledpin;
969 bool ledon;
970 };
971
972 struct rtl_led_ctl {
973 bool led_opendrain;
974 struct rtl_led sw_led0;
975 struct rtl_led sw_led1;
976 };
977
978 struct rtl_qos_parameters {
979 __le16 cw_min;
980 __le16 cw_max;
981 u8 aifs;
982 u8 flag;
983 __le16 tx_op;
984 } __packed;
985
986 struct rt_smooth_data {
987 u32 elements[100]; /*array to store values */
988 u32 index; /*index to current array to store */
989 u32 total_num; /*num of valid elements */
990 u32 total_val; /*sum of valid elements */
991 };
992
993 struct false_alarm_statistics {
994 u32 cnt_parity_fail;
995 u32 cnt_rate_illegal;
996 u32 cnt_crc8_fail;
997 u32 cnt_mcs_fail;
998 u32 cnt_fast_fsync_fail;
999 u32 cnt_sb_search_fail;
1000 u32 cnt_ofdm_fail;
1001 u32 cnt_cck_fail;
1002 u32 cnt_all;
1003 u32 cnt_ofdm_cca;
1004 u32 cnt_cck_cca;
1005 u32 cnt_cca_all;
1006 u32 cnt_bw_usc;
1007 u32 cnt_bw_lsc;
1008 };
1009
1010 struct init_gain {
1011 u8 xaagccore1;
1012 u8 xbagccore1;
1013 u8 xcagccore1;
1014 u8 xdagccore1;
1015 u8 cca;
1016
1017 };
1018
1019 struct wireless_stats {
1020 unsigned long txbytesunicast;
1021 unsigned long txbytesmulticast;
1022 unsigned long txbytesbroadcast;
1023 unsigned long rxbytesunicast;
1024
1025 long rx_snr_db[4];
1026 /*Correct smoothed ss in Dbm, only used
1027 in driver to report real power now. */
1028 long recv_signal_power;
1029 long signal_quality;
1030 long last_sigstrength_inpercent;
1031
1032 u32 rssi_calculate_cnt;
1033 u32 pwdb_all_cnt;
1034
1035 /*Transformed, in dbm. Beautified signal
1036 strength for UI, not correct. */
1037 long signal_strength;
1038
1039 u8 rx_rssi_percentage[4];
1040 u8 rx_evm_dbm[4];
1041 u8 rx_evm_percentage[2];
1042
1043 u16 rx_cfo_short[4];
1044 u16 rx_cfo_tail[4];
1045
1046 struct rt_smooth_data ui_rssi;
1047 struct rt_smooth_data ui_link_quality;
1048 };
1049
1050 struct rate_adaptive {
1051 u8 rate_adaptive_disabled;
1052 u8 ratr_state;
1053 u16 reserve;
1054
1055 u32 high_rssi_thresh_for_ra;
1056 u32 high2low_rssi_thresh_for_ra;
1057 u8 low2high_rssi_thresh_for_ra40m;
1058 u32 low_rssi_thresh_for_ra40m;
1059 u8 low2high_rssi_thresh_for_ra20m;
1060 u32 low_rssi_thresh_for_ra20m;
1061 u32 upper_rssi_threshold_ratr;
1062 u32 middleupper_rssi_threshold_ratr;
1063 u32 middle_rssi_threshold_ratr;
1064 u32 middlelow_rssi_threshold_ratr;
1065 u32 low_rssi_threshold_ratr;
1066 u32 ultralow_rssi_threshold_ratr;
1067 u32 low_rssi_threshold_ratr_40m;
1068 u32 low_rssi_threshold_ratr_20m;
1069 u8 ping_rssi_enable;
1070 u32 ping_rssi_ratr;
1071 u32 ping_rssi_thresh_for_ra;
1072 u32 last_ratr;
1073 u8 pre_ratr_state;
1074 u8 ldpc_thres;
1075 bool use_ldpc;
1076 bool lower_rts_rate;
1077 bool is_special_data;
1078 };
1079
1080 struct regd_pair_mapping {
1081 u16 reg_dmnenum;
1082 u16 reg_5ghz_ctl;
1083 u16 reg_2ghz_ctl;
1084 };
1085
1086 struct dynamic_primary_cca {
1087 u8 pricca_flag;
1088 u8 intf_flag;
1089 u8 intf_type;
1090 u8 dup_rts_flag;
1091 u8 monitor_flag;
1092 u8 ch_offset;
1093 u8 mf_state;
1094 };
1095
1096 struct rtl_regulatory {
1097 char alpha2[2];
1098 u16 country_code;
1099 u16 max_power_level;
1100 u32 tp_scale;
1101 u16 current_rd;
1102 u16 current_rd_ext;
1103 int16_t power_limit;
1104 struct regd_pair_mapping *regpair;
1105 };
1106
1107 struct rtl_rfkill {
1108 bool rfkill_state; /*0 is off, 1 is on */
1109 };
1110
1111 /*for P2P PS**/
1112 #define P2P_MAX_NOA_NUM 2
1113
1114 enum p2p_role {
1115 P2P_ROLE_DISABLE = 0,
1116 P2P_ROLE_DEVICE = 1,
1117 P2P_ROLE_CLIENT = 2,
1118 P2P_ROLE_GO = 3
1119 };
1120
1121 enum p2p_ps_state {
1122 P2P_PS_DISABLE = 0,
1123 P2P_PS_ENABLE = 1,
1124 P2P_PS_SCAN = 2,
1125 P2P_PS_SCAN_DONE = 3,
1126 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1127 };
1128
1129 enum p2p_ps_mode {
1130 P2P_PS_NONE = 0,
1131 P2P_PS_CTWINDOW = 1,
1132 P2P_PS_NOA = 2,
1133 P2P_PS_MIX = 3, /* CTWindow and NoA */
1134 };
1135
1136 struct rtl_p2p_ps_info {
1137 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1138 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1139 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1140 /* Client traffic window. A period of time in TU after TBTT. */
1141 u8 ctwindow;
1142 u8 opp_ps; /* opportunistic power save. */
1143 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1144 /* Count for owner, Type of client. */
1145 u8 noa_count_type[P2P_MAX_NOA_NUM];
1146 /* Max duration for owner, preferred or min acceptable duration
1147 * for client.
1148 */
1149 u32 noa_duration[P2P_MAX_NOA_NUM];
1150 /* Length of interval for owner, preferred or max acceptable intervali
1151 * of client.
1152 */
1153 u32 noa_interval[P2P_MAX_NOA_NUM];
1154 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1155 u32 noa_start_time[P2P_MAX_NOA_NUM];
1156 };
1157
1158 struct p2p_ps_offload_t {
1159 u8 offload_en:1;
1160 u8 role:1; /* 1: Owner, 0: Client */
1161 u8 ctwindow_en:1;
1162 u8 noa0_en:1;
1163 u8 noa1_en:1;
1164 u8 allstasleep:1;
1165 u8 discovery:1;
1166 u8 reserved:1;
1167 };
1168
1169 #define IQK_MATRIX_REG_NUM 8
1170 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1171
1172 struct iqk_matrix_regs {
1173 bool iqk_done;
1174 long value[1][IQK_MATRIX_REG_NUM];
1175 };
1176
1177 struct phy_parameters {
1178 u16 length;
1179 u32 *pdata;
1180 };
1181
1182 enum hw_param_tab_index {
1183 PHY_REG_2T,
1184 PHY_REG_1T,
1185 PHY_REG_PG,
1186 RADIOA_2T,
1187 RADIOB_2T,
1188 RADIOA_1T,
1189 RADIOB_1T,
1190 MAC_REG,
1191 AGCTAB_2T,
1192 AGCTAB_1T,
1193 MAX_TAB
1194 };
1195
1196 struct rtl_phy {
1197 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1198 struct init_gain initgain_backup;
1199 enum io_type current_io_type;
1200
1201 u8 rf_mode;
1202 u8 rf_type;
1203 u8 current_chan_bw;
1204 u8 set_bwmode_inprogress;
1205 u8 sw_chnl_inprogress;
1206 u8 sw_chnl_stage;
1207 u8 sw_chnl_step;
1208 u8 current_channel;
1209 u8 h2c_box_num;
1210 u8 set_io_inprogress;
1211 u8 lck_inprogress;
1212
1213 /* record for power tracking */
1214 s32 reg_e94;
1215 s32 reg_e9c;
1216 s32 reg_ea4;
1217 s32 reg_eac;
1218 s32 reg_eb4;
1219 s32 reg_ebc;
1220 s32 reg_ec4;
1221 s32 reg_ecc;
1222 u8 rfpienable;
1223 u8 reserve_0;
1224 u16 reserve_1;
1225 u32 reg_c04, reg_c08, reg_874;
1226 u32 adda_backup[16];
1227 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1228 u32 iqk_bb_backup[10];
1229 bool iqk_initialized;
1230
1231 bool rfpath_rx_enable[MAX_RF_PATH];
1232 u8 reg_837;
1233 /* Dual mac */
1234 bool need_iqk;
1235 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1236
1237 bool rfpi_enable;
1238 bool iqk_in_progress;
1239
1240 u8 pwrgroup_cnt;
1241 u8 cck_high_power;
1242 /* this is for 88E & 8723A */
1243 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1244 /* MAX_PG_GROUP groups of pwr diff by rates */
1245 u32 mcs_offset[MAX_PG_GROUP][16];
1246 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1247 [TX_PWR_BY_RATE_NUM_RF]
1248 [TX_PWR_BY_RATE_NUM_RF]
1249 [TX_PWR_BY_RATE_NUM_SECTION];
1250 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1251 [TX_PWR_BY_RATE_NUM_RF]
1252 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1253 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1254 [TX_PWR_BY_RATE_NUM_RF]
1255 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1256 u8 default_initialgain[4];
1257
1258 /* the current Tx power level */
1259 u8 cur_cck_txpwridx;
1260 u8 cur_ofdm24g_txpwridx;
1261 u8 cur_bw20_txpwridx;
1262 u8 cur_bw40_txpwridx;
1263
1264 char txpwr_limit_2_4g[MAX_REGULATION_NUM]
1265 [MAX_2_4G_BANDWITH_NUM]
1266 [MAX_RATE_SECTION_NUM]
1267 [CHANNEL_MAX_NUMBER_2G]
1268 [MAX_RF_PATH_NUM];
1269 char txpwr_limit_5g[MAX_REGULATION_NUM]
1270 [MAX_5G_BANDWITH_NUM]
1271 [MAX_RATE_SECTION_NUM]
1272 [CHANNEL_MAX_NUMBER_5G]
1273 [MAX_RF_PATH_NUM];
1274
1275 u32 rfreg_chnlval[2];
1276 bool apk_done;
1277 u32 reg_rf3c[2]; /* pathA / pathB */
1278
1279 u32 backup_rf_0x1a;/*92ee*/
1280 /* bfsync */
1281 u8 framesync;
1282 u32 framesync_c34;
1283
1284 u8 num_total_rfpath;
1285 struct phy_parameters hwparam_tables[MAX_TAB];
1286 u16 rf_pathmap;
1287
1288 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1289 enum rt_polarity_ctl polarity_ctl;
1290 };
1291
1292 #define MAX_TID_COUNT 9
1293 #define RTL_AGG_STOP 0
1294 #define RTL_AGG_PROGRESS 1
1295 #define RTL_AGG_START 2
1296 #define RTL_AGG_OPERATIONAL 3
1297 #define RTL_AGG_OFF 0
1298 #define RTL_AGG_ON 1
1299 #define RTL_RX_AGG_START 1
1300 #define RTL_RX_AGG_STOP 0
1301 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1302 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1303
1304 struct rtl_ht_agg {
1305 u16 txq_id;
1306 u16 wait_for_ba;
1307 u16 start_idx;
1308 u64 bitmap;
1309 u32 rate_n_flags;
1310 u8 agg_state;
1311 u8 rx_agg_state;
1312 };
1313
1314 struct rssi_sta {
1315 long undec_sm_pwdb;
1316 long undec_sm_cck;
1317 };
1318
1319 struct rtl_tid_data {
1320 u16 seq_number;
1321 struct rtl_ht_agg agg;
1322 };
1323
1324 struct rtl_sta_info {
1325 struct list_head list;
1326 u8 ratr_index;
1327 u8 wireless_mode;
1328 u8 mimo_ps;
1329 u8 mac_addr[ETH_ALEN];
1330 struct rtl_tid_data tids[MAX_TID_COUNT];
1331
1332 /* just used for ap adhoc or mesh*/
1333 struct rssi_sta rssi_stat;
1334 } __packed;
1335
1336 struct rtl_priv;
1337 struct rtl_io {
1338 struct device *dev;
1339 struct mutex bb_mutex;
1340
1341 /*PCI MEM map */
1342 unsigned long pci_mem_end; /*shared mem end */
1343 unsigned long pci_mem_start; /*shared mem start */
1344
1345 /*PCI IO map */
1346 unsigned long pci_base_addr; /*device I/O address */
1347
1348 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1349 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1350 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1351 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1352 u16 len);
1353
1354 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1355 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1356 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1357
1358 };
1359
1360 struct rtl_mac {
1361 u8 mac_addr[ETH_ALEN];
1362 u8 mac80211_registered;
1363 u8 beacon_enabled;
1364
1365 u32 tx_ss_num;
1366 u32 rx_ss_num;
1367
1368 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1369 struct ieee80211_hw *hw;
1370 struct ieee80211_vif *vif;
1371 enum nl80211_iftype opmode;
1372
1373 /*Probe Beacon management */
1374 struct rtl_tid_data tids[MAX_TID_COUNT];
1375 enum rtl_link_state link_state;
1376
1377 int n_channels;
1378 int n_bitrates;
1379
1380 bool offchan_delay;
1381 u8 p2p; /*using p2p role*/
1382 bool p2p_in_use;
1383
1384 /*filters */
1385 u32 rx_conf;
1386 u16 rx_mgt_filter;
1387 u16 rx_ctrl_filter;
1388 u16 rx_data_filter;
1389
1390 bool act_scanning;
1391 u8 cnt_after_linked;
1392 bool skip_scan;
1393
1394 /* early mode */
1395 /* skb wait queue */
1396 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1397
1398 u8 ht_stbc_cap;
1399 u8 ht_cur_stbc;
1400
1401 /*vht support*/
1402 u8 vht_enable;
1403 u8 bw_80;
1404 u8 vht_cur_ldpc;
1405 u8 vht_cur_stbc;
1406 u8 vht_stbc_cap;
1407 u8 vht_ldpc_cap;
1408
1409 /*RDG*/
1410 bool rdg_en;
1411
1412 /*AP*/
1413 u8 bssid[ETH_ALEN] __aligned(2);
1414 u32 vendor;
1415 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1416 u32 basic_rates; /* b/g rates */
1417 u8 ht_enable;
1418 u8 sgi_40;
1419 u8 sgi_20;
1420 u8 bw_40;
1421 u16 mode; /* wireless mode */
1422 u8 slot_time;
1423 u8 short_preamble;
1424 u8 use_cts_protect;
1425 u8 cur_40_prime_sc;
1426 u8 cur_40_prime_sc_bk;
1427 u8 cur_80_prime_sc;
1428 u64 tsf;
1429 u8 retry_short;
1430 u8 retry_long;
1431 u16 assoc_id;
1432 bool hiddenssid;
1433
1434 /*IBSS*/
1435 int beacon_interval;
1436
1437 /*AMPDU*/
1438 u8 min_space_cfg; /*For Min spacing configurations */
1439 u8 max_mss_density;
1440 u8 current_ampdu_factor;
1441 u8 current_ampdu_density;
1442
1443 /*QOS & EDCA */
1444 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1445 struct rtl_qos_parameters ac[AC_MAX];
1446
1447 /* counters */
1448 u64 last_txok_cnt;
1449 u64 last_rxok_cnt;
1450 u32 last_bt_edca_ul;
1451 u32 last_bt_edca_dl;
1452 };
1453
1454 struct btdm_8723 {
1455 bool all_off;
1456 bool agc_table_en;
1457 bool adc_back_off_on;
1458 bool b2_ant_hid_en;
1459 bool low_penalty_rate_adaptive;
1460 bool rf_rx_lpf_shrink;
1461 bool reject_aggre_pkt;
1462 bool tra_tdma_on;
1463 u8 tra_tdma_nav;
1464 u8 tra_tdma_ant;
1465 bool tdma_on;
1466 u8 tdma_ant;
1467 u8 tdma_nav;
1468 u8 tdma_dac_swing;
1469 u8 fw_dac_swing_lvl;
1470 bool ps_tdma_on;
1471 u8 ps_tdma_byte[5];
1472 bool pta_on;
1473 u32 val_0x6c0;
1474 u32 val_0x6c8;
1475 u32 val_0x6cc;
1476 bool sw_dac_swing_on;
1477 u32 sw_dac_swing_lvl;
1478 u32 wlan_act_hi;
1479 u32 wlan_act_lo;
1480 u32 bt_retry_index;
1481 bool dec_bt_pwr;
1482 bool ignore_wlan_act;
1483 };
1484
1485 struct bt_coexist_8723 {
1486 u32 high_priority_tx;
1487 u32 high_priority_rx;
1488 u32 low_priority_tx;
1489 u32 low_priority_rx;
1490 u8 c2h_bt_info;
1491 bool c2h_bt_info_req_sent;
1492 bool c2h_bt_inquiry_page;
1493 u32 bt_inq_page_start_time;
1494 u8 bt_retry_cnt;
1495 u8 c2h_bt_info_original;
1496 u8 bt_inquiry_page_cnt;
1497 struct btdm_8723 btdm;
1498 };
1499
1500 struct rtl_hal {
1501 struct ieee80211_hw *hw;
1502 bool driver_is_goingto_unload;
1503 bool up_first_time;
1504 bool first_init;
1505 bool being_init_adapter;
1506 bool bbrf_ready;
1507 bool mac_func_enable;
1508 bool pre_edcca_enable;
1509 struct bt_coexist_8723 hal_coex_8723;
1510
1511 enum intf_type interface;
1512 u16 hw_type; /*92c or 92d or 92s and so on */
1513 u8 ic_class;
1514 u8 oem_id;
1515 u32 version; /*version of chip */
1516 u8 state; /*stop 0, start 1 */
1517 u8 board_type;
1518 u8 external_pa;
1519
1520 u8 pa_mode;
1521 u8 pa_type_2g;
1522 u8 pa_type_5g;
1523 u8 lna_type_2g;
1524 u8 lna_type_5g;
1525 u8 external_pa_2g;
1526 u8 external_lna_2g;
1527 u8 external_pa_5g;
1528 u8 external_lna_5g;
1529 u8 rfe_type;
1530
1531 /*firmware */
1532 u32 fwsize;
1533 u8 *pfirmware;
1534 u16 fw_version;
1535 u16 fw_subversion;
1536 bool h2c_setinprogress;
1537 u8 last_hmeboxnum;
1538 bool fw_ready;
1539 /*Reserve page start offset except beacon in TxQ. */
1540 u8 fw_rsvdpage_startoffset;
1541 u8 h2c_txcmd_seq;
1542 u8 current_ra_rate;
1543
1544 /* FW Cmd IO related */
1545 u16 fwcmd_iomap;
1546 u32 fwcmd_ioparam;
1547 bool set_fwcmd_inprogress;
1548 u8 current_fwcmd_io;
1549
1550 struct p2p_ps_offload_t p2p_ps_offload;
1551 bool fw_clk_change_in_progress;
1552 bool allow_sw_to_change_hwclc;
1553 u8 fw_ps_state;
1554 /**/
1555 bool driver_going2unload;
1556
1557 /*AMPDU init min space*/
1558 u8 minspace_cfg; /*For Min spacing configurations */
1559
1560 /* Dual mac */
1561 enum macphy_mode macphymode;
1562 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1563 enum band_type current_bandtypebackup;
1564 enum band_type bandset;
1565 /* dual MAC 0--Mac0 1--Mac1 */
1566 u32 interfaceindex;
1567 /* just for DualMac S3S4 */
1568 u8 macphyctl_reg;
1569 bool earlymode_enable;
1570 u8 max_earlymode_num;
1571 /* Dual mac*/
1572 bool during_mac0init_radiob;
1573 bool during_mac1init_radioa;
1574 bool reloadtxpowerindex;
1575 /* True if IMR or IQK have done
1576 for 2.4G in scan progress */
1577 bool load_imrandiqk_setting_for2g;
1578
1579 bool disable_amsdu_8k;
1580 bool master_of_dmsp;
1581 bool slave_of_dmsp;
1582
1583 u16 rx_tag;/*for 92ee*/
1584 u8 rts_en;
1585
1586 /*for wowlan*/
1587 bool wow_enable;
1588 bool enter_pnp_sleep;
1589 bool wake_from_pnp_sleep;
1590 bool wow_enabled;
1591 __kernel_time_t last_suspend_sec;
1592 u32 wowlan_fwsize;
1593 u8 *wowlan_firmware;
1594
1595 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1596
1597 bool real_wow_v2_enable;
1598 bool re_init_llt_table;
1599 };
1600
1601 struct rtl_security {
1602 /*default 0 */
1603 bool use_sw_sec;
1604
1605 bool being_setkey;
1606 bool use_defaultkey;
1607 /*Encryption Algorithm for Unicast Packet */
1608 enum rt_enc_alg pairwise_enc_algorithm;
1609 /*Encryption Algorithm for Brocast/Multicast */
1610 enum rt_enc_alg group_enc_algorithm;
1611 /*Cam Entry Bitmap */
1612 u32 hwsec_cam_bitmap;
1613 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1614 /*local Key buffer, indx 0 is for
1615 pairwise key 1-4 is for agoup key. */
1616 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1617 u8 key_len[KEY_BUF_SIZE];
1618
1619 /*The pointer of Pairwise Key,
1620 it always points to KeyBuf[4] */
1621 u8 *pairwise_key;
1622 };
1623
1624 #define ASSOCIATE_ENTRY_NUM 33
1625
1626 struct fast_ant_training {
1627 u8 bssid[6];
1628 u8 antsel_rx_keep_0;
1629 u8 antsel_rx_keep_1;
1630 u8 antsel_rx_keep_2;
1631 u32 ant_sum[7];
1632 u32 ant_cnt[7];
1633 u32 ant_ave[7];
1634 u8 fat_state;
1635 u32 train_idx;
1636 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1637 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1638 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1639 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1640 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1641 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1642 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1643 u8 rx_idle_ant;
1644 bool becomelinked;
1645 };
1646
1647 struct dm_phy_dbg_info {
1648 char rx_snrdb[4];
1649 u64 num_qry_phy_status;
1650 u64 num_qry_phy_status_cck;
1651 u64 num_qry_phy_status_ofdm;
1652 u16 num_qry_beacon_pkt;
1653 u16 num_non_be_pkt;
1654 s32 rx_evm[4];
1655 };
1656
1657 struct rtl_dm {
1658 /*PHY status for Dynamic Management */
1659 long entry_min_undec_sm_pwdb;
1660 long undec_sm_cck;
1661 long undec_sm_pwdb; /*out dm */
1662 long entry_max_undec_sm_pwdb;
1663 s32 ofdm_pkt_cnt;
1664 bool dm_initialgain_enable;
1665 bool dynamic_txpower_enable;
1666 bool current_turbo_edca;
1667 bool is_any_nonbepkts; /*out dm */
1668 bool is_cur_rdlstate;
1669 bool txpower_trackinginit;
1670 bool disable_framebursting;
1671 bool cck_inch14;
1672 bool txpower_tracking;
1673 bool useramask;
1674 bool rfpath_rxenable[4];
1675 bool inform_fw_driverctrldm;
1676 bool current_mrc_switch;
1677 u8 txpowercount;
1678 u8 powerindex_backup[6];
1679
1680 u8 thermalvalue_rxgain;
1681 u8 thermalvalue_iqk;
1682 u8 thermalvalue_lck;
1683 u8 thermalvalue;
1684 u8 last_dtp_lvl;
1685 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1686 u8 thermalvalue_avg_index;
1687 u8 tm_trigger;
1688 bool done_txpower;
1689 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1690 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1691 u8 dm_flag_tmp;
1692 u8 dm_type;
1693 u8 dm_rssi_sel;
1694 u8 txpower_track_control;
1695 bool interrupt_migration;
1696 bool disable_tx_int;
1697 char ofdm_index[MAX_RF_PATH];
1698 u8 default_ofdm_index;
1699 u8 default_cck_index;
1700 char cck_index;
1701 char delta_power_index[MAX_RF_PATH];
1702 char delta_power_index_last[MAX_RF_PATH];
1703 char power_index_offset[MAX_RF_PATH];
1704 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1705 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1706 char remnant_cck_idx;
1707 bool modify_txagc_flag_path_a;
1708 bool modify_txagc_flag_path_b;
1709
1710 bool one_entry_only;
1711 struct dm_phy_dbg_info dbginfo;
1712
1713 /* Dynamic ATC switch */
1714 bool atc_status;
1715 bool large_cfo_hit;
1716 bool is_freeze;
1717 int cfo_tail[2];
1718 int cfo_ave_pre;
1719 int crystal_cap;
1720 u8 cfo_threshold;
1721 u32 packet_count;
1722 u32 packet_count_pre;
1723 u8 tx_rate;
1724
1725 /*88e tx power tracking*/
1726 u8 swing_idx_ofdm[MAX_RF_PATH];
1727 u8 swing_idx_ofdm_cur;
1728 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1729 bool swing_flag_ofdm;
1730 u8 swing_idx_cck;
1731 u8 swing_idx_cck_cur;
1732 u8 swing_idx_cck_base;
1733 bool swing_flag_cck;
1734
1735 char swing_diff_2g;
1736 char swing_diff_5g;
1737
1738 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1739 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1740 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1741 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1742 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1743 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1744 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1745 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1746 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1747 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1748 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1749 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1750 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1751 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1752
1753 /* DMSP */
1754 bool supp_phymode_switch;
1755
1756 /* DulMac */
1757 struct fast_ant_training fat_table;
1758
1759 u8 resp_tx_path;
1760 u8 path_sel;
1761 u32 patha_sum;
1762 u32 pathb_sum;
1763 u32 patha_cnt;
1764 u32 pathb_cnt;
1765
1766 u8 pre_channel;
1767 u8 *p_channel;
1768 u8 linked_interval;
1769
1770 u64 last_tx_ok_cnt;
1771 u64 last_rx_ok_cnt;
1772 };
1773
1774 #define EFUSE_MAX_LOGICAL_SIZE 512
1775
1776 struct rtl_efuse {
1777 bool autoLoad_ok;
1778 bool bootfromefuse;
1779 u16 max_physical_size;
1780
1781 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1782 u16 efuse_usedbytes;
1783 u8 efuse_usedpercentage;
1784 #ifdef EFUSE_REPG_WORKAROUND
1785 bool efuse_re_pg_sec1flag;
1786 u8 efuse_re_pg_data[8];
1787 #endif
1788
1789 u8 autoload_failflag;
1790 u8 autoload_status;
1791
1792 short epromtype;
1793 u16 eeprom_vid;
1794 u16 eeprom_did;
1795 u16 eeprom_svid;
1796 u16 eeprom_smid;
1797 u8 eeprom_oemid;
1798 u16 eeprom_channelplan;
1799 u8 eeprom_version;
1800 u8 board_type;
1801 u8 external_pa;
1802
1803 u8 dev_addr[6];
1804 u8 wowlan_enable;
1805 u8 antenna_div_cfg;
1806 u8 antenna_div_type;
1807
1808 bool txpwr_fromeprom;
1809 u8 eeprom_crystalcap;
1810 u8 eeprom_tssi[2];
1811 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1812 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1813 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1814 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1815 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1816 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1817
1818 u8 internal_pa_5g[2]; /* pathA / pathB */
1819 u8 eeprom_c9;
1820 u8 eeprom_cc;
1821
1822 /*For power group */
1823 u8 eeprom_pwrgroup[2][3];
1824 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1825 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1826
1827 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1828 /*For HT 40MHZ pwr */
1829 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1830 /*For HT 40MHZ pwr */
1831 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1832
1833 /*--------------------------------------------------------*
1834 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1835 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1836 * define new arrays in Windows code.
1837 * BUT, in linux code, we use the same array for all ICs.
1838 *
1839 * The Correspondance relation between two arrays is:
1840 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1841 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1842 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1843 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1844 *
1845 * Sizes of these arrays are decided by the larger ones.
1846 */
1847 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1848 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1849 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1850 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1851
1852 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1853 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1854 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1855 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1856 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1857 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1858
1859 u8 txpwr_safetyflag; /* Band edge enable flag */
1860 u16 eeprom_txpowerdiff;
1861 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1862 u8 antenna_txpwdiff[3];
1863
1864 u8 eeprom_regulatory;
1865 u8 eeprom_thermalmeter;
1866 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1867 u16 tssi_13dbm;
1868 u8 crystalcap; /* CrystalCap. */
1869 u8 delta_iqk;
1870 u8 delta_lck;
1871
1872 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1873 bool apk_thermalmeterignore;
1874
1875 bool b1x1_recvcombine;
1876 bool b1ss_support;
1877
1878 /*channel plan */
1879 u8 channel_plan;
1880 };
1881
1882 struct rtl_ps_ctl {
1883 bool pwrdomain_protect;
1884 bool in_powersavemode;
1885 bool rfchange_inprogress;
1886 bool swrf_processing;
1887 bool hwradiooff;
1888 /*
1889 * just for PCIE ASPM
1890 * If it supports ASPM, Offset[560h] = 0x40,
1891 * otherwise Offset[560h] = 0x00.
1892 * */
1893 bool support_aspm;
1894 bool support_backdoor;
1895
1896 /*for LPS */
1897 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1898 bool swctrl_lps;
1899 bool leisure_ps;
1900 bool fwctrl_lps;
1901 u8 fwctrl_psmode;
1902 /*For Fw control LPS mode */
1903 u8 reg_fwctrl_lps;
1904 /*Record Fw PS mode status. */
1905 bool fw_current_inpsmode;
1906 u8 reg_max_lps_awakeintvl;
1907 bool report_linked;
1908 bool low_power_enable;/*for 32k*/
1909
1910 /*for IPS */
1911 bool inactiveps;
1912
1913 u32 rfoff_reason;
1914
1915 /*RF OFF Level */
1916 u32 cur_ps_level;
1917 u32 reg_rfps_level;
1918
1919 /*just for PCIE ASPM */
1920 u8 const_amdpci_aspm;
1921 bool pwrdown_mode;
1922
1923 enum rf_pwrstate inactive_pwrstate;
1924 enum rf_pwrstate rfpwr_state; /*cur power state */
1925
1926 /* for SW LPS*/
1927 bool sw_ps_enabled;
1928 bool state;
1929 bool state_inap;
1930 bool multi_buffered;
1931 u16 nullfunc_seq;
1932 unsigned int dtim_counter;
1933 unsigned int sleep_ms;
1934 unsigned long last_sleep_jiffies;
1935 unsigned long last_awake_jiffies;
1936 unsigned long last_delaylps_stamp_jiffies;
1937 unsigned long last_dtim;
1938 unsigned long last_beacon;
1939 unsigned long last_action;
1940 unsigned long last_slept;
1941
1942 /*For P2P PS */
1943 struct rtl_p2p_ps_info p2p_ps_info;
1944 u8 pwr_mode;
1945 u8 smart_ps;
1946
1947 /* wake up on line */
1948 u8 wo_wlan_mode;
1949 u8 arp_offload_enable;
1950 u8 gtk_offload_enable;
1951 /* Used for WOL, indicates the reason for waking event.*/
1952 u32 wakeup_reason;
1953 /* Record the last waking time for comparison with setting key. */
1954 u64 last_wakeup_time;
1955 };
1956
1957 struct rtl_stats {
1958 u8 psaddr[ETH_ALEN];
1959 u32 mac_time[2];
1960 s8 rssi;
1961 u8 signal;
1962 u8 noise;
1963 u8 rate; /* hw desc rate */
1964 u8 received_channel;
1965 u8 control;
1966 u8 mask;
1967 u8 freq;
1968 u16 len;
1969 u64 tsf;
1970 u32 beacon_time;
1971 u8 nic_type;
1972 u16 length;
1973 u8 signalquality; /*in 0-100 index. */
1974 /*
1975 * Real power in dBm for this packet,
1976 * no beautification and aggregation.
1977 * */
1978 s32 recvsignalpower;
1979 s8 rxpower; /*in dBm Translate from PWdB */
1980 u8 signalstrength; /*in 0-100 index. */
1981 u16 hwerror:1;
1982 u16 crc:1;
1983 u16 icv:1;
1984 u16 shortpreamble:1;
1985 u16 antenna:1;
1986 u16 decrypted:1;
1987 u16 wakeup:1;
1988 u32 timestamp_low;
1989 u32 timestamp_high;
1990 bool shift;
1991
1992 u8 rx_drvinfo_size;
1993 u8 rx_bufshift;
1994 bool isampdu;
1995 bool isfirst_ampdu;
1996 bool rx_is40Mhzpacket;
1997 u8 rx_packet_bw;
1998 u32 rx_pwdb_all;
1999 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2000 s8 rx_mimo_signalquality[4];
2001 u8 rx_mimo_evm_dbm[4];
2002 u16 cfo_short[4]; /* per-path's Cfo_short */
2003 u16 cfo_tail[4];
2004
2005 s8 rx_mimo_sig_qual[4];
2006 u8 rx_pwr[4]; /* per-path's pwdb */
2007 u8 rx_snr[4]; /* per-path's SNR */
2008 u8 bandwidth;
2009 u8 bt_coex_pwr_adjust;
2010 bool packet_matchbssid;
2011 bool is_cck;
2012 bool is_ht;
2013 bool packet_toself;
2014 bool packet_beacon; /*for rssi */
2015 char cck_adc_pwdb[4]; /*for rx path selection */
2016
2017 bool is_vht;
2018 bool is_short_gi;
2019 u8 vht_nss;
2020
2021 u8 packet_report_type;
2022
2023 u32 macid;
2024 u8 wake_match;
2025 u32 bt_rx_rssi_percentage;
2026 u32 macid_valid_entry[2];
2027 };
2028
2029
2030 struct rt_link_detect {
2031 /* count for roaming */
2032 u32 bcn_rx_inperiod;
2033 u32 roam_times;
2034
2035 u32 num_tx_in4period[4];
2036 u32 num_rx_in4period[4];
2037
2038 u32 num_tx_inperiod;
2039 u32 num_rx_inperiod;
2040
2041 bool busytraffic;
2042 bool tx_busy_traffic;
2043 bool rx_busy_traffic;
2044 bool higher_busytraffic;
2045 bool higher_busyrxtraffic;
2046
2047 u32 tidtx_in4period[MAX_TID_COUNT][4];
2048 u32 tidtx_inperiod[MAX_TID_COUNT];
2049 bool higher_busytxtraffic[MAX_TID_COUNT];
2050 };
2051
2052 struct rtl_tcb_desc {
2053 u8 packet_bw:2;
2054 u8 multicast:1;
2055 u8 broadcast:1;
2056
2057 u8 rts_stbc:1;
2058 u8 rts_enable:1;
2059 u8 cts_enable:1;
2060 u8 rts_use_shortpreamble:1;
2061 u8 rts_use_shortgi:1;
2062 u8 rts_sc:1;
2063 u8 rts_bw:1;
2064 u8 rts_rate;
2065
2066 u8 use_shortgi:1;
2067 u8 use_shortpreamble:1;
2068 u8 use_driver_rate:1;
2069 u8 disable_ratefallback:1;
2070
2071 u8 ratr_index;
2072 u8 mac_id;
2073 u8 hw_rate;
2074
2075 u8 last_inipkt:1;
2076 u8 cmd_or_init:1;
2077 u8 queue_index;
2078
2079 /* early mode */
2080 u8 empkt_num;
2081 /* The max value by HW */
2082 u32 empkt_len[10];
2083 bool tx_enable_sw_calc_duration;
2084 };
2085
2086 struct rtl_wow_pattern {
2087 u8 type;
2088 u16 crc;
2089 u32 mask[4];
2090 };
2091
2092 struct rtl_hal_ops {
2093 int (*init_sw_vars) (struct ieee80211_hw *hw);
2094 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2095 void (*read_chip_version)(struct ieee80211_hw *hw);
2096 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2097 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2098 u32 *p_inta, u32 *p_intb);
2099 int (*hw_init) (struct ieee80211_hw *hw);
2100 void (*hw_disable) (struct ieee80211_hw *hw);
2101 void (*hw_suspend) (struct ieee80211_hw *hw);
2102 void (*hw_resume) (struct ieee80211_hw *hw);
2103 void (*enable_interrupt) (struct ieee80211_hw *hw);
2104 void (*disable_interrupt) (struct ieee80211_hw *hw);
2105 int (*set_network_type) (struct ieee80211_hw *hw,
2106 enum nl80211_iftype type);
2107 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2108 bool check_bssid);
2109 void (*set_bw_mode) (struct ieee80211_hw *hw,
2110 enum nl80211_channel_type ch_type);
2111 u8(*switch_channel) (struct ieee80211_hw *hw);
2112 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2113 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2114 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2115 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2116 u32 add_msr, u32 rm_msr);
2117 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2118 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2119 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2120 struct ieee80211_sta *sta, u8 rssi_level);
2121 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2122 u8 *desc, u8 queue_index,
2123 struct sk_buff *skb, dma_addr_t addr);
2124 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2125 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2126 u8 queue_index);
2127 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2128 u8 queue_index);
2129 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2130 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2131 u8 *pbd_desc_tx,
2132 struct ieee80211_tx_info *info,
2133 struct ieee80211_sta *sta,
2134 struct sk_buff *skb, u8 hw_queue,
2135 struct rtl_tcb_desc *ptcb_desc);
2136 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2137 u32 buffer_len, bool bIsPsPoll);
2138 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2139 bool firstseg, bool lastseg,
2140 struct sk_buff *skb);
2141 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2142 struct rtl_stats *stats,
2143 struct ieee80211_rx_status *rx_status,
2144 u8 *pdesc, struct sk_buff *skb);
2145 void (*set_channel_access) (struct ieee80211_hw *hw);
2146 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2147 void (*dm_watchdog) (struct ieee80211_hw *hw);
2148 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2149 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2150 enum rf_pwrstate rfpwr_state);
2151 void (*led_control) (struct ieee80211_hw *hw,
2152 enum led_ctl_mode ledaction);
2153 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2154 u8 desc_name, u8 *val);
2155 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2156 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2157 u8 hw_queue, u16 index);
2158 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2159 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2160 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2161 u8 *macaddr, bool is_group, u8 enc_algo,
2162 bool is_wepkey, bool clear_all);
2163 void (*init_sw_leds) (struct ieee80211_hw *hw);
2164 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2165 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2166 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2167 u32 data);
2168 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2169 u32 regaddr, u32 bitmask);
2170 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2171 u32 regaddr, u32 bitmask, u32 data);
2172 void (*linked_set_reg) (struct ieee80211_hw *hw);
2173 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2174 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2175 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2176 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2177 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2178 u8 *powerlevel);
2179 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2180 u8 *ppowerlevel, u8 channel);
2181 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2182 u8 configtype);
2183 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2184 u8 configtype);
2185 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2186 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2187 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2188 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2189 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2190 bool mstate);
2191 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2192 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2193 u32 cmd_len, u8 *p_cmdbuffer);
2194 bool (*get_btc_status) (void);
2195 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2196 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2197 struct rtl_stats status, struct sk_buff *skb);
2198 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2199 struct rtl_wow_pattern *rtl_pattern,
2200 u8 index);
2201 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2202 };
2203
2204 struct rtl_intf_ops {
2205 /*com */
2206 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2207 int (*adapter_start) (struct ieee80211_hw *hw);
2208 void (*adapter_stop) (struct ieee80211_hw *hw);
2209 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2210 struct rtl_priv **buddy_priv);
2211
2212 int (*adapter_tx) (struct ieee80211_hw *hw,
2213 struct ieee80211_sta *sta,
2214 struct sk_buff *skb,
2215 struct rtl_tcb_desc *ptcb_desc);
2216 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2217 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2218 bool (*waitq_insert) (struct ieee80211_hw *hw,
2219 struct ieee80211_sta *sta,
2220 struct sk_buff *skb);
2221
2222 /*pci */
2223 void (*disable_aspm) (struct ieee80211_hw *hw);
2224 void (*enable_aspm) (struct ieee80211_hw *hw);
2225
2226 /*usb */
2227 };
2228
2229 struct rtl_mod_params {
2230 /* default: 0 = using hardware encryption */
2231 bool sw_crypto;
2232
2233 /* default: 0 = DBG_EMERG (0)*/
2234 int debug;
2235
2236 /* default: 1 = using no linked power save */
2237 bool inactiveps;
2238
2239 /* default: 1 = using linked sw power save */
2240 bool swctrl_lps;
2241
2242 /* default: 1 = using linked fw power save */
2243 bool fwctrl_lps;
2244
2245 /* default: 0 = not using MSI interrupts mode
2246 * submodules should set their own default value
2247 */
2248 bool msi_support;
2249
2250 /* default 0: 1 means disable */
2251 bool disable_watchdog;
2252
2253 /* default 0: 1 means do not disable interrupts */
2254 bool int_clear;
2255 };
2256
2257 struct rtl_hal_usbint_cfg {
2258 /* data - rx */
2259 u32 in_ep_num;
2260 u32 rx_urb_num;
2261 u32 rx_max_size;
2262
2263 /* op - rx */
2264 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2265 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2266 struct sk_buff_head *);
2267
2268 /* tx */
2269 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2270 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2271 struct sk_buff *);
2272 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2273 struct sk_buff_head *);
2274
2275 /* endpoint mapping */
2276 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2277 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2278 };
2279
2280 struct rtl_hal_cfg {
2281 u8 bar_id;
2282 bool write_readback;
2283 char *name;
2284 char *fw_name;
2285 char *alt_fw_name;
2286 char *wowlan_fw_name;
2287 struct rtl_hal_ops *ops;
2288 struct rtl_mod_params *mod_params;
2289 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2290
2291 /*this map used for some registers or vars
2292 defined int HAL but used in MAIN */
2293 u32 maps[RTL_VAR_MAP_MAX];
2294
2295 };
2296
2297 struct rtl_locks {
2298 /* mutex */
2299 struct mutex conf_mutex;
2300 struct mutex ps_mutex;
2301
2302 /*spin lock */
2303 spinlock_t ips_lock;
2304 spinlock_t irq_th_lock;
2305 spinlock_t irq_pci_lock;
2306 spinlock_t tx_lock;
2307 spinlock_t h2c_lock;
2308 spinlock_t rf_ps_lock;
2309 spinlock_t rf_lock;
2310 spinlock_t lps_lock;
2311 spinlock_t waitq_lock;
2312 spinlock_t entry_list_lock;
2313 spinlock_t usb_lock;
2314
2315 /*FW clock change */
2316 spinlock_t fw_ps_lock;
2317
2318 /*Dual mac*/
2319 spinlock_t cck_and_rw_pagea_lock;
2320
2321 /*Easy concurrent*/
2322 spinlock_t check_sendpkt_lock;
2323
2324 spinlock_t iqk_lock;
2325 };
2326
2327 struct rtl_works {
2328 struct ieee80211_hw *hw;
2329
2330 /*timer */
2331 struct timer_list watchdog_timer;
2332 struct timer_list dualmac_easyconcurrent_retrytimer;
2333 struct timer_list fw_clockoff_timer;
2334 struct timer_list fast_antenna_training_timer;
2335 /*task */
2336 struct tasklet_struct irq_tasklet;
2337 struct tasklet_struct irq_prepare_bcn_tasklet;
2338
2339 /*work queue */
2340 struct workqueue_struct *rtl_wq;
2341 struct delayed_work watchdog_wq;
2342 struct delayed_work ips_nic_off_wq;
2343
2344 /* For SW LPS */
2345 struct delayed_work ps_work;
2346 struct delayed_work ps_rfon_wq;
2347 struct delayed_work fwevt_wq;
2348
2349 struct work_struct lps_change_work;
2350 struct work_struct fill_h2c_cmd;
2351 };
2352
2353 struct rtl_debug {
2354 u32 dbgp_type[DBGP_TYPE_MAX];
2355 int global_debuglevel;
2356 u64 global_debugcomponents;
2357
2358 /* add for proc debug */
2359 struct proc_dir_entry *proc_dir;
2360 char proc_name[20];
2361 };
2362
2363 #define MIMO_PS_STATIC 0
2364 #define MIMO_PS_DYNAMIC 1
2365 #define MIMO_PS_NOLIMIT 3
2366
2367 struct rtl_dualmac_easy_concurrent_ctl {
2368 enum band_type currentbandtype_backfordmdp;
2369 bool close_bbandrf_for_dmsp;
2370 bool change_to_dmdp;
2371 bool change_to_dmsp;
2372 bool switch_in_process;
2373 };
2374
2375 struct rtl_dmsp_ctl {
2376 bool activescan_for_slaveofdmsp;
2377 bool scan_for_anothermac_fordmsp;
2378 bool scan_for_itself_fordmsp;
2379 bool writedig_for_anothermacofdmsp;
2380 u32 curdigvalue_for_anothermacofdmsp;
2381 bool changecckpdstate_for_anothermacofdmsp;
2382 u8 curcckpdstate_for_anothermacofdmsp;
2383 bool changetxhighpowerlvl_for_anothermacofdmsp;
2384 u8 curtxhighlvl_for_anothermacofdmsp;
2385 long rssivalmin_for_anothermacofdmsp;
2386 };
2387
2388 struct ps_t {
2389 u8 pre_ccastate;
2390 u8 cur_ccasate;
2391 u8 pre_rfstate;
2392 u8 cur_rfstate;
2393 u8 initialize;
2394 long rssi_val_min;
2395 };
2396
2397 struct dig_t {
2398 u32 rssi_lowthresh;
2399 u32 rssi_highthresh;
2400 u32 fa_lowthresh;
2401 u32 fa_highthresh;
2402 long last_min_undec_pwdb_for_dm;
2403 long rssi_highpower_lowthresh;
2404 long rssi_highpower_highthresh;
2405 u32 recover_cnt;
2406 u32 pre_igvalue;
2407 u32 cur_igvalue;
2408 long rssi_val;
2409 u8 dig_enable_flag;
2410 u8 dig_ext_port_stage;
2411 u8 dig_algorithm;
2412 u8 dig_twoport_algorithm;
2413 u8 dig_dbgmode;
2414 u8 dig_slgorithm_switch;
2415 u8 cursta_cstate;
2416 u8 presta_cstate;
2417 u8 curmultista_cstate;
2418 u8 stop_dig;
2419 char back_val;
2420 char back_range_max;
2421 char back_range_min;
2422 u8 rx_gain_max;
2423 u8 rx_gain_min;
2424 u8 min_undec_pwdb_for_dm;
2425 u8 rssi_val_min;
2426 u8 pre_cck_cca_thres;
2427 u8 cur_cck_cca_thres;
2428 u8 pre_cck_pd_state;
2429 u8 cur_cck_pd_state;
2430 u8 pre_cck_fa_state;
2431 u8 cur_cck_fa_state;
2432 u8 pre_ccastate;
2433 u8 cur_ccasate;
2434 u8 large_fa_hit;
2435 u8 forbidden_igi;
2436 u8 dig_state;
2437 u8 dig_highpwrstate;
2438 u8 cur_sta_cstate;
2439 u8 pre_sta_cstate;
2440 u8 cur_ap_cstate;
2441 u8 pre_ap_cstate;
2442 u8 cur_pd_thstate;
2443 u8 pre_pd_thstate;
2444 u8 cur_cs_ratiostate;
2445 u8 pre_cs_ratiostate;
2446 u8 backoff_enable_flag;
2447 char backoffval_range_max;
2448 char backoffval_range_min;
2449 u8 dig_min_0;
2450 u8 dig_min_1;
2451 u8 bt30_cur_igi;
2452 bool media_connect_0;
2453 bool media_connect_1;
2454
2455 u32 antdiv_rssi_max;
2456 u32 rssi_max;
2457 };
2458
2459 struct rtl_global_var {
2460 /* from this list we can get
2461 * other adapter's rtl_priv */
2462 struct list_head glb_priv_list;
2463 spinlock_t glb_list_lock;
2464 };
2465
2466 struct rtl_btc_info {
2467 u8 bt_type;
2468 u8 btcoexist;
2469 u8 ant_num;
2470 };
2471
2472 struct bt_coexist_info {
2473 struct rtl_btc_ops *btc_ops;
2474 struct rtl_btc_info btc_info;
2475 /* EEPROM BT info. */
2476 u8 eeprom_bt_coexist;
2477 u8 eeprom_bt_type;
2478 u8 eeprom_bt_ant_num;
2479 u8 eeprom_bt_ant_isol;
2480 u8 eeprom_bt_radio_shared;
2481
2482 u8 bt_coexistence;
2483 u8 bt_ant_num;
2484 u8 bt_coexist_type;
2485 u8 bt_state;
2486 u8 bt_cur_state; /* 0:on, 1:off */
2487 u8 bt_ant_isolation; /* 0:good, 1:bad */
2488 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2489 u8 bt_service;
2490 u8 bt_radio_shared_type;
2491 u8 bt_rfreg_origin_1e;
2492 u8 bt_rfreg_origin_1f;
2493 u8 bt_rssi_state;
2494 u32 ratio_tx;
2495 u32 ratio_pri;
2496 u32 bt_edca_ul;
2497 u32 bt_edca_dl;
2498
2499 bool init_set;
2500 bool bt_busy_traffic;
2501 bool bt_traffic_mode_set;
2502 bool bt_non_traffic_mode_set;
2503
2504 bool fw_coexist_all_off;
2505 bool sw_coexist_all_off;
2506 bool hw_coexist_all_off;
2507 u32 cstate;
2508 u32 previous_state;
2509 u32 cstate_h;
2510 u32 previous_state_h;
2511
2512 u8 bt_pre_rssi_state;
2513 u8 bt_pre_rssi_state1;
2514
2515 u8 reg_bt_iso;
2516 u8 reg_bt_sco;
2517 bool balance_on;
2518 u8 bt_active_zero_cnt;
2519 bool cur_bt_disabled;
2520 bool pre_bt_disabled;
2521
2522 u8 bt_profile_case;
2523 u8 bt_profile_action;
2524 bool bt_busy;
2525 bool hold_for_bt_operation;
2526 u8 lps_counter;
2527 };
2528
2529 struct rtl_btc_ops {
2530 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2531 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2532 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2533 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2534 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2535 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2536 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2537 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2538 enum rt_media_status mstatus);
2539 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2540 void (*btc_halt_notify) (void);
2541 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2542 u8 *tmp_buf, u8 length);
2543 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2544 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2545 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2546 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2547 u8 pkt_type);
2548 };
2549
2550 struct proxim {
2551 bool proxim_on;
2552
2553 void *proximity_priv;
2554 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2555 struct sk_buff *skb);
2556 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2557 };
2558
2559 struct rtl_priv {
2560 struct ieee80211_hw *hw;
2561 struct completion firmware_loading_complete;
2562 struct list_head list;
2563 struct rtl_priv *buddy_priv;
2564 struct rtl_global_var *glb_var;
2565 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2566 struct rtl_dmsp_ctl dmsp_ctl;
2567 struct rtl_locks locks;
2568 struct rtl_works works;
2569 struct rtl_mac mac80211;
2570 struct rtl_hal rtlhal;
2571 struct rtl_regulatory regd;
2572 struct rtl_rfkill rfkill;
2573 struct rtl_io io;
2574 struct rtl_phy phy;
2575 struct rtl_dm dm;
2576 struct rtl_security sec;
2577 struct rtl_efuse efuse;
2578
2579 struct rtl_ps_ctl psc;
2580 struct rate_adaptive ra;
2581 struct dynamic_primary_cca primarycca;
2582 struct wireless_stats stats;
2583 struct rt_link_detect link_info;
2584 struct false_alarm_statistics falsealm_cnt;
2585
2586 struct rtl_rate_priv *rate_priv;
2587
2588 /* sta entry list for ap adhoc or mesh */
2589 struct list_head entry_list;
2590
2591 struct rtl_debug dbg;
2592 int max_fw_size;
2593
2594 /*
2595 *hal_cfg : for diff cards
2596 *intf_ops : for diff interrface usb/pcie
2597 */
2598 struct rtl_hal_cfg *cfg;
2599 struct rtl_intf_ops *intf_ops;
2600
2601 /*this var will be set by set_bit,
2602 and was used to indicate status of
2603 interface or hardware */
2604 unsigned long status;
2605
2606 /* tables for dm */
2607 struct dig_t dm_digtable;
2608 struct ps_t dm_pstable;
2609
2610 u32 reg_874;
2611 u32 reg_c70;
2612 u32 reg_85c;
2613 u32 reg_a74;
2614 bool reg_init; /* true if regs saved */
2615 bool bt_operation_on;
2616 __le32 *usb_data;
2617 int usb_data_index;
2618 bool initialized;
2619 bool enter_ps; /* true when entering PS */
2620 u8 rate_mask[5];
2621
2622 /* intel Proximity, should be alloc mem
2623 * in intel Proximity module and can only
2624 * be used in intel Proximity mode
2625 */
2626 struct proxim proximity;
2627
2628 /*for bt coexist use*/
2629 struct bt_coexist_info btcoexist;
2630
2631 /* separate 92ee from other ICs,
2632 * 92ee use new trx flow.
2633 */
2634 bool use_new_trx_flow;
2635
2636 #ifdef CONFIG_PM
2637 struct wiphy_wowlan_support wowlan;
2638 #endif
2639 /*This must be the last item so
2640 that it points to the data allocated
2641 beyond this structure like:
2642 rtl_pci_priv or rtl_usb_priv */
2643 u8 priv[0] __aligned(sizeof(void *));
2644 };
2645
2646 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2647 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2648 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2649 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2650 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2651
2652
2653 /***************************************
2654 Bluetooth Co-existence Related
2655 ****************************************/
2656
2657 enum bt_ant_num {
2658 ANT_X2 = 0,
2659 ANT_X1 = 1,
2660 };
2661
2662 enum bt_co_type {
2663 BT_2WIRE = 0,
2664 BT_ISSC_3WIRE = 1,
2665 BT_ACCEL = 2,
2666 BT_CSR_BC4 = 3,
2667 BT_CSR_BC8 = 4,
2668 BT_RTL8756 = 5,
2669 BT_RTL8723A = 6,
2670 BT_RTL8821A = 7,
2671 BT_RTL8723B = 8,
2672 BT_RTL8192E = 9,
2673 BT_RTL8812A = 11,
2674 };
2675
2676 enum bt_total_ant_num {
2677 ANT_TOTAL_X2 = 0,
2678 ANT_TOTAL_X1 = 1
2679 };
2680
2681 enum bt_cur_state {
2682 BT_OFF = 0,
2683 BT_ON = 1,
2684 };
2685
2686 enum bt_service_type {
2687 BT_SCO = 0,
2688 BT_A2DP = 1,
2689 BT_HID = 2,
2690 BT_HID_IDLE = 3,
2691 BT_SCAN = 4,
2692 BT_IDLE = 5,
2693 BT_OTHER_ACTION = 6,
2694 BT_BUSY = 7,
2695 BT_OTHERBUSY = 8,
2696 BT_PAN = 9,
2697 };
2698
2699 enum bt_radio_shared {
2700 BT_RADIO_SHARED = 0,
2701 BT_RADIO_INDIVIDUAL = 1,
2702 };
2703
2704
2705 /****************************************
2706 mem access macro define start
2707 Call endian free function when
2708 1. Read/write packet content.
2709 2. Before write integer to IO.
2710 3. After read integer from IO.
2711 ****************************************/
2712 /* Convert little data endian to host ordering */
2713 #define EF1BYTE(_val) \
2714 ((u8)(_val))
2715 #define EF2BYTE(_val) \
2716 (le16_to_cpu(_val))
2717 #define EF4BYTE(_val) \
2718 (le32_to_cpu(_val))
2719
2720 /* Read data from memory */
2721 #define READEF1BYTE(_ptr) \
2722 EF1BYTE(*((u8 *)(_ptr)))
2723 /* Read le16 data from memory and convert to host ordering */
2724 #define READEF2BYTE(_ptr) \
2725 EF2BYTE(*(_ptr))
2726 #define READEF4BYTE(_ptr) \
2727 EF4BYTE(*(_ptr))
2728
2729 /* Write data to memory */
2730 #define WRITEEF1BYTE(_ptr, _val) \
2731 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2732 /* Write le16 data to memory in host ordering */
2733 #define WRITEEF2BYTE(_ptr, _val) \
2734 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2735 #define WRITEEF4BYTE(_ptr, _val) \
2736 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2737
2738 /* Create a bit mask
2739 * Examples:
2740 * BIT_LEN_MASK_32(0) => 0x00000000
2741 * BIT_LEN_MASK_32(1) => 0x00000001
2742 * BIT_LEN_MASK_32(2) => 0x00000003
2743 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2744 */
2745 #define BIT_LEN_MASK_32(__bitlen) \
2746 (0xFFFFFFFF >> (32 - (__bitlen)))
2747 #define BIT_LEN_MASK_16(__bitlen) \
2748 (0xFFFF >> (16 - (__bitlen)))
2749 #define BIT_LEN_MASK_8(__bitlen) \
2750 (0xFF >> (8 - (__bitlen)))
2751
2752 /* Create an offset bit mask
2753 * Examples:
2754 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2755 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2756 */
2757 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2758 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2759 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2760 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2761 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2762 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2763
2764 /*Description:
2765 * Return 4-byte value in host byte ordering from
2766 * 4-byte pointer in little-endian system.
2767 */
2768 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2769 (EF4BYTE(*((__le32 *)(__pstart))))
2770 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2771 (EF2BYTE(*((__le16 *)(__pstart))))
2772 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2773 (EF1BYTE(*((u8 *)(__pstart))))
2774
2775 /*Description:
2776 Translate subfield (continuous bits in little-endian) of 4-byte
2777 value to host byte ordering.*/
2778 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2779 ( \
2780 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2781 BIT_LEN_MASK_32(__bitlen) \
2782 )
2783 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2784 ( \
2785 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2786 BIT_LEN_MASK_16(__bitlen) \
2787 )
2788 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2789 ( \
2790 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2791 BIT_LEN_MASK_8(__bitlen) \
2792 )
2793
2794 /* Description:
2795 * Mask subfield (continuous bits in little-endian) of 4-byte value
2796 * and return the result in 4-byte value in host byte ordering.
2797 */
2798 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2799 ( \
2800 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2801 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2802 )
2803 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2804 ( \
2805 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2806 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2807 )
2808 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2809 ( \
2810 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2811 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2812 )
2813
2814 /* Description:
2815 * Set subfield of little-endian 4-byte value to specified value.
2816 */
2817 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2818 *((u32 *)(__pstart)) = \
2819 ( \
2820 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2821 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2822 );
2823 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2824 *((u16 *)(__pstart)) = \
2825 ( \
2826 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2827 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2828 );
2829 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2830 *((u8 *)(__pstart)) = EF1BYTE \
2831 ( \
2832 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2833 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2834 );
2835
2836 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2837 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2838
2839 /****************************************
2840 mem access macro define end
2841 ****************************************/
2842
2843 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2844
2845 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2846 #define RTL_WATCH_DOG_TIME 2000
2847 #define MSECS(t) msecs_to_jiffies(t)
2848 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2849 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2850 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2851 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2852 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2853
2854 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2855 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2856 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2857 /*NIC halt, re-initialize hw parameters*/
2858 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2859 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2860 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2861 /*Always enable ASPM and Clock Req in initialization.*/
2862 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2863 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2864 #define RT_PS_LEVEL_ASPM BIT(7)
2865 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2866 #define RT_RF_LPS_DISALBE_2R BIT(30)
2867 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2868 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2869 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2870 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2871 (ppsc->cur_ps_level &= (~(_ps_flg)))
2872 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2873 (ppsc->cur_ps_level |= _ps_flg)
2874
2875 #define container_of_dwork_rtl(x, y, z) \
2876 container_of(container_of(x, struct delayed_work, work), y, z)
2877
2878 #define FILL_OCTET_STRING(_os, _octet, _len) \
2879 (_os).octet = (u8 *)(_octet); \
2880 (_os).length = (_len);
2881
2882 #define CP_MACADDR(des, src) \
2883 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2884 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2885 (des)[4] = (src)[4], (des)[5] = (src)[5])
2886
2887 #define LDPC_HT_ENABLE_RX BIT(0)
2888 #define LDPC_HT_ENABLE_TX BIT(1)
2889 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2890 #define LDPC_HT_CAP_TX BIT(3)
2891
2892 #define STBC_HT_ENABLE_RX BIT(0)
2893 #define STBC_HT_ENABLE_TX BIT(1)
2894 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2895 #define STBC_HT_CAP_TX BIT(3)
2896
2897 #define LDPC_VHT_ENABLE_RX BIT(0)
2898 #define LDPC_VHT_ENABLE_TX BIT(1)
2899 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2900 #define LDPC_VHT_CAP_TX BIT(3)
2901
2902 #define STBC_VHT_ENABLE_RX BIT(0)
2903 #define STBC_VHT_ENABLE_TX BIT(1)
2904 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2905 #define STBC_VHT_CAP_TX BIT(3)
2906
2907 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2908 {
2909 return rtlpriv->io.read8_sync(rtlpriv, addr);
2910 }
2911
2912 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2913 {
2914 return rtlpriv->io.read16_sync(rtlpriv, addr);
2915 }
2916
2917 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2918 {
2919 return rtlpriv->io.read32_sync(rtlpriv, addr);
2920 }
2921
2922 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2923 {
2924 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2925
2926 if (rtlpriv->cfg->write_readback)
2927 rtlpriv->io.read8_sync(rtlpriv, addr);
2928 }
2929
2930 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2931 {
2932 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2933
2934 if (rtlpriv->cfg->write_readback)
2935 rtlpriv->io.read16_sync(rtlpriv, addr);
2936 }
2937
2938 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2939 u32 addr, u32 val32)
2940 {
2941 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2942
2943 if (rtlpriv->cfg->write_readback)
2944 rtlpriv->io.read32_sync(rtlpriv, addr);
2945 }
2946
2947 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2948 u32 regaddr, u32 bitmask)
2949 {
2950 struct rtl_priv *rtlpriv = hw->priv;
2951
2952 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2953 }
2954
2955 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2956 u32 bitmask, u32 data)
2957 {
2958 struct rtl_priv *rtlpriv = hw->priv;
2959
2960 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2961 }
2962
2963 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2964 enum radio_path rfpath, u32 regaddr,
2965 u32 bitmask)
2966 {
2967 struct rtl_priv *rtlpriv = hw->priv;
2968
2969 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2970 }
2971
2972 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2973 enum radio_path rfpath, u32 regaddr,
2974 u32 bitmask, u32 data)
2975 {
2976 struct rtl_priv *rtlpriv = hw->priv;
2977
2978 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2979 }
2980
2981 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2982 {
2983 return (_HAL_STATE_STOP == rtlhal->state);
2984 }
2985
2986 static inline void set_hal_start(struct rtl_hal *rtlhal)
2987 {
2988 rtlhal->state = _HAL_STATE_START;
2989 }
2990
2991 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2992 {
2993 rtlhal->state = _HAL_STATE_STOP;
2994 }
2995
2996 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2997 {
2998 return rtlphy->rf_type;
2999 }
3000
3001 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3002 {
3003 return (struct ieee80211_hdr *)(skb->data);
3004 }
3005
3006 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3007 {
3008 return rtl_get_hdr(skb)->frame_control;
3009 }
3010
3011 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3012 {
3013 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3014 }
3015
3016 static inline u16 rtl_get_tid(struct sk_buff *skb)
3017 {
3018 return rtl_get_tid_h(rtl_get_hdr(skb));
3019 }
3020
3021 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3022 struct ieee80211_vif *vif,
3023 const u8 *bssid)
3024 {
3025 return ieee80211_find_sta(vif, bssid);
3026 }
3027
3028 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3029 u8 *mac_addr)
3030 {
3031 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3032 return ieee80211_find_sta(mac->vif, mac_addr);
3033 }
3034
3035 #endif 1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Created on 2010/ 5/18, 1:41
23 *
24 * Larry Finger <Larry.Finger@lwfinger.net>
25 *
26 *****************************************************************************/
27
28 #ifndef __RTL92CE_TABLE__H_
29 #define __RTL92CE_TABLE__H_
30
31 #include <linux/types.h>
32 #define RTL8188EEPHY_REG_1TARRAYLEN 382
33 extern u32 RTL8188EEPHY_REG_1TARRAY[];
34 #define RTL8188EEPHY_REG_ARRAY_PGLEN 264
35 extern u32 RTL8188EEPHY_REG_ARRAY_PG[];
36 #define RTL8188EE_RADIOA_1TARRAYLEN 190
37 extern u32 RTL8188EE_RADIOA_1TARRAY[];
38 #define RTL8188EEMAC_1T_ARRAYLEN 180
39 extern u32 RTL8188EEMAC_1T_ARRAY[];
40 #define RTL8188EEAGCTAB_1TARRAYLEN 256
41 extern u32 RTL8188EEAGCTAB_1TARRAY[];
42
43 #endif 1 #ifndef _LDV_RCV_H_
2 #define _LDV_RCV_H_
3
4 /* If expr evaluates to zero, ldv_assert() causes a program to reach the error
5 label like the standard assert(). */
6 #define ldv_assert(expr) ((expr) ? 0 : ldv_error())
7
8 /* The error label wrapper. It is used because of some static verifiers (like
9 BLAST) don't accept multiple error labels through a program. */
10 static inline void ldv_error(void)
11 {
12 LDV_ERROR: goto LDV_ERROR;
13 }
14
15 /* If expr evaluates to zero, ldv_assume() causes an infinite loop that is
16 avoided by verifiers. */
17 #define ldv_assume(expr) ((expr) ? 0 : ldv_stop())
18
19 /* Infinite loop, that causes verifiers to skip such paths. */
20 static inline void ldv_stop(void) {
21 LDV_STOP: goto LDV_STOP;
22 }
23
24 /* Special nondeterministic functions. */
25 int ldv_undef_int(void);
26 void *ldv_undef_ptr(void);
27 unsigned long ldv_undef_ulong(void);
28 long ldv_undef_long(void);
29 /* Return nondeterministic negative integer number. */
30 static inline int ldv_undef_int_negative(void)
31 {
32 int ret = ldv_undef_int();
33
34 ldv_assume(ret < 0);
35
36 return ret;
37 }
38 /* Return nondeterministic nonpositive integer number. */
39 static inline int ldv_undef_int_nonpositive(void)
40 {
41 int ret = ldv_undef_int();
42
43 ldv_assume(ret <= 0);
44
45 return ret;
46 }
47
48 /* Add explicit model for __builin_expect GCC function. Without the model a
49 return value will be treated as nondetermined by verifiers. */
50 static inline long __builtin_expect(long exp, long c)
51 {
52 return exp;
53 }
54
55 /* This function causes the program to exit abnormally. GCC implements this
56 function by using a target-dependent mechanism (such as intentionally executing
57 an illegal instruction) or by calling abort. The mechanism used may vary from
58 release to release so you should not rely on any particular implementation.
59 http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html */
60 static inline void __builtin_trap(void)
61 {
62 ldv_assert(0);
63 }
64
65 /* The constant is for simulating an error of ldv_undef_ptr() function. */
66 #define LDV_PTR_MAX 2012
67
68 #endif /* _LDV_RCV_H_ */ |
Here is an explanation of a rule violation arisen while checking your driver against a corresponding kernel.
Note that it may be false positive, i.e. there isn't a real error indeed. Please analyze a given error trace and related source code to understand whether there is an error in your driver.
Error trace column contains a path on which the given rule is violated. You can expand/collapse some entity classes by clicking on corresponding checkboxes in a main menu or in an advanced Others menu. Also you can expand/collapse each particular entity by clicking on +/-. In hovering on some entities you can see some tips. Also the error trace is bound with related source code. Line numbers may be shown as links on the left. You can click on them to open corresponding lines in source code.
Source code column contains a content of files related with the error trace. There is source code of your driver (note that there are some LDV modifications at the end), kernel headers and rule model. Tabs show a currently opened file and other available files. In hovering on them you can see full file names. On clicking a corresponding file content will be shown.
| Kernel | Module | Rule | Verifier | Verdict | Status | Timestamp | Bug report |
| linux-4.5-rc7 | drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rtl8188ee.ko | races | CPAchecker | Bug | Fixed | 2016-03-14 16:42:17 | L0232 |
Comment
rtl8723be_dm_watchdog is called from rtl_watchdog_wq_callback, there are no synchronization primitives. Is it a real bug?
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