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Bug # 187

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-__CPAchecker_initialize()
{
20 typedef unsigned char __u8;
23 typedef unsigned short __u16;
25 typedef int __s32;
26 typedef unsigned int __u32;
29 typedef long long __s64;
30 typedef unsigned long long __u64;
15 typedef signed char s8;
16 typedef unsigned char u8;
18 typedef short s16;
19 typedef unsigned short u16;
21 typedef int s32;
22 typedef unsigned int u32;
24 typedef long long s64;
25 typedef unsigned long long u64;
14 typedef long __kernel_long_t;
15 typedef unsigned long __kernel_ulong_t;
27 typedef int __kernel_pid_t;
48 typedef unsigned int __kernel_uid32_t;
49 typedef unsigned int __kernel_gid32_t;
71 typedef __kernel_ulong_t __kernel_size_t;
72 typedef __kernel_long_t __kernel_ssize_t;
87 typedef long long __kernel_loff_t;
88 typedef __kernel_long_t __kernel_time_t;
89 typedef __kernel_long_t __kernel_clock_t;
90 typedef int __kernel_timer_t;
91 typedef int __kernel_clockid_t;
287 struct kernel_symbol { unsigned long value; const char *name; } ;
34 struct module ;
12 typedef __u32 __kernel_dev_t;
15 typedef __kernel_dev_t dev_t;
18 typedef unsigned short umode_t;
21 typedef __kernel_pid_t pid_t;
26 typedef __kernel_clockid_t clockid_t;
29 typedef _Bool bool;
31 typedef __kernel_uid32_t uid_t;
32 typedef __kernel_gid32_t gid_t;
45 typedef __kernel_loff_t loff_t;
54 typedef __kernel_size_t size_t;
59 typedef __kernel_ssize_t ssize_t;
69 typedef __kernel_time_t time_t;
102 typedef __s32 int32_t;
108 typedef __u32 uint32_t;
133 typedef unsigned long sector_t;
134 typedef unsigned long blkcnt_t;
157 typedef unsigned int gfp_t;
158 typedef unsigned int fmode_t;
161 typedef u64 phys_addr_t;
166 typedef phys_addr_t resource_size_t;
176 struct __anonstruct_atomic_t_6 { int counter; } ;
176 typedef struct __anonstruct_atomic_t_6 atomic_t;
181 struct __anonstruct_atomic64_t_7 { long counter; } ;
181 typedef struct __anonstruct_atomic64_t_7 atomic64_t;
182 struct list_head { struct list_head *next; struct list_head *prev; } ;
187 struct hlist_node ;
187 struct hlist_head { struct hlist_node *first; } ;
191 struct hlist_node { struct hlist_node *next; struct hlist_node **pprev; } ;
202 struct callback_head { struct callback_head *next; void (*func)(struct callback_head *); } ;
117 typedef void (*ctor_fn_t)();
283 struct _ddebug { const char *modname; const char *function; const char *filename; const char *format; unsigned int lineno; unsigned char flags; } ;
58 struct device ;
474 struct file_operations ;
486 struct completion ;
487 struct pt_regs ;
546 struct bug_entry { int bug_addr_disp; int file_disp; unsigned short line; unsigned short flags; } ;
61 struct timespec ;
62 struct compat_timespec ;
63 struct pollfd ;
64 enum timespec_type { TT_NONE = 0, TT_NATIVE = 1, TT_COMPAT = 2 } ;
70 struct __anonstruct_futex_27 { u32 *uaddr; u32 val; u32 flags; u32 bitset; u64 time; u32 *uaddr2; } ;
70 union __anonunion____missing_field_name_29 { struct timespec *rmtp; struct compat_timespec *compat_rmtp; } ;
70 struct __anonstruct_nanosleep_28 { clockid_t clockid; enum timespec_type type; union __anonunion____missing_field_name_29 __annonCompField4; u64 expires; } ;
70 struct __anonstruct_poll_30 { struct pollfd *ufds; int nfds; int has_timeout; unsigned long tv_sec; unsigned long tv_nsec; } ;
70 union __anonunion____missing_field_name_26 { struct __anonstruct_futex_27 futex; struct __anonstruct_nanosleep_28 nanosleep; struct __anonstruct_poll_30 poll; } ;
70 struct restart_block { long int (*fn)(struct restart_block *); union __anonunion____missing_field_name_26 __annonCompField5; } ;
61 struct task_struct ;
53 struct page ;
26 struct mm_struct ;
288 struct pt_regs { unsigned long r15; unsigned long r14; unsigned long r13; unsigned long r12; unsigned long bp; unsigned long bx; unsigned long r11; unsigned long r10; unsigned long r9; unsigned long r8; unsigned long ax; unsigned long cx; unsigned long dx; unsigned long si; unsigned long di; unsigned long orig_ax; unsigned long ip; unsigned long cs; unsigned long flags; unsigned long sp; unsigned long ss; } ;
66 struct __anonstruct____missing_field_name_33 { unsigned int a; unsigned int b; } ;
66 struct __anonstruct____missing_field_name_34 { u16 limit0; u16 base0; unsigned char base1; unsigned char type; unsigned char s; unsigned char dpl; unsigned char p; unsigned char limit; unsigned char avl; unsigned char l; unsigned char d; unsigned char g; unsigned char base2; } ;
66 union __anonunion____missing_field_name_32 { struct __anonstruct____missing_field_name_33 __annonCompField6; struct __anonstruct____missing_field_name_34 __annonCompField7; } ;
66 struct desc_struct { union __anonunion____missing_field_name_32 __annonCompField8; } ;
17 typedef unsigned long pgdval_t;
18 typedef unsigned long pgprotval_t;
22 struct pgprot { pgprotval_t pgprot; } ;
256 typedef struct pgprot pgprot_t;
258 struct __anonstruct_pgd_t_36 { pgdval_t pgd; } ;
258 typedef struct __anonstruct_pgd_t_36 pgd_t;
460 typedef struct page *pgtable_t;
471 struct file ;
482 struct seq_file ;
519 struct thread_struct ;
521 struct cpumask ;
20 struct qspinlock { atomic_t val; } ;
33 typedef struct qspinlock arch_spinlock_t;
34 struct qrwlock { atomic_t cnts; arch_spinlock_t wait_lock; } ;
14 typedef struct qrwlock arch_rwlock_t;
247 struct math_emu_info { long ___orig_eip; struct pt_regs *regs; } ;
83 struct static_key { atomic_t enabled; } ;
23 typedef atomic64_t atomic_long_t;
380 struct cpumask { unsigned long bits[128U]; } ;
15 typedef struct cpumask cpumask_t;
685 typedef struct cpumask *cpumask_var_t;
22 struct tracepoint_func { void *func; void *data; int prio; } ;
28 struct tracepoint { const char *name; struct static_key key; int (*regfunc)(); void (*unregfunc)(); struct tracepoint_func *funcs; } ;
237 struct fregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; u32 st_space[20U]; u32 status; } ;
26 struct __anonstruct____missing_field_name_63 { u64 rip; u64 rdp; } ;
26 struct __anonstruct____missing_field_name_64 { u32 fip; u32 fcs; u32 foo; u32 fos; } ;
26 union __anonunion____missing_field_name_62 { struct __anonstruct____missing_field_name_63 __annonCompField14; struct __anonstruct____missing_field_name_64 __annonCompField15; } ;
26 union __anonunion____missing_field_name_65 { u32 padding1[12U]; u32 sw_reserved[12U]; } ;
26 struct fxregs_state { u16 cwd; u16 swd; u16 twd; u16 fop; union __anonunion____missing_field_name_62 __annonCompField16; u32 mxcsr; u32 mxcsr_mask; u32 st_space[32U]; u32 xmm_space[64U]; u32 padding[12U]; union __anonunion____missing_field_name_65 __annonCompField17; } ;
66 struct swregs_state { u32 cwd; u32 swd; u32 twd; u32 fip; u32 fcs; u32 foo; u32 fos; u32 st_space[20U]; u8 ftop; u8 changed; u8 lookahead; u8 no_update; u8 rm; u8 alimit; struct math_emu_info *info; u32 entry_eip; } ;
227 struct xstate_header { u64 xfeatures; u64 xcomp_bv; u64 reserved[6U]; } ;
233 struct xregs_state { struct fxregs_state i387; struct xstate_header header; u8 extended_state_area[0U]; } ;
254 union fpregs_state { struct fregs_state fsave; struct fxregs_state fxsave; struct swregs_state soft; struct xregs_state xsave; u8 __padding[4096U]; } ;
271 struct fpu { unsigned int last_cpu; unsigned char fpstate_active; unsigned char fpregs_active; union fpregs_state state; } ;
174 struct seq_operations ;
416 struct perf_event ;
421 struct __anonstruct_mm_segment_t_77 { unsigned long seg; } ;
421 typedef struct __anonstruct_mm_segment_t_77 mm_segment_t;
422 struct thread_struct { struct desc_struct tls_array[3U]; unsigned long sp0; unsigned long sp; unsigned short es; unsigned short ds; unsigned short fsindex; unsigned short gsindex; u32 status; unsigned long fsbase; unsigned long gsbase; struct perf_event *ptrace_bps[4U]; unsigned long debugreg6; unsigned long ptrace_dr7; unsigned long cr2; unsigned long trap_nr; unsigned long error_code; unsigned long *io_bitmap_ptr; unsigned long iopl; unsigned int io_bitmap_max; mm_segment_t addr_limit; unsigned char sig_on_uaccess_err; unsigned char uaccess_err; struct fpu fpu; } ;
48 struct thread_info { unsigned long flags; } ;
33 struct lockdep_map ;
55 struct stack_trace { unsigned int nr_entries; unsigned int max_entries; unsigned long *entries; int skip; } ;
30 struct lockdep_subclass_key { char __one_byte; } ;
53 struct lock_class_key { struct lockdep_subclass_key subkeys[8U]; } ;
59 struct lock_class { struct hlist_node hash_entry; struct list_head lock_entry; struct lockdep_subclass_key *key; unsigned int subclass; unsigned int dep_gen_id; unsigned long usage_mask; struct stack_trace usage_traces[13U]; struct list_head locks_after; struct list_head locks_before; unsigned int version; unsigned long ops; const char *name; int name_version; unsigned long contention_point[4U]; unsigned long contending_point[4U]; } ;
144 struct lockdep_map { struct lock_class_key *key; struct lock_class *class_cache[2U]; const char *name; int cpu; unsigned long ip; } ;
207 struct held_lock { u64 prev_chain_key; unsigned long acquire_ip; struct lockdep_map *instance; struct lockdep_map *nest_lock; u64 waittime_stamp; u64 holdtime_stamp; unsigned short class_idx; unsigned char irq_context; unsigned char trylock; unsigned char read; unsigned char check; unsigned char hardirqs_off; unsigned short references; unsigned int pin_count; } ;
596 struct raw_spinlock { arch_spinlock_t raw_lock; unsigned int magic; unsigned int owner_cpu; void *owner; struct lockdep_map dep_map; } ;
32 typedef struct raw_spinlock raw_spinlock_t;
33 struct __anonstruct____missing_field_name_79 { u8 __padding[24U]; struct lockdep_map dep_map; } ;
33 union __anonunion____missing_field_name_78 { struct raw_spinlock rlock; struct __anonstruct____missing_field_name_79 __annonCompField20; } ;
33 struct spinlock { union __anonunion____missing_field_name_78 __annonCompField21; } ;
76 typedef struct spinlock spinlock_t;
23 struct __anonstruct_rwlock_t_80 { arch_rwlock_t raw_lock; unsigned int magic; unsigned int owner_cpu; void *owner; struct lockdep_map dep_map; } ;
23 typedef struct __anonstruct_rwlock_t_80 rwlock_t;
428 struct seqcount { unsigned int sequence; struct lockdep_map dep_map; } ;
52 typedef struct seqcount seqcount_t;
601 struct timespec { __kernel_time_t tv_sec; long tv_nsec; } ;
7 typedef __s64 time64_t;
83 struct user_namespace ;
22 struct __anonstruct_kuid_t_96 { uid_t val; } ;
22 typedef struct __anonstruct_kuid_t_96 kuid_t;
27 struct __anonstruct_kgid_t_97 { gid_t val; } ;
27 typedef struct __anonstruct_kgid_t_97 kgid_t;
139 struct kstat { u32 result_mask; umode_t mode; unsigned int nlink; uint32_t blksize; u64 attributes; u64 attributes_mask; u64 ino; dev_t dev; dev_t rdev; kuid_t uid; kgid_t gid; loff_t size; struct timespec atime; struct timespec mtime; struct timespec ctime; struct timespec btime; u64 blocks; } ;
49 struct vm_area_struct ;
31 struct wait_queue_head { spinlock_t lock; struct list_head head; } ;
36 typedef struct wait_queue_head wait_queue_head_t;
97 struct __anonstruct_nodemask_t_98 { unsigned long bits[16U]; } ;
97 typedef struct __anonstruct_nodemask_t_98 nodemask_t;
253 typedef unsigned int isolate_mode_t;
13 struct optimistic_spin_queue { atomic_t tail; } ;
39 struct ww_acquire_ctx ;
40 struct mutex { atomic_long_t owner; spinlock_t wait_lock; struct optimistic_spin_queue osq; struct list_head wait_list; void *magic; struct lockdep_map dep_map; } ;
72 struct mutex_waiter { struct list_head list; struct task_struct *task; struct ww_acquire_ctx *ww_ctx; void *magic; } ;
229 struct rw_semaphore ;
230 struct rw_semaphore { atomic_long_t count; struct list_head wait_list; raw_spinlock_t wait_lock; struct optimistic_spin_queue osq; struct task_struct *owner; struct lockdep_map dep_map; } ;
28 typedef s64 ktime_t;
109 struct timer_list { struct hlist_node entry; unsigned long expires; void (*function)(unsigned long); unsigned long data; u32 flags; struct lockdep_map lockdep_map; } ;
211 struct hrtimer ;
212 enum hrtimer_restart ;
235 struct workqueue_struct ;
236 struct work_struct ;
54 struct work_struct { atomic_long_t data; struct list_head entry; void (*func)(struct work_struct *); struct lockdep_map lockdep_map; } ;
107 struct delayed_work { struct work_struct work; struct timer_list timer; struct workqueue_struct *wq; int cpu; } ;
42 struct completion { unsigned int done; wait_queue_head_t wait; } ;
217 struct resource ;
38 struct ldt_struct ;
38 struct vdso_image ;
38 struct __anonstruct_mm_context_t_163 { struct ldt_struct *ldt; unsigned short ia32_compat; struct mutex lock; void *vdso; const struct vdso_image *vdso_image; atomic_t perf_rdpmc_allowed; u16 pkey_allocation_map; s16 execute_only_pkey; void *bd_addr; } ;
38 typedef struct __anonstruct_mm_context_t_163 mm_context_t;
1314 struct llist_node ;
1314 struct llist_head { struct llist_node *first; } ;
69 struct llist_node { struct llist_node *next; } ;
596 struct rb_node { unsigned long __rb_parent_color; struct rb_node *rb_right; struct rb_node *rb_left; } ;
41 struct rb_root { struct rb_node *rb_node; } ;
836 struct nsproxy ;
37 struct cred ;
19 struct arch_tlbflush_unmap_batch { struct cpumask cpumask; } ;
13 struct vmacache { u32 seqnum; struct vm_area_struct *vmas[4U]; } ;
45 struct task_rss_stat { int events; int count[4U]; } ;
53 struct mm_rss_stat { atomic_long_t count[4U]; } ;
58 struct page_frag { struct page *page; __u32 offset; __u32 size; } ;
65 struct tlbflush_unmap_batch { struct arch_tlbflush_unmap_batch arch; bool flush_required; bool writable; } ;
92 struct inode ;
58 struct arch_uprobe_task { unsigned long saved_scratch_register; unsigned int saved_trap_nr; unsigned int saved_tf; } ;
66 enum uprobe_task_state { UTASK_RUNNING = 0, UTASK_SSTEP = 1, UTASK_SSTEP_ACK = 2, UTASK_SSTEP_TRAPPED = 3 } ;
73 struct __anonstruct____missing_field_name_217 { struct arch_uprobe_task autask; unsigned long vaddr; } ;
73 struct __anonstruct____missing_field_name_218 { struct callback_head dup_xol_work; unsigned long dup_xol_addr; } ;
73 union __anonunion____missing_field_name_216 { struct __anonstruct____missing_field_name_217 __annonCompField36; struct __anonstruct____missing_field_name_218 __annonCompField37; } ;
73 struct uprobe ;
73 struct return_instance ;
73 struct uprobe_task { enum uprobe_task_state state; union __anonunion____missing_field_name_216 __annonCompField38; struct uprobe *active_uprobe; unsigned long xol_vaddr; struct return_instance *return_instances; unsigned int depth; } ;
95 struct return_instance { struct uprobe *uprobe; unsigned long func; unsigned long stack; unsigned long orig_ret_vaddr; bool chained; struct return_instance *next; } ;
111 struct xol_area ;
112 struct uprobes_state { struct xol_area *xol_area; } ;
151 struct address_space ;
152 struct mem_cgroup ;
153 union __anonunion____missing_field_name_219 { struct address_space *mapping; void *s_mem; atomic_t compound_mapcount; } ;
153 union __anonunion____missing_field_name_220 { unsigned long index; void *freelist; } ;
153 struct __anonstruct____missing_field_name_224 { unsigned short inuse; unsigned short objects; unsigned char frozen; } ;
153 union __anonunion____missing_field_name_223 { atomic_t _mapcount; unsigned int active; struct __anonstruct____missing_field_name_224 __annonCompField41; int units; } ;
153 struct __anonstruct____missing_field_name_222 { union __anonunion____missing_field_name_223 __annonCompField42; atomic_t _refcount; } ;
153 union __anonunion____missing_field_name_221 { unsigned long counters; struct __anonstruct____missing_field_name_222 __annonCompField43; } ;
153 struct dev_pagemap ;
153 struct __anonstruct____missing_field_name_226 { struct page *next; int pages; int pobjects; } ;
153 struct __anonstruct____missing_field_name_227 { unsigned long compound_head; unsigned int compound_dtor; unsigned int compound_order; } ;
153 struct __anonstruct____missing_field_name_228 { unsigned long __pad; pgtable_t pmd_huge_pte; } ;
153 union __anonunion____missing_field_name_225 { struct list_head lru; struct dev_pagemap *pgmap; struct __anonstruct____missing_field_name_226 __annonCompField45; struct callback_head callback_head; struct __anonstruct____missing_field_name_227 __annonCompField46; struct __anonstruct____missing_field_name_228 __annonCompField47; } ;
153 struct kmem_cache ;
153 union __anonunion____missing_field_name_229 { unsigned long private; spinlock_t *ptl; struct kmem_cache *slab_cache; } ;
153 struct page { unsigned long flags; union __anonunion____missing_field_name_219 __annonCompField39; union __anonunion____missing_field_name_220 __annonCompField40; union __anonunion____missing_field_name_221 __annonCompField44; union __anonunion____missing_field_name_225 __annonCompField48; union __anonunion____missing_field_name_229 __annonCompField49; struct mem_cgroup *mem_cgroup; } ;
266 struct userfaultfd_ctx ;
266 struct vm_userfaultfd_ctx { struct userfaultfd_ctx *ctx; } ;
273 struct __anonstruct_shared_230 { struct rb_node rb; unsigned long rb_subtree_last; } ;
273 struct anon_vma ;
273 struct vm_operations_struct ;
273 struct mempolicy ;
273 struct vm_area_struct { unsigned long vm_start; unsigned long vm_end; struct vm_area_struct *vm_next; struct vm_area_struct *vm_prev; struct rb_node vm_rb; unsigned long rb_subtree_gap; struct mm_struct *vm_mm; pgprot_t vm_page_prot; unsigned long vm_flags; struct __anonstruct_shared_230 shared; struct list_head anon_vma_chain; struct anon_vma *anon_vma; const struct vm_operations_struct *vm_ops; unsigned long vm_pgoff; struct file *vm_file; void *vm_private_data; struct mempolicy *vm_policy; struct vm_userfaultfd_ctx vm_userfaultfd_ctx; } ;
346 struct core_thread { struct task_struct *task; struct core_thread *next; } ;
351 struct core_state { atomic_t nr_threads; struct core_thread dumper; struct completion startup; } ;
357 struct kioctx_table ;
358 struct linux_binfmt ;
358 struct mmu_notifier_mm ;
358 struct mm_struct { struct vm_area_struct *mmap; struct rb_root mm_rb; u32 vmacache_seqnum; unsigned long int (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); unsigned long mmap_base; unsigned long mmap_legacy_base; unsigned long mmap_compat_base; unsigned long mmap_compat_legacy_base; unsigned long task_size; unsigned long highest_vm_end; pgd_t *pgd; atomic_t mm_users; atomic_t mm_count; atomic_long_t nr_ptes; atomic_long_t nr_pmds; int map_count; spinlock_t page_table_lock; struct rw_semaphore mmap_sem; struct list_head mmlist; unsigned long hiwater_rss; unsigned long hiwater_vm; unsigned long total_vm; unsigned long locked_vm; unsigned long pinned_vm; unsigned long data_vm; unsigned long exec_vm; unsigned long stack_vm; unsigned long def_flags; unsigned long start_code; unsigned long end_code; unsigned long start_data; unsigned long end_data; unsigned long start_brk; unsigned long brk; unsigned long start_stack; unsigned long arg_start; unsigned long arg_end; unsigned long env_start; unsigned long env_end; unsigned long saved_auxv[46U]; struct mm_rss_stat rss_stat; struct linux_binfmt *binfmt; cpumask_var_t cpu_vm_mask_var; mm_context_t context; unsigned long flags; struct core_state *core_state; spinlock_t ioctx_lock; struct kioctx_table *ioctx_table; struct task_struct *owner; struct user_namespace *user_ns; struct file *exe_file; struct mmu_notifier_mm *mmu_notifier_mm; struct cpumask cpumask_allocation; unsigned long numa_next_scan; unsigned long numa_scan_offset; int numa_scan_seq; bool tlb_flush_pending; struct uprobes_state uprobes_state; atomic_long_t hugetlb_usage; struct work_struct async_put_work; } ;
603 struct vdso_image { void *data; unsigned long size; unsigned long alt; unsigned long alt_len; long sym_vvar_start; long sym_vvar_page; long sym_hpet_page; long sym_pvclock_page; long sym_hvclock_page; long sym_VDSO32_NOTE_MASK; long sym___kernel_sigreturn; long sym___kernel_rt_sigreturn; long sym___kernel_vsyscall; long sym_int80_landing_pad; } ;
15 typedef __u64 Elf64_Addr;
16 typedef __u16 Elf64_Half;
18 typedef __u64 Elf64_Off;
20 typedef __u32 Elf64_Word;
21 typedef __u64 Elf64_Xword;
190 struct elf64_sym { Elf64_Word st_name; unsigned char st_info; unsigned char st_other; Elf64_Half st_shndx; Elf64_Addr st_value; Elf64_Xword st_size; } ;
198 typedef struct elf64_sym Elf64_Sym;
219 struct elf64_hdr { unsigned char e_ident[16U]; Elf64_Half e_type; Elf64_Half e_machine; Elf64_Word e_version; Elf64_Addr e_entry; Elf64_Off e_phoff; Elf64_Off e_shoff; Elf64_Word e_flags; Elf64_Half e_ehsize; Elf64_Half e_phentsize; Elf64_Half e_phnum; Elf64_Half e_shentsize; Elf64_Half e_shnum; Elf64_Half e_shstrndx; } ;
235 typedef struct elf64_hdr Elf64_Ehdr;
314 struct elf64_shdr { Elf64_Word sh_name; Elf64_Word sh_type; Elf64_Xword sh_flags; Elf64_Addr sh_addr; Elf64_Off sh_offset; Elf64_Xword sh_size; Elf64_Word sh_link; Elf64_Word sh_info; Elf64_Xword sh_addralign; Elf64_Xword sh_entsize; } ;
326 typedef struct elf64_shdr Elf64_Shdr;
65 struct radix_tree_root ;
65 union __anonunion____missing_field_name_235 { struct list_head private_list; struct callback_head callback_head; } ;
65 struct radix_tree_node { unsigned char shift; unsigned char offset; unsigned char count; unsigned char exceptional; struct radix_tree_node *parent; struct radix_tree_root *root; union __anonunion____missing_field_name_235 __annonCompField50; void *slots[64U]; unsigned long tags[3U][1U]; } ;
107 struct radix_tree_root { gfp_t gfp_mask; struct radix_tree_node *rnode; } ;
176 struct ida { struct radix_tree_root ida_rt; } ;
216 struct dentry ;
217 struct iattr ;
218 struct super_block ;
219 struct file_system_type ;
220 struct kernfs_open_node ;
221 struct kernfs_iattrs ;
245 struct kernfs_root ;
245 struct kernfs_elem_dir { unsigned long subdirs; struct rb_root children; struct kernfs_root *root; } ;
86 struct kernfs_node ;
86 struct kernfs_elem_symlink { struct kernfs_node *target_kn; } ;
90 struct kernfs_ops ;
90 struct kernfs_elem_attr { const struct kernfs_ops *ops; struct kernfs_open_node *open; loff_t size; struct kernfs_node *notify_next; } ;
97 union __anonunion____missing_field_name_244 { struct kernfs_elem_dir dir; struct kernfs_elem_symlink symlink; struct kernfs_elem_attr attr; } ;
97 struct kernfs_node { atomic_t count; atomic_t active; struct lockdep_map dep_map; struct kernfs_node *parent; const char *name; struct rb_node rb; const void *ns; unsigned int hash; union __anonunion____missing_field_name_244 __annonCompField51; void *priv; unsigned short flags; umode_t mode; unsigned int ino; struct kernfs_iattrs *iattr; } ;
139 struct kernfs_syscall_ops { int (*remount_fs)(struct kernfs_root *, int *, char *); int (*show_options)(struct seq_file *, struct kernfs_root *); int (*mkdir)(struct kernfs_node *, const char *, umode_t ); int (*rmdir)(struct kernfs_node *); int (*rename)(struct kernfs_node *, struct kernfs_node *, const char *); int (*show_path)(struct seq_file *, struct kernfs_node *, struct kernfs_root *); } ;
158 struct kernfs_root { struct kernfs_node *kn; unsigned int flags; struct ida ino_ida; struct kernfs_syscall_ops *syscall_ops; struct list_head supers; wait_queue_head_t deactivate_waitq; } ;
174 struct kernfs_open_file { struct kernfs_node *kn; struct file *file; struct seq_file *seq_file; void *priv; struct mutex mutex; struct mutex prealloc_mutex; int event; struct list_head list; char *prealloc_buf; size_t atomic_write_len; bool mmapped; bool released; const struct vm_operations_struct *vm_ops; } ;
194 struct kernfs_ops { int (*open)(struct kernfs_open_file *); void (*release)(struct kernfs_open_file *); int (*seq_show)(struct seq_file *, void *); void * (*seq_start)(struct seq_file *, loff_t *); void * (*seq_next)(struct seq_file *, void *, loff_t *); void (*seq_stop)(struct seq_file *, void *); ssize_t (*read)(struct kernfs_open_file *, char *, size_t , loff_t ); size_t atomic_write_len; bool prealloc; ssize_t (*write)(struct kernfs_open_file *, char *, size_t , loff_t ); int (*mmap)(struct kernfs_open_file *, struct vm_area_struct *); struct lock_class_key lockdep_key; } ;
521 struct sock ;
522 struct kobject ;
523 enum kobj_ns_type { KOBJ_NS_TYPE_NONE = 0, KOBJ_NS_TYPE_NET = 1, KOBJ_NS_TYPES = 2 } ;
529 struct kobj_ns_type_operations { enum kobj_ns_type type; bool (*current_may_mount)(); void * (*grab_current_ns)(); const void * (*netlink_ns)(struct sock *); const void * (*initial_ns)(); void (*drop_ns)(void *); } ;
59 struct bin_attribute ;
60 struct attribute { const char *name; umode_t mode; bool ignore_lockdep; struct lock_class_key *key; struct lock_class_key skey; } ;
37 struct attribute_group { const char *name; umode_t (*is_visible)(struct kobject *, struct attribute *, int); umode_t (*is_bin_visible)(struct kobject *, struct bin_attribute *, int); struct attribute **attrs; struct bin_attribute **bin_attrs; } ;
92 struct bin_attribute { struct attribute attr; size_t size; void *private; ssize_t (*read)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t , size_t ); ssize_t (*write)(struct file *, struct kobject *, struct bin_attribute *, char *, loff_t , size_t ); int (*mmap)(struct file *, struct kobject *, struct bin_attribute *, struct vm_area_struct *); } ;
165 struct sysfs_ops { ssize_t (*show)(struct kobject *, struct attribute *, char *); ssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t ); } ;
530 struct refcount_struct { atomic_t refs; } ;
19 typedef struct refcount_struct refcount_t;
96 struct kref { refcount_t refcount; } ;
52 struct kset ;
52 struct kobj_type ;
52 struct kobject { const char *name; struct list_head entry; struct kobject *parent; struct kset *kset; struct kobj_type *ktype; struct kernfs_node *sd; struct kref kref; struct delayed_work release; unsigned char state_initialized; unsigned char state_in_sysfs; unsigned char state_add_uevent_sent; unsigned char state_remove_uevent_sent; unsigned char uevent_suppress; } ;
117 struct kobj_type { void (*release)(struct kobject *); const struct sysfs_ops *sysfs_ops; struct attribute **default_attrs; const struct kobj_ns_type_operations * (*child_ns_type)(struct kobject *); const void * (*namespace)(struct kobject *); } ;
125 struct kobj_uevent_env { char *argv[3U]; char *envp[32U]; int envp_idx; char buf[2048U]; int buflen; } ;
133 struct kset_uevent_ops { const int (*filter)(struct kset *, struct kobject *); const const char * (*name)(struct kset *, struct kobject *); const int (*uevent)(struct kset *, struct kobject *, struct kobj_uevent_env *); } ;
150 struct kset { struct list_head list; spinlock_t list_lock; struct kobject kobj; const struct kset_uevent_ops *uevent_ops; } ;
224 struct kernel_param ;
229 struct kernel_param_ops { unsigned int flags; int (*set)(const char *, const struct kernel_param *); int (*get)(char *, const struct kernel_param *); void (*free)(void *); } ;
63 struct kparam_string ;
63 struct kparam_array ;
63 union __anonunion____missing_field_name_247 { void *arg; const struct kparam_string *str; const struct kparam_array *arr; } ;
63 struct kernel_param { const char *name; struct module *mod; const struct kernel_param_ops *ops; const u16 perm; s8 level; u8 flags; union __anonunion____missing_field_name_247 __annonCompField52; } ;
85 struct kparam_string { unsigned int maxlen; char *string; } ;
91 struct kparam_array { unsigned int max; unsigned int elemsize; unsigned int *num; const struct kernel_param_ops *ops; void *elem; } ;
533 struct latch_tree_node { struct rb_node node[2U]; } ;
211 struct mod_arch_specific { } ;
38 struct exception_table_entry ;
39 struct module_param_attrs ;
39 struct module_kobject { struct kobject kobj; struct module *mod; struct kobject *drivers_dir; struct module_param_attrs *mp; struct completion *kobj_completion; } ;
49 struct module_attribute { struct attribute attr; ssize_t (*show)(struct module_attribute *, struct module_kobject *, char *); ssize_t (*store)(struct module_attribute *, struct module_kobject *, const char *, size_t ); void (*setup)(struct module *, const char *); int (*test)(struct module *); void (*free)(struct module *); } ;
276 enum module_state { MODULE_STATE_LIVE = 0, MODULE_STATE_COMING = 1, MODULE_STATE_GOING = 2, MODULE_STATE_UNFORMED = 3 } ;
283 struct mod_tree_node { struct module *mod; struct latch_tree_node node; } ;
288 struct module_layout { void *base; unsigned int size; unsigned int text_size; unsigned int ro_size; unsigned int ro_after_init_size; struct mod_tree_node mtn; } ;
304 struct mod_kallsyms { Elf64_Sym *symtab; unsigned int num_symtab; char *strtab; } ;
318 struct klp_modinfo { Elf64_Ehdr hdr; Elf64_Shdr *sechdrs; char *secstrings; unsigned int symndx; } ;
326 struct module_sect_attrs ;
326 struct module_notes_attrs ;
326 struct trace_event_call ;
326 struct trace_eval_map ;
326 struct module { enum module_state state; struct list_head list; char name[56U]; struct module_kobject mkobj; struct module_attribute *modinfo_attrs; const char *version; const char *srcversion; struct kobject *holders_dir; const struct kernel_symbol *syms; const s32 *crcs; unsigned int num_syms; struct mutex param_lock; struct kernel_param *kp; unsigned int num_kp; unsigned int num_gpl_syms; const struct kernel_symbol *gpl_syms; const s32 *gpl_crcs; const struct kernel_symbol *unused_syms; const s32 *unused_crcs; unsigned int num_unused_syms; unsigned int num_unused_gpl_syms; const struct kernel_symbol *unused_gpl_syms; const s32 *unused_gpl_crcs; bool sig_ok; bool async_probe_requested; const struct kernel_symbol *gpl_future_syms; const s32 *gpl_future_crcs; unsigned int num_gpl_future_syms; unsigned int num_exentries; struct exception_table_entry *extable; int (*init)(); struct module_layout core_layout; struct module_layout init_layout; struct mod_arch_specific arch; unsigned long taints; unsigned int num_bugs; struct list_head bug_list; struct bug_entry *bug_table; struct mod_kallsyms *kallsyms; struct mod_kallsyms core_kallsyms; struct module_sect_attrs *sect_attrs; struct module_notes_attrs *notes_attrs; char *args; void *percpu; unsigned int percpu_size; unsigned int num_tracepoints; const struct tracepoint **tracepoints_ptrs; unsigned int num_trace_bprintk_fmt; const char **trace_bprintk_fmt_start; struct trace_event_call **trace_events; unsigned int num_trace_events; struct trace_eval_map **trace_evals; unsigned int num_trace_evals; bool klp; bool klp_alive; struct klp_modinfo *klp_info; struct list_head source_list; struct list_head target_list; void (*exit)(); atomic_t refcnt; ctor_fn_t (**ctors)(); unsigned int num_ctors; } ;
802 struct clk ;
13 struct device_node ;
690 struct resource { resource_size_t start; resource_size_t end; const char *name; unsigned long flags; unsigned long desc; struct resource *parent; struct resource *sibling; struct resource *child; } ;
282 struct klist_node ;
37 struct klist_node { void *n_klist; struct list_head n_node; struct kref n_ref; } ;
93 struct hlist_bl_node ;
93 struct hlist_bl_head { struct hlist_bl_node *first; } ;
36 struct hlist_bl_node { struct hlist_bl_node *next; struct hlist_bl_node **pprev; } ;
114 struct __anonstruct____missing_field_name_301 { spinlock_t lock; int count; } ;
114 union __anonunion____missing_field_name_300 { struct __anonstruct____missing_field_name_301 __annonCompField53; } ;
114 struct lockref { union __anonunion____missing_field_name_300 __annonCompField54; } ;
77 struct path ;
78 struct vfsmount ;
79 struct __anonstruct____missing_field_name_303 { u32 hash; u32 len; } ;
79 union __anonunion____missing_field_name_302 { struct __anonstruct____missing_field_name_303 __annonCompField55; u64 hash_len; } ;
79 struct qstr { union __anonunion____missing_field_name_302 __annonCompField56; const unsigned char *name; } ;
71 struct dentry_operations ;
71 union __anonunion____missing_field_name_304 { struct list_head d_lru; wait_queue_head_t *d_wait; } ;
71 union __anonunion_d_u_305 { struct hlist_node d_alias; struct hlist_bl_node d_in_lookup_hash; struct callback_head d_rcu; } ;
71 struct dentry { unsigned int d_flags; seqcount_t d_seq; struct hlist_bl_node d_hash; struct dentry *d_parent; struct qstr d_name; struct inode *d_inode; unsigned char d_iname[32U]; struct lockref d_lockref; const struct dentry_operations *d_op; struct super_block *d_sb; unsigned long d_time; void *d_fsdata; union __anonunion____missing_field_name_304 __annonCompField57; struct list_head d_child; struct list_head d_subdirs; union __anonunion_d_u_305 d_u; } ;
127 struct dentry_operations { int (*d_revalidate)(struct dentry *, unsigned int); int (*d_weak_revalidate)(struct dentry *, unsigned int); int (*d_hash)(const struct dentry *, struct qstr *); int (*d_compare)(const struct dentry *, unsigned int, const char *, const struct qstr *); int (*d_delete)(const struct dentry *); int (*d_init)(struct dentry *); void (*d_release)(struct dentry *); void (*d_prune)(struct dentry *); void (*d_iput)(struct dentry *, struct inode *); char * (*d_dname)(struct dentry *, char *, int); struct vfsmount * (*d_automount)(struct path *); int (*d_manage)(const struct path *, bool ); struct dentry * (*d_real)(struct dentry *, const struct inode *, unsigned int); } ;
605 struct path { struct vfsmount *mnt; struct dentry *dentry; } ;
19 struct shrink_control { gfp_t gfp_mask; unsigned long nr_to_scan; int nid; struct mem_cgroup *memcg; } ;
27 struct shrinker { unsigned long int (*count_objects)(struct shrinker *, struct shrink_control *); unsigned long int (*scan_objects)(struct shrinker *, struct shrink_control *); int seeks; long batch; unsigned long flags; struct list_head list; atomic_long_t *nr_deferred; } ;
80 struct list_lru_one { struct list_head list; long nr_items; } ;
32 struct list_lru_memcg { struct list_lru_one *lru[0U]; } ;
37 struct list_lru_node { spinlock_t lock; struct list_lru_one lru; struct list_lru_memcg *memcg_lrus; long nr_items; } ;
49 struct list_lru { struct list_lru_node *node; struct list_head list; } ;
190 enum pid_type { PIDTYPE_PID = 0, PIDTYPE_PGID = 1, PIDTYPE_SID = 2, PIDTYPE_MAX = 3 } ;
197 struct pid_namespace ;
197 struct upid { int nr; struct pid_namespace *ns; struct hlist_node pid_chain; } ;
56 struct pid { atomic_t count; unsigned int level; struct hlist_head tasks[3U]; struct callback_head rcu; struct upid numbers[1U]; } ;
68 struct pid_link { struct hlist_node node; struct pid *pid; } ;
22 struct kernel_cap_struct { __u32 cap[2U]; } ;
25 typedef struct kernel_cap_struct kernel_cap_t;
217 struct fiemap_extent { __u64 fe_logical; __u64 fe_physical; __u64 fe_length; __u64 fe_reserved64[2U]; __u32 fe_flags; __u32 fe_reserved[3U]; } ;
38 enum migrate_mode { MIGRATE_ASYNC = 0, MIGRATE_SYNC_LIGHT = 1, MIGRATE_SYNC = 2 } ;
44 struct rcuwait { struct task_struct *task; } ;
32 enum rcu_sync_type { RCU_SYNC = 0, RCU_SCHED_SYNC = 1, RCU_BH_SYNC = 2 } ;
38 struct rcu_sync { int gp_state; int gp_count; wait_queue_head_t gp_wait; int cb_state; struct callback_head cb_head; enum rcu_sync_type gp_type; } ;
66 struct percpu_rw_semaphore { struct rcu_sync rss; unsigned int *read_count; struct rw_semaphore rw_sem; struct rcuwait writer; int readers_block; } ;
144 struct delayed_call { void (*fn)(void *); void *arg; } ;
25 struct __anonstruct_uuid_t_308 { __u8 b[16U]; } ;
25 typedef struct __anonstruct_uuid_t_308 uuid_t;
6 typedef u32 errseq_t;
302 struct backing_dev_info ;
303 struct bdi_writeback ;
305 struct export_operations ;
308 struct kiocb ;
309 struct pipe_inode_info ;
310 struct poll_table_struct ;
311 struct kstatfs ;
312 struct swap_info_struct ;
313 struct iov_iter ;
314 struct fscrypt_info ;
315 struct fscrypt_operations ;
79 struct iattr { unsigned int ia_valid; umode_t ia_mode; kuid_t ia_uid; kgid_t ia_gid; loff_t ia_size; struct timespec ia_atime; struct timespec ia_mtime; struct timespec ia_ctime; struct file *ia_file; } ;
213 struct dquot ;
214 struct kqid ;
19 typedef __kernel_uid32_t projid_t;
23 struct __anonstruct_kprojid_t_309 { projid_t val; } ;
23 typedef struct __anonstruct_kprojid_t_309 kprojid_t;
181 enum quota_type { USRQUOTA = 0, GRPQUOTA = 1, PRJQUOTA = 2 } ;
66 typedef long long qsize_t;
67 union __anonunion____missing_field_name_310 { kuid_t uid; kgid_t gid; kprojid_t projid; } ;
67 struct kqid { union __anonunion____missing_field_name_310 __annonCompField58; enum quota_type type; } ;
194 struct mem_dqblk { qsize_t dqb_bhardlimit; qsize_t dqb_bsoftlimit; qsize_t dqb_curspace; qsize_t dqb_rsvspace; qsize_t dqb_ihardlimit; qsize_t dqb_isoftlimit; qsize_t dqb_curinodes; time64_t dqb_btime; time64_t dqb_itime; } ;
216 struct quota_format_type ;
217 struct mem_dqinfo { struct quota_format_type *dqi_format; int dqi_fmt_id; struct list_head dqi_dirty_list; unsigned long dqi_flags; unsigned int dqi_bgrace; unsigned int dqi_igrace; qsize_t dqi_max_spc_limit; qsize_t dqi_max_ino_limit; void *dqi_priv; } ;
282 struct dquot { struct hlist_node dq_hash; struct list_head dq_inuse; struct list_head dq_free; struct list_head dq_dirty; struct mutex dq_lock; atomic_t dq_count; wait_queue_head_t dq_wait_unused; struct super_block *dq_sb; struct kqid dq_id; loff_t dq_off; unsigned long dq_flags; struct mem_dqblk dq_dqb; } ;
309 struct quota_format_ops { int (*check_quota_file)(struct super_block *, int); int (*read_file_info)(struct super_block *, int); int (*write_file_info)(struct super_block *, int); int (*free_file_info)(struct super_block *, int); int (*read_dqblk)(struct dquot *); int (*commit_dqblk)(struct dquot *); int (*release_dqblk)(struct dquot *); int (*get_next_id)(struct super_block *, struct kqid *); } ;
321 struct dquot_operations { int (*write_dquot)(struct dquot *); struct dquot * (*alloc_dquot)(struct super_block *, int); void (*destroy_dquot)(struct dquot *); int (*acquire_dquot)(struct dquot *); int (*release_dquot)(struct dquot *); int (*mark_dirty)(struct dquot *); int (*write_info)(struct super_block *, int); qsize_t * (*get_reserved_space)(struct inode *); int (*get_projid)(struct inode *, kprojid_t *); int (*get_inode_usage)(struct inode *, qsize_t *); int (*get_next_id)(struct super_block *, struct kqid *); } ;
340 struct qc_dqblk { int d_fieldmask; u64 d_spc_hardlimit; u64 d_spc_softlimit; u64 d_ino_hardlimit; u64 d_ino_softlimit; u64 d_space; u64 d_ino_count; s64 d_ino_timer; s64 d_spc_timer; int d_ino_warns; int d_spc_warns; u64 d_rt_spc_hardlimit; u64 d_rt_spc_softlimit; u64 d_rt_space; s64 d_rt_spc_timer; int d_rt_spc_warns; } ;
363 struct qc_type_state { unsigned int flags; unsigned int spc_timelimit; unsigned int ino_timelimit; unsigned int rt_spc_timelimit; unsigned int spc_warnlimit; unsigned int ino_warnlimit; unsigned int rt_spc_warnlimit; unsigned long long ino; blkcnt_t blocks; blkcnt_t nextents; } ;
409 struct qc_state { unsigned int s_incoredqs; struct qc_type_state s_state[3U]; } ;
420 struct qc_info { int i_fieldmask; unsigned int i_flags; unsigned int i_spc_timelimit; unsigned int i_ino_timelimit; unsigned int i_rt_spc_timelimit; unsigned int i_spc_warnlimit; unsigned int i_ino_warnlimit; unsigned int i_rt_spc_warnlimit; } ;
433 struct quotactl_ops { int (*quota_on)(struct super_block *, int, int, const struct path *); int (*quota_off)(struct super_block *, int); int (*quota_enable)(struct super_block *, unsigned int); int (*quota_disable)(struct super_block *, unsigned int); int (*quota_sync)(struct super_block *, int); int (*set_info)(struct super_block *, int, struct qc_info *); int (*get_dqblk)(struct super_block *, struct kqid , struct qc_dqblk *); int (*get_nextdqblk)(struct super_block *, struct kqid *, struct qc_dqblk *); int (*set_dqblk)(struct super_block *, struct kqid , struct qc_dqblk *); int (*get_state)(struct super_block *, struct qc_state *); int (*rm_xquota)(struct super_block *, unsigned int); } ;
449 struct quota_format_type { int qf_fmt_id; const struct quota_format_ops *qf_ops; struct module *qf_owner; struct quota_format_type *qf_next; } ;
513 struct quota_info { unsigned int flags; struct mutex dqio_mutex; struct inode *files[3U]; struct mem_dqinfo info[3U]; const struct quota_format_ops *ops[3U]; } ;
542 struct writeback_control ;
543 enum rw_hint { WRITE_LIFE_NOT_SET = 0, WRITE_LIFE_NONE = 1, WRITE_LIFE_SHORT = 2, WRITE_LIFE_MEDIUM = 3, WRITE_LIFE_LONG = 4, WRITE_LIFE_EXTREME = 5 } ;
552 struct kiocb { struct file *ki_filp; loff_t ki_pos; void (*ki_complete)(struct kiocb *, long, long); void *private; int ki_flags; enum rw_hint ki_hint; } ;
326 struct address_space_operations { int (*writepage)(struct page *, struct writeback_control *); int (*readpage)(struct file *, struct page *); int (*writepages)(struct address_space *, struct writeback_control *); int (*set_page_dirty)(struct page *); int (*readpages)(struct file *, struct address_space *, struct list_head *, unsigned int); int (*write_begin)(struct file *, struct address_space *, loff_t , unsigned int, unsigned int, struct page **, void **); int (*write_end)(struct file *, struct address_space *, loff_t , unsigned int, unsigned int, struct page *, void *); sector_t (*bmap)(struct address_space *, sector_t ); void (*invalidatepage)(struct page *, unsigned int, unsigned int); int (*releasepage)(struct page *, gfp_t ); void (*freepage)(struct page *); ssize_t (*direct_IO)(struct kiocb *, struct iov_iter *); int (*migratepage)(struct address_space *, struct page *, struct page *, enum migrate_mode ); bool (*isolate_page)(struct page *, isolate_mode_t ); void (*putback_page)(struct page *); int (*launder_page)(struct page *); int (*is_partially_uptodate)(struct page *, unsigned long, unsigned long); void (*is_dirty_writeback)(struct page *, bool *, bool *); int (*error_remove_page)(struct address_space *, struct page *); int (*swap_activate)(struct swap_info_struct *, struct file *, sector_t *); void (*swap_deactivate)(struct file *); } ;
385 struct address_space { struct inode *host; struct radix_tree_root page_tree; spinlock_t tree_lock; atomic_t i_mmap_writable; struct rb_root i_mmap; struct rw_semaphore i_mmap_rwsem; unsigned long nrpages; unsigned long nrexceptional; unsigned long writeback_index; const struct address_space_operations *a_ops; unsigned long flags; spinlock_t private_lock; gfp_t gfp_mask; struct list_head private_list; void *private_data; errseq_t wb_err; } ;
408 struct request_queue ;
409 struct hd_struct ;
409 struct gendisk ;
409 struct block_device { dev_t bd_dev; int bd_openers; struct inode *bd_inode; struct super_block *bd_super; struct mutex bd_mutex; void *bd_claiming; void *bd_holder; int bd_holders; bool bd_write_holder; struct list_head bd_holder_disks; struct block_device *bd_contains; unsigned int bd_block_size; struct hd_struct *bd_part; unsigned int bd_part_count; int bd_invalidated; struct gendisk *bd_disk; struct request_queue *bd_queue; struct backing_dev_info *bd_bdi; struct list_head bd_list; unsigned long bd_private; int bd_fsfreeze_count; struct mutex bd_fsfreeze_mutex; } ;
525 struct posix_acl ;
552 struct fsnotify_mark_connector ;
553 struct inode_operations ;
553 union __anonunion____missing_field_name_315 { const unsigned int i_nlink; unsigned int __i_nlink; } ;
553 union __anonunion____missing_field_name_316 { struct hlist_head i_dentry; struct callback_head i_rcu; } ;
553 struct file_lock_context ;
553 struct cdev ;
553 union __anonunion____missing_field_name_317 { struct pipe_inode_info *i_pipe; struct block_device *i_bdev; struct cdev *i_cdev; char *i_link; unsigned int i_dir_seq; } ;
553 struct inode { umode_t i_mode; unsigned short i_opflags; kuid_t i_uid; kgid_t i_gid; unsigned int i_flags; struct posix_acl *i_acl; struct posix_acl *i_default_acl; const struct inode_operations *i_op; struct super_block *i_sb; struct address_space *i_mapping; void *i_security; unsigned long i_ino; union __anonunion____missing_field_name_315 __annonCompField59; dev_t i_rdev; loff_t i_size; struct timespec i_atime; struct timespec i_mtime; struct timespec i_ctime; spinlock_t i_lock; unsigned short i_bytes; unsigned int i_blkbits; enum rw_hint i_write_hint; blkcnt_t i_blocks; unsigned long i_state; struct rw_semaphore i_rwsem; unsigned long dirtied_when; unsigned long dirtied_time_when; struct hlist_node i_hash; struct list_head i_io_list; struct bdi_writeback *i_wb; int i_wb_frn_winner; u16 i_wb_frn_avg_time; u16 i_wb_frn_history; struct list_head i_lru; struct list_head i_sb_list; struct list_head i_wb_list; union __anonunion____missing_field_name_316 __annonCompField60; u64 i_version; atomic_t i_count; atomic_t i_dio_count; atomic_t i_writecount; atomic_t i_readcount; const struct file_operations *i_fop; struct file_lock_context *i_flctx; struct address_space i_data; struct list_head i_devices; union __anonunion____missing_field_name_317 __annonCompField61; __u32 i_generation; __u32 i_fsnotify_mask; struct fsnotify_mark_connector *i_fsnotify_marks; struct fscrypt_info *i_crypt_info; void *i_private; } ;
816 struct fown_struct { rwlock_t lock; struct pid *pid; enum pid_type pid_type; kuid_t uid; kuid_t euid; int signum; } ;
824 struct file_ra_state { unsigned long start; unsigned int size; unsigned int async_size; unsigned int ra_pages; unsigned int mmap_miss; loff_t prev_pos; } ;
847 union __anonunion_f_u_318 { struct llist_node fu_llist; struct callback_head fu_rcuhead; } ;
847 struct file { union __anonunion_f_u_318 f_u; struct path f_path; struct inode *f_inode; const struct file_operations *f_op; spinlock_t f_lock; enum rw_hint f_write_hint; atomic_long_t f_count; unsigned int f_flags; fmode_t f_mode; struct mutex f_pos_lock; loff_t f_pos; struct fown_struct f_owner; const struct cred *f_cred; struct file_ra_state f_ra; u64 f_version; void *f_security; void *private_data; struct list_head f_ep_links; struct list_head f_tfile_llink; struct address_space *f_mapping; errseq_t f_wb_err; } ;
936 typedef void *fl_owner_t;
937 struct file_lock ;
938 struct file_lock_operations { void (*fl_copy_lock)(struct file_lock *, struct file_lock *); void (*fl_release_private)(struct file_lock *); } ;
944 struct lock_manager_operations { int (*lm_compare_owner)(struct file_lock *, struct file_lock *); unsigned long int (*lm_owner_key)(struct file_lock *); fl_owner_t (*lm_get_owner)(fl_owner_t ); void (*lm_put_owner)(fl_owner_t ); void (*lm_notify)(struct file_lock *); int (*lm_grant)(struct file_lock *, int); bool (*lm_break)(struct file_lock *); int (*lm_change)(struct file_lock *, int, struct list_head *); void (*lm_setup)(struct file_lock *, void **); } ;
971 struct nlm_lockowner ;
972 struct nfs_lock_info { u32 state; struct nlm_lockowner *owner; struct list_head list; } ;
14 struct nfs4_lock_state ;
15 struct nfs4_lock_info { struct nfs4_lock_state *owner; } ;
19 struct fasync_struct ;
19 struct __anonstruct_afs_320 { struct list_head link; int state; } ;
19 union __anonunion_fl_u_319 { struct nfs_lock_info nfs_fl; struct nfs4_lock_info nfs4_fl; struct __anonstruct_afs_320 afs; } ;
19 struct file_lock { struct file_lock *fl_next; struct list_head fl_list; struct hlist_node fl_link; struct list_head fl_block; fl_owner_t fl_owner; unsigned int fl_flags; unsigned char fl_type; unsigned int fl_pid; int fl_link_cpu; struct pid *fl_nspid; wait_queue_head_t fl_wait; struct file *fl_file; loff_t fl_start; loff_t fl_end; struct fasync_struct *fl_fasync; unsigned long fl_break_time; unsigned long fl_downgrade_time; const struct file_lock_operations *fl_ops; const struct lock_manager_operations *fl_lmops; union __anonunion_fl_u_319 fl_u; } ;
1024 struct file_lock_context { spinlock_t flc_lock; struct list_head flc_flock; struct list_head flc_posix; struct list_head flc_lease; } ;
1089 struct files_struct ;
1242 struct fasync_struct { spinlock_t fa_lock; int magic; int fa_fd; struct fasync_struct *fa_next; struct file *fa_file; struct callback_head fa_rcu; } ;
1277 struct sb_writers { int frozen; wait_queue_head_t wait_unfrozen; struct percpu_rw_semaphore rw_sem[3U]; } ;
1307 struct super_operations ;
1307 struct xattr_handler ;
1307 struct mtd_info ;
1307 struct super_block { struct list_head s_list; dev_t s_dev; unsigned char s_blocksize_bits; unsigned long s_blocksize; loff_t s_maxbytes; struct file_system_type *s_type; const struct super_operations *s_op; const struct dquot_operations *dq_op; const struct quotactl_ops *s_qcop; const struct export_operations *s_export_op; unsigned long s_flags; unsigned long s_iflags; unsigned long s_magic; struct dentry *s_root; struct rw_semaphore s_umount; int s_count; atomic_t s_active; void *s_security; const struct xattr_handler **s_xattr; const struct fscrypt_operations *s_cop; struct hlist_bl_head s_anon; struct list_head s_mounts; struct block_device *s_bdev; struct backing_dev_info *s_bdi; struct mtd_info *s_mtd; struct hlist_node s_instances; unsigned int s_quota_types; struct quota_info s_dquot; struct sb_writers s_writers; char s_id[32U]; uuid_t s_uuid; void *s_fs_info; unsigned int s_max_links; fmode_t s_mode; u32 s_time_gran; struct mutex s_vfs_rename_mutex; char *s_subtype; const struct dentry_operations *s_d_op; int cleancache_poolid; struct shrinker s_shrink; atomic_long_t s_remove_count; int s_readonly_remount; struct workqueue_struct *s_dio_done_wq; struct hlist_head s_pins; struct user_namespace *s_user_ns; struct list_lru s_dentry_lru; struct list_lru s_inode_lru; struct callback_head rcu; struct work_struct destroy_work; struct mutex s_sync_lock; int s_stack_depth; spinlock_t s_inode_list_lock; struct list_head s_inodes; spinlock_t s_inode_wblist_lock; struct list_head s_inodes_wb; } ;
1588 struct fiemap_extent_info { unsigned int fi_flags; unsigned int fi_extents_mapped; unsigned int fi_extents_max; struct fiemap_extent *fi_extents_start; } ;
1601 struct dir_context ;
1626 struct dir_context { int (*actor)(struct dir_context *, const char *, int, loff_t , u64 , unsigned int); loff_t pos; } ;
1633 struct file_operations { struct module *owner; loff_t (*llseek)(struct file *, loff_t , int); ssize_t (*read)(struct file *, char *, size_t , loff_t *); ssize_t (*write)(struct file *, const char *, size_t , loff_t *); ssize_t (*read_iter)(struct kiocb *, struct iov_iter *); ssize_t (*write_iter)(struct kiocb *, struct iov_iter *); int (*iterate)(struct file *, struct dir_context *); int (*iterate_shared)(struct file *, struct dir_context *); unsigned int (*poll)(struct file *, struct poll_table_struct *); long int (*unlocked_ioctl)(struct file *, unsigned int, unsigned long); long int (*compat_ioctl)(struct file *, unsigned int, unsigned long); int (*mmap)(struct file *, struct vm_area_struct *); int (*open)(struct inode *, struct file *); int (*flush)(struct file *, fl_owner_t ); int (*release)(struct inode *, struct file *); int (*fsync)(struct file *, loff_t , loff_t , int); int (*fasync)(int, struct file *, int); int (*lock)(struct file *, int, struct file_lock *); ssize_t (*sendpage)(struct file *, struct page *, int, size_t , loff_t *, int); unsigned long int (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); int (*check_flags)(int); int (*flock)(struct file *, int, struct file_lock *); ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t , unsigned int); ssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t , unsigned int); int (*setlease)(struct file *, long, struct file_lock **, void **); long int (*fallocate)(struct file *, int, loff_t , loff_t ); void (*show_fdinfo)(struct seq_file *, struct file *); ssize_t (*copy_file_range)(struct file *, loff_t , struct file *, loff_t , size_t , unsigned int); int (*clone_file_range)(struct file *, loff_t , struct file *, loff_t , u64 ); ssize_t (*dedupe_file_range)(struct file *, u64 , u64 , struct file *, u64 ); } ;
1701 struct inode_operations { struct dentry * (*lookup)(struct inode *, struct dentry *, unsigned int); const char * (*get_link)(struct dentry *, struct inode *, struct delayed_call *); int (*permission)(struct inode *, int); struct posix_acl * (*get_acl)(struct inode *, int); int (*readlink)(struct dentry *, char *, int); int (*create)(struct inode *, struct dentry *, umode_t , bool ); int (*link)(struct dentry *, struct inode *, struct dentry *); int (*unlink)(struct inode *, struct dentry *); int (*symlink)(struct inode *, struct dentry *, const char *); int (*mkdir)(struct inode *, struct dentry *, umode_t ); int (*rmdir)(struct inode *, struct dentry *); int (*mknod)(struct inode *, struct dentry *, umode_t , dev_t ); int (*rename)(struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*setattr)(struct dentry *, struct iattr *); int (*getattr)(const struct path *, struct kstat *, u32 , unsigned int); ssize_t (*listxattr)(struct dentry *, char *, size_t ); int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 , u64 ); int (*update_time)(struct inode *, struct timespec *, int); int (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned int, umode_t , int *); int (*tmpfile)(struct inode *, struct dentry *, umode_t ); int (*set_acl)(struct inode *, struct posix_acl *, int); } ;
1774 struct super_operations { struct inode * (*alloc_inode)(struct super_block *); void (*destroy_inode)(struct inode *); void (*dirty_inode)(struct inode *, int); int (*write_inode)(struct inode *, struct writeback_control *); int (*drop_inode)(struct inode *); void (*evict_inode)(struct inode *); void (*put_super)(struct super_block *); int (*sync_fs)(struct super_block *, int); int (*freeze_super)(struct super_block *); int (*freeze_fs)(struct super_block *); int (*thaw_super)(struct super_block *); int (*unfreeze_fs)(struct super_block *); int (*statfs)(struct dentry *, struct kstatfs *); int (*remount_fs)(struct super_block *, int *, char *); void (*umount_begin)(struct super_block *); int (*show_options)(struct seq_file *, struct dentry *); int (*show_devname)(struct seq_file *, struct dentry *); int (*show_path)(struct seq_file *, struct dentry *); int (*show_stats)(struct seq_file *, struct dentry *); ssize_t (*quota_read)(struct super_block *, int, char *, size_t , loff_t ); ssize_t (*quota_write)(struct super_block *, int, const char *, size_t , loff_t ); struct dquot ** (*get_dquots)(struct inode *); int (*bdev_try_to_free_page)(struct super_block *, struct page *, gfp_t ); long int (*nr_cached_objects)(struct super_block *, struct shrink_control *); long int (*free_cached_objects)(struct super_block *, struct shrink_control *); } ;
2040 struct file_system_type { const char *name; int fs_flags; struct dentry * (*mount)(struct file_system_type *, int, const char *, void *); void (*kill_sb)(struct super_block *); struct module *owner; struct file_system_type *next; struct hlist_head fs_supers; struct lock_class_key s_lock_key; struct lock_class_key s_umount_key; struct lock_class_key s_vfs_rename_key; struct lock_class_key s_writers_key[3U]; struct lock_class_key i_lock_key; struct lock_class_key i_mutex_key; struct lock_class_key i_mutex_dir_key; } ;
3331 struct assoc_array_ptr ;
3331 struct assoc_array { struct assoc_array_ptr *root; unsigned long nr_leaves_on_tree; } ;
32 typedef int32_t key_serial_t;
35 typedef uint32_t key_perm_t;
36 struct key ;
37 struct user_struct ;
38 struct signal_struct ;
39 struct key_type ;
43 struct keyring_index_key { struct key_type *type; const char *description; size_t desc_len; } ;
92 union key_payload { void *rcu_data0; void *data[4U]; } ;
131 struct key_restriction { int (*check)(struct key *, const struct key_type *, const union key_payload *, struct key *); struct key *key; struct key_type *keytype; } ;
140 union __anonunion____missing_field_name_321 { struct list_head graveyard_link; struct rb_node serial_node; } ;
140 struct key_user ;
140 union __anonunion____missing_field_name_322 { time_t expiry; time_t revoked_at; } ;
140 struct __anonstruct____missing_field_name_324 { struct key_type *type; char *description; } ;
140 union __anonunion____missing_field_name_323 { struct keyring_index_key index_key; struct __anonstruct____missing_field_name_324 __annonCompField64; } ;
140 struct __anonstruct____missing_field_name_326 { struct list_head name_link; struct assoc_array keys; } ;
140 union __anonunion____missing_field_name_325 { union key_payload payload; struct __anonstruct____missing_field_name_326 __annonCompField66; int reject_error; } ;
140 struct key { refcount_t usage; key_serial_t serial; union __anonunion____missing_field_name_321 __annonCompField62; struct rw_semaphore sem; struct key_user *user; void *security; union __anonunion____missing_field_name_322 __annonCompField63; time_t last_used_at; kuid_t uid; kgid_t gid; key_perm_t perm; unsigned short quotalen; unsigned short datalen; unsigned long flags; union __anonunion____missing_field_name_323 __annonCompField65; union __anonunion____missing_field_name_325 __annonCompField67; struct key_restriction *restrict_link; } ;
390 struct audit_context ;
45 struct sem_undo_list ;
45 struct sysv_sem { struct sem_undo_list *undo_list; } ;
26 struct sysv_shm { struct list_head shm_clist; } ;
12 enum kcov_mode { KCOV_MODE_DISABLED = 0, KCOV_MODE_TRACE = 1 } ;
84 struct plist_node { int prio; struct list_head prio_list; struct list_head node_list; } ;
299 struct timerqueue_node { struct rb_node node; ktime_t expires; } ;
12 struct timerqueue_head { struct rb_root head; struct timerqueue_node *next; } ;
50 struct hrtimer_clock_base ;
51 struct hrtimer_cpu_base ;
60 enum hrtimer_restart { HRTIMER_NORESTART = 0, HRTIMER_RESTART = 1 } ;
65 struct hrtimer { struct timerqueue_node node; ktime_t _softexpires; enum hrtimer_restart (*function)(struct hrtimer *); struct hrtimer_clock_base *base; u8 state; u8 is_rel; } ;
113 struct hrtimer_clock_base { struct hrtimer_cpu_base *cpu_base; int index; clockid_t clockid; struct timerqueue_head active; ktime_t (*get_time)(); ktime_t offset; } ;
146 struct hrtimer_cpu_base { raw_spinlock_t lock; seqcount_t seq; struct hrtimer *running; unsigned int cpu; unsigned int active_bases; unsigned int clock_was_set_seq; bool migration_enabled; bool nohz_active; unsigned char in_hrtirq; unsigned char hres_active; unsigned char hang_detected; ktime_t expires_next; struct hrtimer *next_timer; unsigned int nr_events; unsigned int nr_retries; unsigned int nr_hangs; unsigned int max_hang_time; struct hrtimer_clock_base clock_base[4U]; } ;
43 struct seccomp_filter ;
44 struct seccomp { int mode; struct seccomp_filter *filter; } ;
11 struct latency_record { unsigned long backtrace[12U]; unsigned int count; unsigned long time; unsigned long max; } ;
24 struct __anonstruct_sigset_t_327 { unsigned long sig[1U]; } ;
24 typedef struct __anonstruct_sigset_t_327 sigset_t;
25 struct siginfo ;
38 union sigval { int sival_int; void *sival_ptr; } ;
10 typedef union sigval sigval_t;
11 struct __anonstruct__kill_329 { __kernel_pid_t _pid; __kernel_uid32_t _uid; } ;
11 struct __anonstruct__timer_330 { __kernel_timer_t _tid; int _overrun; char _pad[0U]; sigval_t _sigval; int _sys_private; } ;
11 struct __anonstruct__rt_331 { __kernel_pid_t _pid; __kernel_uid32_t _uid; sigval_t _sigval; } ;
11 struct __anonstruct__sigchld_332 { __kernel_pid_t _pid; __kernel_uid32_t _uid; int _status; __kernel_clock_t _utime; __kernel_clock_t _stime; } ;
11 struct __anonstruct__addr_bnd_335 { void *_lower; void *_upper; } ;
11 union __anonunion____missing_field_name_334 { struct __anonstruct__addr_bnd_335 _addr_bnd; __u32 _pkey; } ;
11 struct __anonstruct__sigfault_333 { void *_addr; short _addr_lsb; union __anonunion____missing_field_name_334 __annonCompField68; } ;
11 struct __anonstruct__sigpoll_336 { long _band; int _fd; } ;
11 struct __anonstruct__sigsys_337 { void *_call_addr; int _syscall; unsigned int _arch; } ;
11 union __anonunion__sifields_328 { int _pad[28U]; struct __anonstruct__kill_329 _kill; struct __anonstruct__timer_330 _timer; struct __anonstruct__rt_331 _rt; struct __anonstruct__sigchld_332 _sigchld; struct __anonstruct__sigfault_333 _sigfault; struct __anonstruct__sigpoll_336 _sigpoll; struct __anonstruct__sigsys_337 _sigsys; } ;
11 struct siginfo { int si_signo; int si_errno; int si_code; union __anonunion__sifields_328 _sifields; } ;
118 typedef struct siginfo siginfo_t;
21 struct sigpending { struct list_head list; sigset_t signal; } ;
65 struct task_io_accounting { u64 rchar; u64 wchar; u64 syscr; u64 syscw; u64 read_bytes; u64 write_bytes; u64 cancelled_write_bytes; } ;
45 struct bio_list ;
46 struct blk_plug ;
47 struct cfs_rq ;
48 struct fs_struct ;
49 struct futex_pi_state ;
50 struct io_context ;
51 struct nameidata ;
52 struct perf_event_context ;
54 struct reclaim_state ;
55 struct robust_list_head ;
58 struct sighand_struct ;
59 struct task_delay_info ;
60 struct task_group ;
187 struct prev_cputime { u64 utime; u64 stime; raw_spinlock_t lock; } ;
203 struct task_cputime { u64 utime; u64 stime; unsigned long long sum_exec_runtime; } ;
243 struct sched_info { unsigned long pcount; unsigned long long run_delay; unsigned long long last_arrival; unsigned long long last_queued; } ;
262 struct load_weight { unsigned long weight; u32 inv_weight; } ;
279 struct sched_avg { u64 last_update_time; u64 load_sum; u32 util_sum; u32 period_contrib; unsigned long load_avg; unsigned long util_avg; } ;
340 struct sched_statistics { u64 wait_start; u64 wait_max; u64 wait_count; u64 wait_sum; u64 iowait_count; u64 iowait_sum; u64 sleep_start; u64 sleep_max; s64 sum_sleep_runtime; u64 block_start; u64 block_max; u64 exec_max; u64 slice_max; u64 nr_migrations_cold; u64 nr_failed_migrations_affine; u64 nr_failed_migrations_running; u64 nr_failed_migrations_hot; u64 nr_forced_migrations; u64 nr_wakeups; u64 nr_wakeups_sync; u64 nr_wakeups_migrate; u64 nr_wakeups_local; u64 nr_wakeups_remote; u64 nr_wakeups_affine; u64 nr_wakeups_affine_attempts; u64 nr_wakeups_passive; u64 nr_wakeups_idle; } ;
375 struct sched_entity { struct load_weight load; struct rb_node run_node; struct list_head group_node; unsigned int on_rq; u64 exec_start; u64 sum_exec_runtime; u64 vruntime; u64 prev_sum_exec_runtime; u64 nr_migrations; struct sched_statistics statistics; int depth; struct sched_entity *parent; struct cfs_rq *cfs_rq; struct cfs_rq *my_q; struct sched_avg avg; } ;
411 struct rt_rq ;
411 struct sched_rt_entity { struct list_head run_list; unsigned long timeout; unsigned long watchdog_stamp; unsigned int time_slice; unsigned short on_rq; unsigned short on_list; struct sched_rt_entity *back; struct sched_rt_entity *parent; struct rt_rq *rt_rq; struct rt_rq *my_q; } ;
429 struct sched_dl_entity { struct rb_node rb_node; u64 dl_runtime; u64 dl_deadline; u64 dl_period; u64 dl_bw; u64 dl_density; s64 runtime; u64 deadline; unsigned int flags; int dl_throttled; int dl_boosted; int dl_yielded; int dl_non_contending; struct hrtimer dl_timer; struct hrtimer inactive_timer; } ;
514 struct wake_q_node { struct wake_q_node *next; } ;
518 struct sched_class ;
518 struct rt_mutex_waiter ;
518 struct css_set ;
518 struct compat_robust_list_head ;
518 struct numa_group ;
518 struct kcov ;
518 struct task_struct { struct thread_info thread_info; volatile long state; void *stack; atomic_t usage; unsigned int flags; unsigned int ptrace; struct llist_node wake_entry; int on_cpu; unsigned int cpu; unsigned int wakee_flips; unsigned long wakee_flip_decay_ts; struct task_struct *last_wakee; int wake_cpu; int on_rq; int prio; int static_prio; int normal_prio; unsigned int rt_priority; const struct sched_class *sched_class; struct sched_entity se; struct sched_rt_entity rt; struct task_group *sched_task_group; struct sched_dl_entity dl; struct hlist_head preempt_notifiers; unsigned int policy; int nr_cpus_allowed; cpumask_t cpus_allowed; unsigned long rcu_tasks_nvcsw; bool rcu_tasks_holdout; struct list_head rcu_tasks_holdout_list; int rcu_tasks_idle_cpu; struct sched_info sched_info; struct list_head tasks; struct plist_node pushable_tasks; struct rb_node pushable_dl_tasks; struct mm_struct *mm; struct mm_struct *active_mm; struct vmacache vmacache; struct task_rss_stat rss_stat; int exit_state; int exit_code; int exit_signal; int pdeath_signal; unsigned long jobctl; unsigned int personality; unsigned char sched_reset_on_fork; unsigned char sched_contributes_to_load; unsigned char sched_migrated; unsigned char sched_remote_wakeup; unsigned char; unsigned char in_execve; unsigned char in_iowait; unsigned char restore_sigmask; unsigned char memcg_may_oom; unsigned char memcg_kmem_skip_account; unsigned char brk_randomized; unsigned char no_cgroup_migration; unsigned long atomic_flags; struct restart_block restart_block; pid_t pid; pid_t tgid; struct task_struct *real_parent; struct task_struct *parent; struct list_head children; struct list_head sibling; struct task_struct *group_leader; struct list_head ptraced; struct list_head ptrace_entry; struct pid_link pids[3U]; struct list_head thread_group; struct list_head thread_node; struct completion *vfork_done; int *set_child_tid; int *clear_child_tid; u64 utime; u64 stime; u64 gtime; struct prev_cputime prev_cputime; unsigned long nvcsw; unsigned long nivcsw; u64 start_time; u64 real_start_time; unsigned long min_flt; unsigned long maj_flt; struct task_cputime cputime_expires; struct list_head cpu_timers[3U]; const struct cred *ptracer_cred; const struct cred *real_cred; const struct cred *cred; char comm[16U]; struct nameidata *nameidata; struct sysv_sem sysvsem; struct sysv_shm sysvshm; unsigned long last_switch_count; struct fs_struct *fs; struct files_struct *files; struct nsproxy *nsproxy; struct signal_struct *signal; struct sighand_struct *sighand; sigset_t blocked; sigset_t real_blocked; sigset_t saved_sigmask; struct sigpending pending; unsigned long sas_ss_sp; size_t sas_ss_size; unsigned int sas_ss_flags; struct callback_head *task_works; struct audit_context *audit_context; kuid_t loginuid; unsigned int sessionid; struct seccomp seccomp; u32 parent_exec_id; u32 self_exec_id; spinlock_t alloc_lock; raw_spinlock_t pi_lock; struct wake_q_node wake_q; struct rb_root pi_waiters; struct rb_node *pi_waiters_leftmost; struct task_struct *pi_top_task; struct rt_mutex_waiter *pi_blocked_on; struct mutex_waiter *blocked_on; unsigned int irq_events; unsigned long hardirq_enable_ip; unsigned long hardirq_disable_ip; unsigned int hardirq_enable_event; unsigned int hardirq_disable_event; int hardirqs_enabled; int hardirq_context; unsigned long softirq_disable_ip; unsigned long softirq_enable_ip; unsigned int softirq_disable_event; unsigned int softirq_enable_event; int softirqs_enabled; int softirq_context; u64 curr_chain_key; int lockdep_depth; unsigned int lockdep_recursion; struct held_lock held_locks[48U]; gfp_t lockdep_reclaim_gfp; unsigned int in_ubsan; void *journal_info; struct bio_list *bio_list; struct blk_plug *plug; struct reclaim_state *reclaim_state; struct backing_dev_info *backing_dev_info; struct io_context *io_context; unsigned long ptrace_message; siginfo_t *last_siginfo; struct task_io_accounting ioac; u64 acct_rss_mem1; u64 acct_vm_mem1; u64 acct_timexpd; nodemask_t mems_allowed; seqcount_t mems_allowed_seq; int cpuset_mem_spread_rotor; int cpuset_slab_spread_rotor; struct css_set *cgroups; struct list_head cg_list; int closid; struct robust_list_head *robust_list; struct compat_robust_list_head *compat_robust_list; struct list_head pi_state_list; struct futex_pi_state *pi_state_cache; struct perf_event_context *perf_event_ctxp[2U]; struct mutex perf_event_mutex; struct list_head perf_event_list; struct mempolicy *mempolicy; short il_prev; short pref_node_fork; int numa_scan_seq; unsigned int numa_scan_period; unsigned int numa_scan_period_max; int numa_preferred_nid; unsigned long numa_migrate_retry; u64 node_stamp; u64 last_task_numa_placement; u64 last_sum_exec_runtime; struct callback_head numa_work; struct list_head numa_entry; struct numa_group *numa_group; unsigned long *numa_faults; unsigned long total_numa_faults; unsigned long numa_faults_locality[3U]; unsigned long numa_pages_migrated; struct tlbflush_unmap_batch tlb_ubc; struct callback_head rcu; struct pipe_inode_info *splice_pipe; struct page_frag task_frag; struct task_delay_info *delays; int make_it_fail; unsigned int fail_nth; int nr_dirtied; int nr_dirtied_pause; unsigned long dirty_paused_when; int latency_record_count; struct latency_record latency_record[32U]; u64 timer_slack_ns; u64 default_timer_slack_ns; unsigned int kasan_depth; unsigned long trace; unsigned long trace_recursion; enum kcov_mode kcov_mode; unsigned int kcov_size; void *kcov_area; struct kcov *kcov; struct mem_cgroup *memcg_in_oom; gfp_t memcg_oom_gfp_mask; int memcg_oom_order; unsigned int memcg_nr_pages_over_high; struct uprobe_task *utask; unsigned int sequential_io; unsigned int sequential_io_avg; unsigned long task_state_change; int pagefault_disabled; struct task_struct *oom_reaper_list; atomic_t stack_refcount; int patch_state; void *security; struct thread_struct thread; } ;
1607 struct user_struct { atomic_t __count; atomic_t processes; atomic_t sigpending; atomic_t fanotify_listeners; atomic_long_t epoll_watches; unsigned long mq_bytes; unsigned long locked_shm; unsigned long unix_inflight; atomic_long_t pipe_bufs; struct key *uid_keyring; struct key *session_keyring; struct hlist_node uidhash_node; kuid_t uid; atomic_long_t locked_vm; } ;
60 struct group_info { atomic_t usage; int ngroups; kgid_t gid[0U]; } ;
86 struct cred { atomic_t usage; atomic_t subscribers; void *put_addr; unsigned int magic; kuid_t uid; kgid_t gid; kuid_t suid; kgid_t sgid; kuid_t euid; kgid_t egid; kuid_t fsuid; kgid_t fsgid; unsigned int securebits; kernel_cap_t cap_inheritable; kernel_cap_t cap_permitted; kernel_cap_t cap_effective; kernel_cap_t cap_bset; kernel_cap_t cap_ambient; unsigned char jit_keyring; struct key *session_keyring; struct key *process_keyring; struct key *thread_keyring; struct key *request_key_auth; void *security; struct user_struct *user; struct user_namespace *user_ns; struct group_info *group_info; struct callback_head rcu; } ;
369 struct seq_file { char *buf; size_t size; size_t from; size_t count; size_t pad_until; loff_t index; loff_t read_pos; u64 version; struct mutex lock; const struct seq_operations *op; int poll_event; const struct file *file; void *private; } ;
30 struct seq_operations { void * (*start)(struct seq_file *, loff_t *); void (*stop)(struct seq_file *, void *); void * (*next)(struct seq_file *, void *, loff_t *); int (*show)(struct seq_file *, void *); } ;
222 struct pinctrl ;
223 struct pinctrl_state ;
200 struct dev_pin_info { struct pinctrl *p; struct pinctrl_state *default_state; struct pinctrl_state *init_state; struct pinctrl_state *sleep_state; struct pinctrl_state *idle_state; } ;
58 struct pm_message { int event; } ;
64 typedef struct pm_message pm_message_t;
65 struct dev_pm_ops { int (*prepare)(struct device *); void (*complete)(struct device *); int (*suspend)(struct device *); int (*resume)(struct device *); int (*freeze)(struct device *); int (*thaw)(struct device *); int (*poweroff)(struct device *); int (*restore)(struct device *); int (*suspend_late)(struct device *); int (*resume_early)(struct device *); int (*freeze_late)(struct device *); int (*thaw_early)(struct device *); int (*poweroff_late)(struct device *); int (*restore_early)(struct device *); int (*suspend_noirq)(struct device *); int (*resume_noirq)(struct device *); int (*freeze_noirq)(struct device *); int (*thaw_noirq)(struct device *); int (*poweroff_noirq)(struct device *); int (*restore_noirq)(struct device *); int (*runtime_suspend)(struct device *); int (*runtime_resume)(struct device *); int (*runtime_idle)(struct device *); } ;
315 enum rpm_status { RPM_ACTIVE = 0, RPM_RESUMING = 1, RPM_SUSPENDED = 2, RPM_SUSPENDING = 3 } ;
322 enum rpm_request { RPM_REQ_NONE = 0, RPM_REQ_IDLE = 1, RPM_REQ_SUSPEND = 2, RPM_REQ_AUTOSUSPEND = 3, RPM_REQ_RESUME = 4 } ;
330 struct wakeup_source ;
331 struct wake_irq ;
332 struct pm_domain_data ;
333 struct pm_subsys_data { spinlock_t lock; unsigned int refcount; struct list_head clock_list; struct pm_domain_data *domain_data; } ;
551 struct dev_pm_qos ;
551 struct dev_pm_info { pm_message_t power_state; unsigned char can_wakeup; unsigned char async_suspend; bool in_dpm_list; bool is_prepared; bool is_suspended; bool is_noirq_suspended; bool is_late_suspended; bool early_init; bool direct_complete; spinlock_t lock; struct list_head entry; struct completion completion; struct wakeup_source *wakeup; bool wakeup_path; bool syscore; bool no_pm_callbacks; struct timer_list suspend_timer; unsigned long timer_expires; struct work_struct work; wait_queue_head_t wait_queue; struct wake_irq *wakeirq; atomic_t usage_count; atomic_t child_count; unsigned char disable_depth; unsigned char idle_notification; unsigned char request_pending; unsigned char deferred_resume; unsigned char runtime_auto; bool ignore_children; unsigned char no_callbacks; unsigned char irq_safe; unsigned char use_autosuspend; unsigned char timer_autosuspends; unsigned char memalloc_noio; unsigned int links_count; enum rpm_request request; enum rpm_status runtime_status; int runtime_error; int autosuspend_delay; unsigned long last_busy; unsigned long active_jiffies; unsigned long suspended_jiffies; unsigned long accounting_timestamp; struct pm_subsys_data *subsys_data; void (*set_latency_tolerance)(struct device *, s32 ); struct dev_pm_qos *qos; } ;
612 struct dev_pm_domain { struct dev_pm_ops ops; void (*detach)(struct device *, bool ); int (*activate)(struct device *); void (*sync)(struct device *); void (*dismiss)(struct device *); } ;
76 struct dev_archdata { void *iommu; } ;
8 struct dma_map_ops ;
18 struct pdev_archdata { } ;
21 struct device_private ;
22 struct device_driver ;
23 struct driver_private ;
24 struct class ;
25 struct subsys_private ;
26 struct bus_type ;
27 struct fwnode_handle ;
28 struct iommu_ops ;
29 struct iommu_group ;
30 struct iommu_fwspec ;
62 struct bus_type { const char *name; const char *dev_name; struct device *dev_root; const struct attribute_group **bus_groups; const struct attribute_group **dev_groups; const struct attribute_group **drv_groups; int (*match)(struct device *, struct device_driver *); int (*uevent)(struct device *, struct kobj_uevent_env *); int (*probe)(struct device *); int (*remove)(struct device *); void (*shutdown)(struct device *); int (*online)(struct device *); int (*offline)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); int (*num_vf)(struct device *); const struct dev_pm_ops *pm; const struct iommu_ops *iommu_ops; struct subsys_private *p; struct lock_class_key lock_key; } ;
145 struct device_type ;
204 enum probe_type { PROBE_DEFAULT_STRATEGY = 0, PROBE_PREFER_ASYNCHRONOUS = 1, PROBE_FORCE_SYNCHRONOUS = 2 } ;
210 struct of_device_id ;
210 struct acpi_device_id ;
210 struct device_driver { const char *name; struct bus_type *bus; struct module *owner; const char *mod_name; bool suppress_bind_attrs; enum probe_type probe_type; const struct of_device_id *of_match_table; const struct acpi_device_id *acpi_match_table; int (*probe)(struct device *); int (*remove)(struct device *); void (*shutdown)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); const struct attribute_group **groups; const struct dev_pm_ops *pm; struct driver_private *p; } ;
360 struct class { const char *name; struct module *owner; const struct attribute_group **class_groups; const struct attribute_group **dev_groups; struct kobject *dev_kobj; int (*dev_uevent)(struct device *, struct kobj_uevent_env *); char * (*devnode)(struct device *, umode_t *); void (*class_release)(struct class *); void (*dev_release)(struct device *); int (*suspend)(struct device *, pm_message_t ); int (*resume)(struct device *); int (*shutdown)(struct device *); const struct kobj_ns_type_operations *ns_type; const void * (*namespace)(struct device *); const struct dev_pm_ops *pm; struct subsys_private *p; } ;
523 struct device_type { const char *name; const struct attribute_group **groups; int (*uevent)(struct device *, struct kobj_uevent_env *); char * (*devnode)(struct device *, umode_t *, kuid_t *, kgid_t *); void (*release)(struct device *); const struct dev_pm_ops *pm; } ;
723 struct device_dma_parameters { unsigned int max_segment_size; unsigned long segment_boundary_mask; } ;
786 enum dl_dev_state { DL_DEV_NO_DRIVER = 0, DL_DEV_PROBING = 1, DL_DEV_DRIVER_BOUND = 2, DL_DEV_UNBINDING = 3 } ;
793 struct dev_links_info { struct list_head suppliers; struct list_head consumers; enum dl_dev_state status; } ;
813 struct irq_domain ;
813 struct dma_coherent_mem ;
813 struct cma ;
813 struct device { struct device *parent; struct device_private *p; struct kobject kobj; const char *init_name; const struct device_type *type; struct mutex mutex; struct bus_type *bus; struct device_driver *driver; void *platform_data; void *driver_data; struct dev_links_info links; struct dev_pm_info power; struct dev_pm_domain *pm_domain; struct irq_domain *msi_domain; struct dev_pin_info *pins; struct list_head msi_list; int numa_node; const struct dma_map_ops *dma_ops; u64 *dma_mask; u64 coherent_dma_mask; unsigned long dma_pfn_offset; struct device_dma_parameters *dma_parms; struct list_head dma_pools; struct dma_coherent_mem *dma_mem; struct cma *cma_area; struct dev_archdata archdata; struct device_node *of_node; struct fwnode_handle *fwnode; dev_t devt; u32 id; spinlock_t devres_lock; struct list_head devres_head; struct klist_node knode_class; struct class *class; const struct attribute_group **groups; void (*release)(struct device *); struct iommu_group *iommu_group; struct iommu_fwspec *iommu_fwspec; bool offline_disabled; bool offline; bool of_node_reused; } ;
975 struct wakeup_source { const char *name; struct list_head entry; spinlock_t lock; struct wake_irq *wakeirq; struct timer_list timer; unsigned long timer_expires; ktime_t total_time; ktime_t max_time; ktime_t last_time; ktime_t start_prevent_time; ktime_t prevent_sleep_time; unsigned long event_count; unsigned long active_count; unsigned long relax_count; unsigned long expire_count; unsigned long wakeup_count; bool active; bool autosleep_enabled; } ;
1455 struct tty_struct ;
105 struct tty_driver ;
105 struct console { char name[16U]; void (*write)(struct console *, const char *, unsigned int); int (*read)(struct console *, char *, unsigned int); struct tty_driver * (*device)(struct console *, int *); void (*unblank)(); int (*setup)(struct console *, char *); int (*match)(struct console *, char *, int, char *); short flags; short index; int cflag; void *data; struct console *next; } ;
216 enum irqreturn { IRQ_NONE = 0, IRQ_HANDLED = 1, IRQ_WAKE_THREAD = 2 } ;
16 typedef enum irqreturn irqreturn_t;
478 struct proc_dir_entry ;
133 struct exception_table_entry { int insn; int fixup; int handler; } ;
743 struct circ_buf { char *buf; int head; int tail; } ;
6 typedef unsigned char cc_t;
7 typedef unsigned int speed_t;
8 typedef unsigned int tcflag_t;
30 struct ktermios { tcflag_t c_iflag; tcflag_t c_oflag; tcflag_t c_cflag; tcflag_t c_lflag; cc_t c_line; cc_t c_cc[19U]; speed_t c_ispeed; speed_t c_ospeed; } ;
41 struct winsize { unsigned short ws_row; unsigned short ws_col; unsigned short ws_xpixel; unsigned short ws_ypixel; } ;
93 struct termiox { __u16 x_hflag; __u16 x_cflag; __u16 x_rflag[5U]; __u16 x_sflag; } ;
16 struct cdev { struct kobject kobj; struct module *owner; const struct file_operations *ops; struct list_head list; dev_t dev; unsigned int count; } ;
37 struct serial_icounter_struct ;
38 struct tty_operations { struct tty_struct * (*lookup)(struct tty_driver *, struct file *, int); int (*install)(struct tty_driver *, struct tty_struct *); void (*remove)(struct tty_driver *, struct tty_struct *); int (*open)(struct tty_struct *, struct file *); void (*close)(struct tty_struct *, struct file *); void (*shutdown)(struct tty_struct *); void (*cleanup)(struct tty_struct *); int (*write)(struct tty_struct *, const unsigned char *, int); int (*put_char)(struct tty_struct *, unsigned char); void (*flush_chars)(struct tty_struct *); int (*write_room)(struct tty_struct *); int (*chars_in_buffer)(struct tty_struct *); int (*ioctl)(struct tty_struct *, unsigned int, unsigned long); long int (*compat_ioctl)(struct tty_struct *, unsigned int, unsigned long); void (*set_termios)(struct tty_struct *, struct ktermios *); void (*throttle)(struct tty_struct *); void (*unthrottle)(struct tty_struct *); void (*stop)(struct tty_struct *); void (*start)(struct tty_struct *); void (*hangup)(struct tty_struct *); int (*break_ctl)(struct tty_struct *, int); void (*flush_buffer)(struct tty_struct *); void (*set_ldisc)(struct tty_struct *); void (*wait_until_sent)(struct tty_struct *, int); void (*send_xchar)(struct tty_struct *, char); int (*tiocmget)(struct tty_struct *); int (*tiocmset)(struct tty_struct *, unsigned int, unsigned int); int (*resize)(struct tty_struct *, struct winsize *); int (*set_termiox)(struct tty_struct *, struct termiox *); int (*get_icount)(struct tty_struct *, struct serial_icounter_struct *); int (*poll_init)(struct tty_driver *, int, char *); int (*poll_get_char)(struct tty_driver *, int); void (*poll_put_char)(struct tty_driver *, int, char); const struct file_operations *proc_fops; } ;
295 struct tty_port ;
295 struct tty_driver { int magic; struct kref kref; struct cdev **cdevs; struct module *owner; const char *driver_name; const char *name; int name_base; int major; int minor_start; unsigned int num; short type; short subtype; struct ktermios init_termios; unsigned long flags; struct proc_dir_entry *proc_entry; struct tty_driver *other; struct tty_struct **ttys; struct tty_port **ports; struct ktermios **termios; void *driver_state; const struct tty_operations *ops; struct list_head tty_drivers; } ;
362 struct ld_semaphore { long count; raw_spinlock_t wait_lock; unsigned int wait_readers; struct list_head read_wait; struct list_head write_wait; struct lockdep_map dep_map; } ;
159 struct tty_ldisc_ops { int magic; char *name; int num; int flags; int (*open)(struct tty_struct *); void (*close)(struct tty_struct *); void (*flush_buffer)(struct tty_struct *); ssize_t (*read)(struct tty_struct *, struct file *, unsigned char *, size_t ); ssize_t (*write)(struct tty_struct *, struct file *, const unsigned char *, size_t ); int (*ioctl)(struct tty_struct *, struct file *, unsigned int, unsigned long); long int (*compat_ioctl)(struct tty_struct *, struct file *, unsigned int, unsigned long); void (*set_termios)(struct tty_struct *, struct ktermios *); unsigned int (*poll)(struct tty_struct *, struct file *, struct poll_table_struct *); int (*hangup)(struct tty_struct *); void (*receive_buf)(struct tty_struct *, const unsigned char *, char *, int); void (*write_wakeup)(struct tty_struct *); void (*dcd_change)(struct tty_struct *, unsigned int); int (*receive_buf2)(struct tty_struct *, const unsigned char *, char *, int); struct module *owner; int refcount; } ;
207 struct tty_ldisc { struct tty_ldisc_ops *ops; struct tty_struct *tty; } ;
217 union __anonunion____missing_field_name_362 { struct tty_buffer *next; struct llist_node free; } ;
217 struct tty_buffer { union __anonunion____missing_field_name_362 __annonCompField81; int used; int size; int commit; int read; int flags; unsigned long data[0U]; } ;
82 struct tty_bufhead { struct tty_buffer *head; struct work_struct work; struct mutex lock; atomic_t priority; struct tty_buffer sentinel; struct llist_head free; atomic_t mem_used; int mem_limit; struct tty_buffer *tail; } ;
94 struct tty_port_operations { int (*carrier_raised)(struct tty_port *); void (*dtr_rts)(struct tty_port *, int); void (*shutdown)(struct tty_port *); int (*activate)(struct tty_port *, struct tty_struct *); void (*destruct)(struct tty_port *); } ;
220 struct tty_port_client_operations { int (*receive_buf)(struct tty_port *, const unsigned char *, const unsigned char *, size_t ); void (*write_wakeup)(struct tty_port *); } ;
225 struct tty_port { struct tty_bufhead buf; struct tty_struct *tty; struct tty_struct *itty; const struct tty_port_operations *ops; const struct tty_port_client_operations *client_ops; spinlock_t lock; int blocked_open; int count; wait_queue_head_t open_wait; wait_queue_head_t delta_msr_wait; unsigned long flags; unsigned long iflags; unsigned char console; unsigned char low_latency; struct mutex mutex; struct mutex buf_mutex; unsigned char *xmit_buf; unsigned int close_delay; unsigned int closing_wait; int drain_delay; struct kref kref; void *client_data; } ;
252 struct tty_struct { int magic; struct kref kref; struct device *dev; struct tty_driver *driver; const struct tty_operations *ops; int index; struct ld_semaphore ldisc_sem; struct tty_ldisc *ldisc; struct mutex atomic_write_lock; struct mutex legacy_mutex; struct mutex throttle_mutex; struct rw_semaphore termios_rwsem; struct mutex winsize_mutex; spinlock_t ctrl_lock; spinlock_t flow_lock; struct ktermios termios; struct ktermios termios_locked; struct termiox *termiox; char name[64U]; struct pid *pgrp; struct pid *session; unsigned long flags; int count; struct winsize winsize; unsigned char stopped; unsigned char flow_stopped; unsigned long unused; int hw_stopped; unsigned char ctrl_status; unsigned char packet; unsigned long unused_ctrl; unsigned int receive_room; int flow_change; struct tty_struct *link; struct fasync_struct *fasync; wait_queue_head_t write_wait; wait_queue_head_t read_wait; struct work_struct hangup_work; void *disc_data; void *driver_data; spinlock_t files_lock; struct list_head tty_files; int closing; unsigned char *write_buf; int write_cnt; struct work_struct SAK_work; struct tty_port *port; } ;
52 struct serial_struct { int type; int line; unsigned int port; int irq; int flags; int xmit_fifo_size; int custom_divisor; int baud_base; unsigned short close_delay; char io_type; char reserved_char[1U]; int hub6; unsigned short closing_wait; unsigned short closing_wait2; unsigned char *iomem_base; unsigned short iomem_reg_shift; unsigned int port_high; unsigned long iomap_base; } ;
96 struct serial_icounter_struct { int cts; int dsr; int rng; int dcd; int rx; int tx; int frame; int overrun; int parity; int brk; int buf_overrun; int reserved[9U]; } ;
108 struct serial_rs485 { __u32 flags; __u32 delay_rts_before_send; __u32 delay_rts_after_send; __u32 padding[5U]; } ;
25 struct uart_port ;
26 struct uart_ops { unsigned int (*tx_empty)(struct uart_port *); void (*set_mctrl)(struct uart_port *, unsigned int); unsigned int (*get_mctrl)(struct uart_port *); void (*stop_tx)(struct uart_port *); void (*start_tx)(struct uart_port *); void (*throttle)(struct uart_port *); void (*unthrottle)(struct uart_port *); void (*send_xchar)(struct uart_port *, char); void (*stop_rx)(struct uart_port *); void (*enable_ms)(struct uart_port *); void (*break_ctl)(struct uart_port *, int); int (*startup)(struct uart_port *); void (*shutdown)(struct uart_port *); void (*flush_buffer)(struct uart_port *); void (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *); void (*set_ldisc)(struct uart_port *, struct ktermios *); void (*pm)(struct uart_port *, unsigned int, unsigned int); const char * (*type)(struct uart_port *); void (*release_port)(struct uart_port *); int (*request_port)(struct uart_port *); void (*config_port)(struct uart_port *, int); int (*verify_port)(struct uart_port *, struct serial_struct *); int (*ioctl)(struct uart_port *, unsigned int, unsigned long); int (*poll_init)(struct uart_port *); void (*poll_put_char)(struct uart_port *, unsigned char); int (*poll_get_char)(struct uart_port *); } ;
94 struct uart_icount { __u32 cts; __u32 dsr; __u32 rng; __u32 dcd; __u32 rx; __u32 tx; __u32 frame; __u32 overrun; __u32 parity; __u32 brk; __u32 buf_overrun; } ;
114 typedef unsigned int upf_t;
115 typedef unsigned int upstat_t;
116 struct uart_state ;
116 struct uart_port { spinlock_t lock; unsigned long iobase; unsigned char *membase; unsigned int (*serial_in)(struct uart_port *, int); void (*serial_out)(struct uart_port *, int, int); void (*set_termios)(struct uart_port *, struct ktermios *, struct ktermios *); void (*set_ldisc)(struct uart_port *, struct ktermios *); unsigned int (*get_mctrl)(struct uart_port *); void (*set_mctrl)(struct uart_port *, unsigned int); int (*startup)(struct uart_port *); void (*shutdown)(struct uart_port *); void (*throttle)(struct uart_port *); void (*unthrottle)(struct uart_port *); int (*handle_irq)(struct uart_port *); void (*pm)(struct uart_port *, unsigned int, unsigned int); void (*handle_break)(struct uart_port *); int (*rs485_config)(struct uart_port *, struct serial_rs485 *); unsigned int irq; unsigned long irqflags; unsigned int uartclk; unsigned int fifosize; unsigned char x_char; unsigned char regshift; unsigned char iotype; unsigned char unused1; unsigned int read_status_mask; unsigned int ignore_status_mask; struct uart_state *state; struct uart_icount icount; struct console *cons; unsigned long sysrq; upf_t flags; upstat_t status; int hw_stopped; unsigned int mctrl; unsigned int timeout; unsigned int type; const struct uart_ops *ops; unsigned int custom_divisor; unsigned int line; unsigned int minor; resource_size_t mapbase; resource_size_t mapsize; struct device *dev; unsigned char hub6; unsigned char suspended; unsigned char irq_wake; unsigned char unused[2U]; const char *name; struct attribute_group *attr_group; const struct attribute_group **tty_groups; struct serial_rs485 rs485; void *private_data; } ;
267 enum uart_pm_state { UART_PM_STATE_ON = 0, UART_PM_STATE_OFF = 3, UART_PM_STATE_UNDEFINED = 4 } ;
273 struct uart_state { struct tty_port port; enum uart_pm_state pm_state; struct circ_buf xmit; atomic_t refcount; wait_queue_head_t remove_wait; struct uart_port *uart_port; } ;
293 struct uart_driver { struct module *owner; const char *driver_name; const char *dev_name; int major; int minor; int nr; struct console *cons; struct uart_state *state; struct tty_driver *tty_driver; } ;
13 typedef unsigned long kernel_ulong_t;
187 struct acpi_device_id { __u8 id[9U]; kernel_ulong_t driver_data; __u32 cls; __u32 cls_msk; } ;
230 struct of_device_id { char name[32U]; char type[32U]; char compatible[128U]; const void *data; } ;
496 struct platform_device_id { char name[20U]; kernel_ulong_t driver_data; } ;
687 struct mfd_cell ;
689 struct platform_device { const char *name; int id; bool id_auto; struct device dev; u32 num_resources; struct resource *resource; const struct platform_device_id *id_entry; char *driver_override; struct mfd_cell *mfd_cell; struct pdev_archdata archdata; } ;
352 struct sccnxp_pdata { const u8 reg_shift; const u32 mctrl_cfg[2U]; const unsigned int poll_time_us; } ;
155 struct regulator ;
610 struct sccnxp_chip { const char *name; unsigned int nr; unsigned long freq_min; unsigned long freq_std; unsigned long freq_max; unsigned int flags; unsigned int fifosize; } ;
111 struct sccnxp_port { struct uart_driver uart; struct uart_port port[2U]; bool opened[2U]; int irq; u8 imr; struct sccnxp_chip *chip; spinlock_t lock; bool poll; struct timer_list timer; struct sccnxp_pdata pdata; struct regulator *regulator; } ;
253 struct __anonstruct_baud_std_364 { u8 csr; u8 acr; u8 mr0; int baud; } ;
1 long int __builtin_expect(long, long);
34 extern struct module __this_module;
63 void __dynamic_dev_dbg(struct _ddebug *, const struct device *, const char *, ...);
3 bool ldv_is_err(const void *ptr);
6 long int ldv_ptr_err(const void *ptr);
32 void * __memcpy(void *, const void *, size_t );
32 long int PTR_ERR(const void *ptr);
41 bool IS_ERR(const void *ptr);
93 void __raw_spin_lock_init(raw_spinlock_t *, const char *, struct lock_class_key *);
32 unsigned long int _raw_spin_lock_irqsave(raw_spinlock_t *);
43 void _raw_spin_unlock_irqrestore(raw_spinlock_t *, unsigned long);
286 raw_spinlock_t * spinlock_check(spinlock_t *lock);
352 void spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags);
77 extern volatile unsigned long jiffies;
370 unsigned long int __usecs_to_jiffies(const unsigned int);
406 unsigned long int usecs_to_jiffies(const unsigned int u);
92 void init_timer_key(struct timer_list *, unsigned int, const char *, struct lock_class_key *);
188 int mod_timer(struct timer_list *, unsigned long);
202 int del_timer_sync(struct timer_list *);
56 unsigned char readb(const volatile void *addr);
64 void writeb(unsigned char val, volatile void *addr);
87 const char * kobject_name(const struct kobject *kobj);
11 void ldv_clk_disable_clk(struct clk *clk);
12 int ldv_clk_enable_clk();
316 struct clk * devm_clk_get(struct device *, const char *);
348 int ldv_clk_enable_5(struct clk *clk);
376 void ldv_clk_disable_6(struct clk *clk);
398 unsigned long int clk_get_rate(struct clk *);
657 int ldv_clk_prepare_enable_7(struct clk *clk);
656 void * devm_kmalloc(struct device *, size_t , gfp_t );
662 void * devm_kzalloc(struct device *dev, size_t size, gfp_t gfp);
687 void * devm_ioremap_resource(struct device *, struct resource *);
978 const char * dev_name(const struct device *dev);
1025 void * dev_get_drvdata(const struct device *dev);
1030 void dev_set_drvdata(struct device *dev, void *data);
1167 void * dev_get_platdata(const struct device *dev);
1260 void dev_err(const struct device *, const char *, ...);
1264 void dev_notice(const struct device *, const char *, ...);
1266 void _dev_info(const struct device *, const char *, ...);
173 int devm_request_threaded_irq(struct device *, unsigned int, irqreturn_t (*)(int, void *), irqreturn_t (*)(int, void *), unsigned long, const char *, void *);
191 void devm_free_irq(struct device *, unsigned int, void *);
487 void do_SAK(struct tty_struct *);
500 speed_t tty_termios_baud_rate(struct ktermios *);
502 void tty_termios_encode_baud_rate(struct ktermios *, speed_t , speed_t );
320 void uart_write_wakeup(struct uart_port *);
325 void uart_update_timeout(struct uart_port *, unsigned int, unsigned int);
327 unsigned int uart_get_baud_rate(struct uart_port *, struct ktermios *, struct ktermios *, unsigned int, unsigned int);
402 int uart_register_driver(struct uart_driver *);
403 void uart_unregister_driver(struct uart_driver *);
404 int uart_add_one_port(struct uart_driver *, struct uart_port *);
405 int uart_remove_one_port(struct uart_driver *, struct uart_port *);
423 int uart_tx_stopped(struct uart_port *port);
452 void uart_insert_char(struct uart_port *, unsigned int, unsigned int, unsigned int, unsigned int);
476 int uart_handle_break(struct uart_port *port);
13 void tty_flip_buffer_push(struct tty_port *);
52 struct resource * platform_get_resource(struct platform_device *, unsigned int, unsigned int);
54 int platform_get_irq(struct platform_device *, unsigned int);
211 void * platform_get_drvdata(const struct platform_device *pdev);
216 void platform_set_drvdata(struct platform_device *pdev, void *data);
183 struct regulator * devm_regulator_get(struct device *, const char *);
225 int regulator_enable(struct regulator *);
226 int regulator_disable(struct regulator *);
216 u8 sccnxp_read(struct uart_port *port, u8 reg);
221 void sccnxp_write(struct uart_port *port, u8 reg, u8 v);
226 u8 sccnxp_port_read(struct uart_port *port, u8 reg);
231 void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v);
236 int sccnxp_update_best_err(int a, int b, int *besterr);
253 const struct __anonstruct_baud_std_364 baud_std[29U] = { { 0U, 0U, 0U, 50 }, { 0U, 128U, 0U, 75 }, { 1U, 0U, 0U, 110 }, { 2U, 0U, 0U, 134 }, { 3U, 128U, 0U, 150 }, { 3U, 0U, 0U, 200 }, { 4U, 0U, 0U, 300 }, { 0U, 128U, 1U, 450 }, { 1U, 0U, 5U, 880 }, { 3U, 128U, 1U, 900 }, { 5U, 0U, 0U, 600 }, { 7U, 0U, 0U, 1050 }, { 2U, 0U, 5U, 1076 }, { 6U, 0U, 0U, 1200 }, { 10U, 128U, 0U, 1800 }, { 7U, 128U, 0U, 2000 }, { 8U, 0U, 0U, 2400 }, { 5U, 128U, 1U, 3600 }, { 9U, 0U, 0U, 4800 }, { 10U, 0U, 0U, 7200 }, { 11U, 0U, 0U, 9600 }, { 8U, 0U, 1U, 14400 }, { 12U, 128U, 0U, 19200 }, { 9U, 0U, 1U, 28800 }, { 12U, 0U, 0U, 38400 }, { 11U, 0U, 1U, 57600 }, { 12U, 128U, 1U, 115200 }, { 12U, 0U, 1U, 230400 }, { 0U, 0U, 0U, 0 } };
285 int sccnxp_set_baud(struct uart_port *port, int baud);
324 void sccnxp_enable_irq(struct uart_port *port, int mask);
332 void sccnxp_disable_irq(struct uart_port *port, int mask);
340 void sccnxp_set_bit(struct uart_port *port, int sig, int state);
354 void sccnxp_handle_rx(struct uart_port *port);
410 void sccnxp_handle_tx(struct uart_port *port);
449 void sccnxp_handle_events(struct sccnxp_port *s);
469 void sccnxp_timer(unsigned long data);
481 irqreturn_t sccnxp_ist(int irq, void *dev_id);
493 void sccnxp_start_tx(struct uart_port *port);
509 void sccnxp_stop_tx(struct uart_port *port);
514 void sccnxp_stop_rx(struct uart_port *port);
524 unsigned int sccnxp_tx_empty(struct uart_port *port);
537 void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl);
553 unsigned int sccnxp_get_mctrl(struct uart_port *port);
597 void sccnxp_break_ctl(struct uart_port *port, int break_state);
608 void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old);
695 int sccnxp_startup(struct uart_port *port);
726 void sccnxp_shutdown(struct uart_port *port);
748 const char * sccnxp_type(struct uart_port *port);
755 void sccnxp_release_port(struct uart_port *port);
760 int sccnxp_request_port(struct uart_port *port);
766 void sccnxp_config_port(struct uart_port *port, int flags);
772 int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s);
782 const struct uart_ops sccnxp_ops = { &sccnxp_tx_empty, &sccnxp_set_mctrl, &sccnxp_get_mctrl, &sccnxp_stop_tx, &sccnxp_start_tx, 0, 0, 0, &sccnxp_stop_rx, 0, &sccnxp_break_ctl, &sccnxp_startup, &sccnxp_shutdown, 0, &sccnxp_set_termios, 0, 0, &sccnxp_type, &sccnxp_release_port, &sccnxp_request_port, &sccnxp_config_port, &sccnxp_verify_port, 0, 0, 0, 0 };
849 const struct platform_device_id __mod_platform__sccnxp_id_table_device_table[9U] = { };
851 int sccnxp_probe(struct platform_device *pdev);
997 int sccnxp_remove(struct platform_device *pdev);
1048 void ldv_check_final_state();
1051 void ldv_check_return_value(int);
1054 void ldv_check_return_value_probe(int);
1057 void ldv_initialize();
1060 void ldv_handler_precall();
1063 int nondet_int();
1066 int LDV_IN_INTERRUPT = 0;
1069 void ldv_main0_sequence_infinite_withcheck_stateful();
10 void ldv_error();
25 int ldv_undef_int();
14 void * ldv_err_ptr(long error);
28 bool ldv_is_err_or_null(const void *ptr);
9 int ldv_counter_clk = 0;
return ;
}
-entry_point
{
1071 struct uart_port *var_group1;
1072 unsigned int var_sccnxp_set_mctrl_18_p1;
1073 int var_sccnxp_break_ctl_20_p1;
1074 struct ktermios *var_group2;
1075 struct ktermios *var_sccnxp_set_termios_21_p2;
1076 int var_sccnxp_config_port_27_p1;
1077 struct serial_struct *var_group3;
1078 struct platform_device *var_group4;
1079 int res_sccnxp_probe_32;
1080 int var_sccnxp_ist_13_p0;
1081 void *var_sccnxp_ist_13_p1;
1082 int ldv_s_sccnxp_uart_driver_platform_driver;
1083 int tmp;
1084 int tmp___0;
2501 ldv_s_sccnxp_uart_driver_platform_driver = 0;
2489 LDV_IN_INTERRUPT = 1;
2498 ldv_initialize() { /* Function call is skipped due to function is undefined */}
2506 goto ldv_31265;
2506 tmp___0 = nondet_int() { /* Function call is skipped due to function is undefined */}
2506 assume(tmp___0 != 0);
2509 goto ldv_31264;
2507 ldv_31264:;
2510 tmp = nondet_int() { /* Function call is skipped due to function is undefined */}
2510 switch (tmp);
2511 assume(!(tmp == 0));
2604 assume(!(tmp == 1));
2696 assume(!(tmp == 2));
2788 assume(!(tmp == 3));
2880 assume(!(tmp == 4));
2972 assume(!(tmp == 5));
3064 assume(!(tmp == 6));
3156 assume(!(tmp == 7));
3248 assume(!(tmp == 8));
3340 assume(!(tmp == 9));
3432 assume(!(tmp == 10));
3524 assume(!(tmp == 11));
3616 assume(!(tmp == 12));
3708 assume(!(tmp == 13));
3800 assume(!(tmp == 14));
3892 assume(tmp == 15);
3895 assume(ldv_s_sccnxp_uart_driver_platform_driver == 0);
3971 -sccnxp_probe(var_group4)
{
853 struct resource *res;
854 struct resource *tmp;
855 struct sccnxp_pdata *pdata;
856 void *tmp___0;
857 int i;
858 int ret;
859 int uartclk;
860 struct sccnxp_port *s;
861 void *membase;
862 struct clk *clk;
863 long tmp___1;
864 _Bool tmp___2;
865 void *tmp___3;
866 struct lock_class_key __key;
867 long tmp___4;
868 _Bool tmp___5;
869 int tmp___6;
870 long tmp___7;
871 unsigned long tmp___8;
872 _Bool tmp___9;
873 const char *tmp___10;
874 struct lock_class_key __key___0;
875 struct lock_class_key __key___1;
876 unsigned long tmp___11;
877 int tmp___12;
878 _Bool tmp___13;
879 int tmp___14;
853 tmp = platform_get_resource(pdev, 512U, 0U) { /* Function call is skipped due to function is undefined */}
853 res = tmp;
854 -dev_get_platdata((const struct device *)(&(pdev->dev)))
{
1169 void *__CPAchecker_TMP_0 = (void *)(dev->platform_data);
1169 return __CPAchecker_TMP_0;;
}
854 pdata = (struct sccnxp_pdata *)tmp___0;
860 membase = devm_ioremap_resource(&(pdev->dev), res) { /* Function call is skipped due to function is undefined */}
861 -IS_ERR((const void *)membase)
{
28 _Bool tmp;
29 -ldv_is_err(ptr)
{
10 return ((unsigned long)ptr) > 2012UL;;
}
29 return tmp;;
}
861 assume(((int)tmp___2) == 0);
864 -devm_kzalloc(&(pdev->dev), 1200UL, 20971712U)
{
664 void *tmp;
664 tmp = devm_kmalloc(dev, size, gfp | 32768U) { /* Function call is skipped due to function is undefined */}
664 return tmp;;
}
864 s = (struct sccnxp_port *)tmp___3;
865 assume(!(((unsigned long)s) == ((unsigned long)((struct sccnxp_port *)0))));
869 -platform_set_drvdata(pdev, (void *)s)
{
219 -dev_set_drvdata(&(pdev->dev), data)
{
1032 dev->driver_data = data;
1033 return ;;
}
220 return ;;
}
871 -spinlock_check(&(s->lock))
{
288 return &(lock->__annonCompField21.rlock);;
}
871 __raw_spin_lock_init(&(s->lock.__annonCompField21.rlock), "&(&s->lock)->rlock", &__key) { /* Function call is skipped due to function is undefined */}
873 struct sccnxp_chip *__CPAchecker_TMP_0 = (struct sccnxp_chip *)(pdev->id_entry->driver_data);
873 s->chip = __CPAchecker_TMP_0;
875 s->regulator = devm_regulator_get(&(pdev->dev), "vcc") { /* Function call is skipped due to function is undefined */}
876 const void *__CPAchecker_TMP_1 = (const void *)(s->regulator);
876 -IS_ERR(__CPAchecker_TMP_1)
{
28 _Bool tmp;
29 -ldv_is_err(ptr)
{
10 return ((unsigned long)ptr) > 2012UL;;
}
29 return tmp;;
}
876 assume(tmp___5 == 0);
876 tmp___6 = 1;
876 assume(!(tmp___6 == 0));
877 ret = regulator_enable(s->regulator) { /* Function call is skipped due to function is undefined */}
878 assume(!(ret != 0));
886 clk = devm_clk_get(&(pdev->dev), (const char *)0) { /* Function call is skipped due to function is undefined */}
887 -IS_ERR((const void *)clk)
{
28 _Bool tmp;
29 -ldv_is_err(ptr)
{
10 return ((unsigned long)ptr) > 2012UL;;
}
29 return tmp;;
}
887 assume(((int)tmp___9) == 0);
893 -ldv_clk_prepare_enable_7(clk)
{
52 int tmp;
53 -ldv_clk_enable_clk()
{
21 int retval;
22 int tmp;
21 tmp = ldv_undef_int() { /* Function call is skipped due to function is undefined */}
21 retval = tmp;
22 assume(retval == 0);
25 ldv_counter_clk = 1;
27 return retval;;
}
53 return tmp;;
}
894 tmp___8 = clk_get_rate(clk) { /* Function call is skipped due to function is undefined */}
894 uartclk = (int)tmp___8;
897 assume(!(uartclk == 0));
903 assume(!(((unsigned long)uartclk) < (s->chip->freq_min)));
903 assume(!(((unsigned long)uartclk) > (s->chip->freq_max)));
909 assume(((unsigned long)pdata) != ((unsigned long)((struct sccnxp_pdata *)0)));
910 __memcpy((void *)(&(s->pdata)), (const void *)pdata, 16UL) { /* Function call is skipped due to function is undefined */}
912 assume(!(((unsigned int)(s->pdata.poll_time_us)) != 0U));
918 assume((s->poll) == 0);
919 s->irq = platform_get_irq(pdev, 0U) { /* Function call is skipped due to function is undefined */}
920 assume(!((s->irq) < 0));
927 s->uart.owner = &__this_module;
928 s->uart.dev_name = "ttySC";
929 s->uart.major = 204;
930 s->uart.minor = 205;
931 int __CPAchecker_TMP_4 = (int)(s->chip->nr);
931 s->uart.nr = __CPAchecker_TMP_4;
942 ret = uart_register_driver(&(s->uart)) { /* Function call is skipped due to function is undefined */}
943 assume(!(ret != 0));
948 i = 0;
948 goto ldv_31183;
948 assume(!((s->uart.nr) > i));
968 s->imr = 0U;
969 -sccnxp_write((struct uart_port *)(&(s->port)), 5, 0)
{
223 volatile void *__CPAchecker_TMP_0 = (volatile void *)(port->membase);
223 int __CPAchecker_TMP_1 = (int)(port->regshift);
223 -writeb((int)v, __CPAchecker_TMP_0 + ((unsigned long)(((int)reg) << __CPAchecker_TMP_1)))
{
64 Ignored inline assembler code
65 return ;;
}
224 return ;;
}
971 assume((s->poll) == 0);
972 -dev_name((const struct device *)(&(pdev->dev)))
{
980 const char *tmp;
981 unsigned long __CPAchecker_TMP_0 = (unsigned long)(dev->init_name);
981 assume(!(__CPAchecker_TMP_0 != ((unsigned long)((const char *)0))));
984 -kobject_name(&(dev->kobj))
{
89 const char *__CPAchecker_TMP_0 = (const char *)(kobj->name);
89 return __CPAchecker_TMP_0;;
}
984 return tmp;;
}
972 unsigned int __CPAchecker_TMP_7 = (unsigned int)(s->irq);
972 ret = devm_request_threaded_irq(&(pdev->dev), __CPAchecker_TMP_7, (irqreturn_t (*)(int, void *))0, &sccnxp_ist, 8194UL, tmp___10, (void *)s) { /* Function call is skipped due to function is undefined */}
977 assume(!(ret == 0));
980 dev_err((const struct device *)(&(pdev->dev)), "Unable to reguest IRQ %i\n", s->irq) { /* Function call is skipped due to function is undefined */}
989 uart_unregister_driver(&(s->uart)) { /* Function call is skipped due to function is undefined */}
990 err_out:;
991 const void *__CPAchecker_TMP_8 = (const void *)(s->regulator);
991 -IS_ERR(__CPAchecker_TMP_8)
{
28 _Bool tmp;
29 -ldv_is_err(ptr)
{
10 return ((unsigned long)ptr) > 2012UL;;
}
29 return tmp;;
}
991 assume(tmp___13 == 0);
991 tmp___14 = 1;
991 assume(!(tmp___14 == 0));
992 tmp___12 = regulator_disable(s->regulator) { /* Function call is skipped due to function is undefined */}
992 return tmp___12;;
}
3972 ldv_check_return_value(res_sccnxp_probe_32) { /* Function call is skipped due to function is undefined */}
3973 ldv_check_return_value_probe(res_sccnxp_probe_32) { /* Function call is skipped due to function is undefined */}
3974 assume(res_sccnxp_probe_32 != 0);
3975 goto ldv_module_exit;
4174 -ldv_check_final_state()
{
35 assume(ldv_counter_clk != 0);
35 -ldv_error()
{
15 LDV_ERROR:;
}
}
}
Source code
1 #ifndef _ASM_X86_IO_H 2 #define _ASM_X86_IO_H 3 4 /* 5 * This file contains the definitions for the x86 IO instructions 6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same 7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" 8 * versions of the single-IO instructions (inb_p/inw_p/..). 9 * 10 * This file is not meant to be obfuscating: it's just complicated 11 * to (a) handle it all in a way that makes gcc able to optimize it 12 * as well as possible and (b) trying to avoid writing the same thing 13 * over and over again with slight variations and possibly making a 14 * mistake somewhere. 15 */ 16 17 /* 18 * Thanks to James van Artsdalen for a better timing-fix than 19 * the two short jumps: using outb's to a nonexistent port seems 20 * to guarantee better timings even on fast machines. 21 * 22 * On the other hand, I'd like to be sure of a non-existent port: 23 * I feel a bit unsafe about using 0x80 (should be safe, though) 24 * 25 * Linus 26 */ 27 28 /* 29 * Bit simplified and optimized by Jan Hubicka 30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. 31 * 32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, 33 * isa_read[wl] and isa_write[wl] fixed 34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> 35 */ 36 37 #define ARCH_HAS_IOREMAP_WC 38 #define ARCH_HAS_IOREMAP_WT 39 40 #include <linux/string.h> 41 #include <linux/compiler.h> 42 #include <asm/page.h> 43 #include <asm/early_ioremap.h> 44 #include <asm/pgtable_types.h> 45 46 #define build_mmio_read(name, size, type, reg, barrier) \ 47 static inline type name(const volatile void __iomem *addr) \ 48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 49 :"m" (*(volatile type __force *)addr) barrier); return ret; } 50 51 #define build_mmio_write(name, size, type, reg, barrier) \ 52 static inline void name(type val, volatile void __iomem *addr) \ 53 { asm volatile("mov" size " %0,%1": :reg (val), \ 54 "m" (*(volatile type __force *)addr) barrier); } 55 56 build_mmio_read(readb, "b", unsigned char, "=q", :"memory") 57 build_mmio_read(readw, "w", unsigned short, "=r", :"memory") 58 build_mmio_read(readl, "l", unsigned int, "=r", :"memory") 59 60 build_mmio_read(__readb, "b", unsigned char, "=q", ) 61 build_mmio_read(__readw, "w", unsigned short, "=r", ) 62 build_mmio_read(__readl, "l", unsigned int, "=r", ) 63 64 build_mmio_write(writeb, "b", unsigned char, "q", :"memory") 65 build_mmio_write(writew, "w", unsigned short, "r", :"memory") 66 build_mmio_write(writel, "l", unsigned int, "r", :"memory") 67 68 build_mmio_write(__writeb, "b", unsigned char, "q", ) 69 build_mmio_write(__writew, "w", unsigned short, "r", ) 70 build_mmio_write(__writel, "l", unsigned int, "r", ) 71 72 #define readb_relaxed(a) __readb(a) 73 #define readw_relaxed(a) __readw(a) 74 #define readl_relaxed(a) __readl(a) 75 #define __raw_readb __readb 76 #define __raw_readw __readw 77 #define __raw_readl __readl 78 79 #define writeb_relaxed(v, a) __writeb(v, a) 80 #define writew_relaxed(v, a) __writew(v, a) 81 #define writel_relaxed(v, a) __writel(v, a) 82 #define __raw_writeb __writeb 83 #define __raw_writew __writew 84 #define __raw_writel __writel 85 86 #define mmiowb() barrier() 87 88 #ifdef CONFIG_X86_64 89 90 build_mmio_read(readq, "q", unsigned long, "=r", :"memory") 91 build_mmio_write(writeq, "q", unsigned long, "r", :"memory") 92 93 #define readq_relaxed(a) readq(a) 94 #define writeq_relaxed(v, a) writeq(v, a) 95 96 #define __raw_readq(a) readq(a) 97 #define __raw_writeq(val, addr) writeq(val, addr) 98 99 /* Let people know that we have them */ 100 #define readq readq 101 #define writeq writeq 102 103 #endif 104 105 /** 106 * virt_to_phys - map virtual addresses to physical 107 * @address: address to remap 108 * 109 * The returned physical address is the physical (CPU) mapping for 110 * the memory address given. It is only valid to use this function on 111 * addresses directly mapped or allocated via kmalloc. 112 * 113 * This function does not give bus mappings for DMA transfers. In 114 * almost all conceivable cases a device driver should not be using 115 * this function 116 */ 117 118 static inline phys_addr_t virt_to_phys(volatile void *address) 119 { 120 return __pa(address); 121 } 122 123 /** 124 * phys_to_virt - map physical address to virtual 125 * @address: address to remap 126 * 127 * The returned virtual address is a current CPU mapping for 128 * the memory address given. It is only valid to use this function on 129 * addresses that have a kernel mapping 130 * 131 * This function does not handle bus mappings for DMA transfers. In 132 * almost all conceivable cases a device driver should not be using 133 * this function 134 */ 135 136 static inline void *phys_to_virt(phys_addr_t address) 137 { 138 return __va(address); 139 } 140 141 /* 142 * Change "struct page" to physical address. 143 */ 144 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 145 146 /* 147 * ISA I/O bus memory addresses are 1:1 with the physical address. 148 * However, we truncate the address to unsigned int to avoid undesirable 149 * promitions in legacy drivers. 150 */ 151 static inline unsigned int isa_virt_to_bus(volatile void *address) 152 { 153 return (unsigned int)virt_to_phys(address); 154 } 155 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) 156 #define isa_bus_to_virt phys_to_virt 157 158 /* 159 * However PCI ones are not necessarily 1:1 and therefore these interfaces 160 * are forbidden in portable PCI drivers. 161 * 162 * Allow them on x86 for legacy drivers, though. 163 */ 164 #define virt_to_bus virt_to_phys 165 #define bus_to_virt phys_to_virt 166 167 /* 168 * The default ioremap() behavior is non-cached; if you need something 169 * else, you probably want one of the following. 170 */ 171 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); 172 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); 173 #define ioremap_uc ioremap_uc 174 175 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); 176 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val); 177 178 /** 179 * ioremap - map bus memory into CPU space 180 * @offset: bus address of the memory 181 * @size: size of the resource to map 182 * 183 * ioremap performs a platform specific sequence of operations to 184 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 185 * writew/writel functions and the other mmio helpers. The returned 186 * address is not guaranteed to be usable directly as a virtual 187 * address. 188 * 189 * If the area you are trying to map is a PCI BAR you should have a 190 * look at pci_iomap(). 191 */ 192 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) 193 { 194 return ioremap_nocache(offset, size); 195 } 196 197 extern void iounmap(volatile void __iomem *addr); 198 199 extern void set_iounmap_nonlazy(void); 200 201 #ifdef __KERNEL__ 202 203 #include <asm-generic/iomap.h> 204 205 /* 206 * Convert a virtual cached pointer to an uncached pointer 207 */ 208 #define xlate_dev_kmem_ptr(p) p 209 210 /** 211 * memset_io Set a range of I/O memory to a constant value 212 * @addr: The beginning of the I/O-memory range to set 213 * @val: The value to set the memory to 214 * @count: The number of bytes to set 215 * 216 * Set a range of I/O memory to a given value. 217 */ 218 static inline void 219 memset_io(volatile void __iomem *addr, unsigned char val, size_t count) 220 { 221 memset((void __force *)addr, val, count); 222 } 223 224 /** 225 * memcpy_fromio Copy a block of data from I/O memory 226 * @dst: The (RAM) destination for the copy 227 * @src: The (I/O memory) source for the data 228 * @count: The number of bytes to copy 229 * 230 * Copy a block of data from I/O memory. 231 */ 232 static inline void 233 memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count) 234 { 235 memcpy(dst, (const void __force *)src, count); 236 } 237 238 /** 239 * memcpy_toio Copy a block of data into I/O memory 240 * @dst: The (I/O memory) destination for the copy 241 * @src: The (RAM) source for the data 242 * @count: The number of bytes to copy 243 * 244 * Copy a block of data to I/O memory. 245 */ 246 static inline void 247 memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) 248 { 249 memcpy((void __force *)dst, src, count); 250 } 251 252 /* 253 * ISA space is 'always mapped' on a typical x86 system, no need to 254 * explicitly ioremap() it. The fact that the ISA IO space is mapped 255 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values 256 * are physical addresses. The following constant pointer can be 257 * used as the IO-area pointer (it can be iounmapped as well, so the 258 * analogy with PCI is quite large): 259 */ 260 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) 261 262 /* 263 * Cache management 264 * 265 * This needed for two cases 266 * 1. Out of order aware processors 267 * 2. Accidentally out of order processors (PPro errata #51) 268 */ 269 270 static inline void flush_write_buffers(void) 271 { 272 #if defined(CONFIG_X86_PPRO_FENCE) 273 asm volatile("lock; addl $0,0(%%esp)": : :"memory"); 274 #endif 275 } 276 277 #endif /* __KERNEL__ */ 278 279 extern void native_io_delay(void); 280 281 extern int io_delay_type; 282 extern void io_delay_init(void); 283 284 #if defined(CONFIG_PARAVIRT) 285 #include <asm/paravirt.h> 286 #else 287 288 static inline void slow_down_io(void) 289 { 290 native_io_delay(); 291 #ifdef REALLY_SLOW_IO 292 native_io_delay(); 293 native_io_delay(); 294 native_io_delay(); 295 #endif 296 } 297 298 #endif 299 300 #define BUILDIO(bwl, bw, type) \ 301 static inline void out##bwl(unsigned type value, int port) \ 302 { \ 303 asm volatile("out" #bwl " %" #bw "0, %w1" \ 304 : : "a"(value), "Nd"(port)); \ 305 } \ 306 \ 307 static inline unsigned type in##bwl(int port) \ 308 { \ 309 unsigned type value; \ 310 asm volatile("in" #bwl " %w1, %" #bw "0" \ 311 : "=a"(value) : "Nd"(port)); \ 312 return value; \ 313 } \ 314 \ 315 static inline void out##bwl##_p(unsigned type value, int port) \ 316 { \ 317 out##bwl(value, port); \ 318 slow_down_io(); \ 319 } \ 320 \ 321 static inline unsigned type in##bwl##_p(int port) \ 322 { \ 323 unsigned type value = in##bwl(port); \ 324 slow_down_io(); \ 325 return value; \ 326 } \ 327 \ 328 static inline void outs##bwl(int port, const void *addr, unsigned long count) \ 329 { \ 330 asm volatile("rep; outs" #bwl \ 331 : "+S"(addr), "+c"(count) : "d"(port)); \ 332 } \ 333 \ 334 static inline void ins##bwl(int port, void *addr, unsigned long count) \ 335 { \ 336 asm volatile("rep; ins" #bwl \ 337 : "+D"(addr), "+c"(count) : "d"(port)); \ 338 } 339 340 BUILDIO(b, b, char) 341 BUILDIO(w, w, short) 342 BUILDIO(l, , int) 343 344 extern void *xlate_dev_mem_ptr(phys_addr_t phys); 345 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); 346 347 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, 348 enum page_cache_mode pcm); 349 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); 350 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); 351 352 extern bool is_early_ioremap_ptep(pte_t *ptep); 353 354 #ifdef CONFIG_XEN 355 #include <xen/xen.h> 356 struct bio_vec; 357 358 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 359 const struct bio_vec *vec2); 360 361 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ 362 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ 363 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) 364 #endif /* CONFIG_XEN */ 365 366 #define IO_SPACE_LIMIT 0xffff 367 368 #ifdef CONFIG_MTRR 369 extern int __must_check arch_phys_wc_index(int handle); 370 #define arch_phys_wc_index arch_phys_wc_index 371 372 extern int __must_check arch_phys_wc_add(unsigned long base, 373 unsigned long size); 374 extern void arch_phys_wc_del(int handle); 375 #define arch_phys_wc_add arch_phys_wc_add 376 #endif 377 378 #ifdef CONFIG_X86_PAT 379 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); 380 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); 381 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc 382 #endif 383 384 #endif /* _ASM_X86_IO_H */
1 2 /* 3 * NXP (Philips) SCC+++(SCN+++) serial driver 4 * 5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 16 #define SUPPORT_SYSRQ 17 #endif 18 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/module.h> 22 #include <linux/device.h> 23 #include <linux/console.h> 24 #include <linux/serial_core.h> 25 #include <linux/serial.h> 26 #include <linux/io.h> 27 #include <linux/tty.h> 28 #include <linux/tty_flip.h> 29 #include <linux/spinlock.h> 30 #include <linux/platform_device.h> 31 #include <linux/platform_data/serial-sccnxp.h> 32 #include <linux/regulator/consumer.h> 33 34 #define SCCNXP_NAME "uart-sccnxp" 35 #define SCCNXP_MAJOR 204 36 #define SCCNXP_MINOR 205 37 38 #define SCCNXP_MR_REG (0x00) 39 # define MR0_BAUD_NORMAL (0 << 0) 40 # define MR0_BAUD_EXT1 (1 << 0) 41 # define MR0_BAUD_EXT2 (5 << 0) 42 # define MR0_FIFO (1 << 3) 43 # define MR0_TXLVL (1 << 4) 44 # define MR1_BITS_5 (0 << 0) 45 # define MR1_BITS_6 (1 << 0) 46 # define MR1_BITS_7 (2 << 0) 47 # define MR1_BITS_8 (3 << 0) 48 # define MR1_PAR_EVN (0 << 2) 49 # define MR1_PAR_ODD (1 << 2) 50 # define MR1_PAR_NO (4 << 2) 51 # define MR2_STOP1 (7 << 0) 52 # define MR2_STOP2 (0xf << 0) 53 #define SCCNXP_SR_REG (0x01) 54 #define SCCNXP_CSR_REG SCCNXP_SR_REG 55 # define SR_RXRDY (1 << 0) 56 # define SR_FULL (1 << 1) 57 # define SR_TXRDY (1 << 2) 58 # define SR_TXEMT (1 << 3) 59 # define SR_OVR (1 << 4) 60 # define SR_PE (1 << 5) 61 # define SR_FE (1 << 6) 62 # define SR_BRK (1 << 7) 63 #define SCCNXP_CR_REG (0x02) 64 # define CR_RX_ENABLE (1 << 0) 65 # define CR_RX_DISABLE (1 << 1) 66 # define CR_TX_ENABLE (1 << 2) 67 # define CR_TX_DISABLE (1 << 3) 68 # define CR_CMD_MRPTR1 (0x01 << 4) 69 # define CR_CMD_RX_RESET (0x02 << 4) 70 # define CR_CMD_TX_RESET (0x03 << 4) 71 # define CR_CMD_STATUS_RESET (0x04 << 4) 72 # define CR_CMD_BREAK_RESET (0x05 << 4) 73 # define CR_CMD_START_BREAK (0x06 << 4) 74 # define CR_CMD_STOP_BREAK (0x07 << 4) 75 # define CR_CMD_MRPTR0 (0x0b << 4) 76 #define SCCNXP_RHR_REG (0x03) 77 #define SCCNXP_THR_REG SCCNXP_RHR_REG 78 #define SCCNXP_IPCR_REG (0x04) 79 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 80 # define ACR_BAUD0 (0 << 7) 81 # define ACR_BAUD1 (1 << 7) 82 # define ACR_TIMER_MODE (6 << 4) 83 #define SCCNXP_ISR_REG (0x05) 84 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 85 # define IMR_TXRDY (1 << 0) 86 # define IMR_RXRDY (1 << 1) 87 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 88 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 89 #define SCCNXP_IPR_REG (0x0d) 90 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 91 #define SCCNXP_SOP_REG (0x0e) 92 #define SCCNXP_ROP_REG (0x0f) 93 94 /* Route helpers */ 95 #define MCTRL_MASK(sig) (0xf << (sig)) 96 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 97 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 98 99 #define SCCNXP_HAVE_IO 0x00000001 100 #define SCCNXP_HAVE_MR0 0x00000002 101 102 struct sccnxp_chip { 103 const char *name; 104 unsigned int nr; 105 unsigned long freq_min; 106 unsigned long freq_std; 107 unsigned long freq_max; 108 unsigned int flags; 109 unsigned int fifosize; 110 }; 111 112 struct sccnxp_port { 113 struct uart_driver uart; 114 struct uart_port port[SCCNXP_MAX_UARTS]; 115 bool opened[SCCNXP_MAX_UARTS]; 116 117 int irq; 118 u8 imr; 119 120 struct sccnxp_chip *chip; 121 122 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 123 struct console console; 124 #endif 125 126 spinlock_t lock; 127 128 bool poll; 129 struct timer_list timer; 130 131 struct sccnxp_pdata pdata; 132 133 struct regulator *regulator; 134 }; 135 136 static const struct sccnxp_chip sc2681 = { 137 .name = "SC2681", 138 .nr = 2, 139 .freq_min = 1000000, 140 .freq_std = 3686400, 141 .freq_max = 4000000, 142 .flags = SCCNXP_HAVE_IO, 143 .fifosize = 3, 144 }; 145 146 static const struct sccnxp_chip sc2691 = { 147 .name = "SC2691", 148 .nr = 1, 149 .freq_min = 1000000, 150 .freq_std = 3686400, 151 .freq_max = 4000000, 152 .flags = 0, 153 .fifosize = 3, 154 }; 155 156 static const struct sccnxp_chip sc2692 = { 157 .name = "SC2692", 158 .nr = 2, 159 .freq_min = 1000000, 160 .freq_std = 3686400, 161 .freq_max = 4000000, 162 .flags = SCCNXP_HAVE_IO, 163 .fifosize = 3, 164 }; 165 166 static const struct sccnxp_chip sc2891 = { 167 .name = "SC2891", 168 .nr = 1, 169 .freq_min = 100000, 170 .freq_std = 3686400, 171 .freq_max = 8000000, 172 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 173 .fifosize = 16, 174 }; 175 176 static const struct sccnxp_chip sc2892 = { 177 .name = "SC2892", 178 .nr = 2, 179 .freq_min = 100000, 180 .freq_std = 3686400, 181 .freq_max = 8000000, 182 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 183 .fifosize = 16, 184 }; 185 186 static const struct sccnxp_chip sc28202 = { 187 .name = "SC28202", 188 .nr = 2, 189 .freq_min = 1000000, 190 .freq_std = 14745600, 191 .freq_max = 50000000, 192 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 193 .fifosize = 256, 194 }; 195 196 static const struct sccnxp_chip sc68681 = { 197 .name = "SC68681", 198 .nr = 2, 199 .freq_min = 1000000, 200 .freq_std = 3686400, 201 .freq_max = 4000000, 202 .flags = SCCNXP_HAVE_IO, 203 .fifosize = 3, 204 }; 205 206 static const struct sccnxp_chip sc68692 = { 207 .name = "SC68692", 208 .nr = 2, 209 .freq_min = 1000000, 210 .freq_std = 3686400, 211 .freq_max = 4000000, 212 .flags = SCCNXP_HAVE_IO, 213 .fifosize = 3, 214 }; 215 216 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 217 { 218 return readb(port->membase + (reg << port->regshift)); 219 } 220 221 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 222 { 223 writeb(v, port->membase + (reg << port->regshift)); 224 } 225 226 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 227 { 228 return sccnxp_read(port, (port->line << 3) + reg); 229 } 230 231 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 232 { 233 sccnxp_write(port, (port->line << 3) + reg, v); 234 } 235 236 static int sccnxp_update_best_err(int a, int b, int *besterr) 237 { 238 int err = abs(a - b); 239 240 if ((*besterr < 0) || (*besterr > err)) { 241 *besterr = err; 242 return 0; 243 } 244 245 return 1; 246 } 247 248 static const struct { 249 u8 csr; 250 u8 acr; 251 u8 mr0; 252 int baud; 253 } baud_std[] = { 254 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 255 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 256 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 257 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 258 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 259 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 260 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 261 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 262 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 263 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 264 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 265 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 266 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 267 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 268 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 269 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 270 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 271 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 272 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 273 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 274 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 275 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 276 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 277 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 278 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 279 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 280 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 281 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 282 { 0, 0, 0, 0 } 283 }; 284 285 static int sccnxp_set_baud(struct uart_port *port, int baud) 286 { 287 struct sccnxp_port *s = dev_get_drvdata(port->dev); 288 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 289 struct sccnxp_chip *chip = s->chip; 290 u8 i, acr = 0, csr = 0, mr0 = 0; 291 292 /* Find best baud from table */ 293 for (i = 0; baud_std[i].baud && besterr; i++) { 294 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0)) 295 continue; 296 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud); 297 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 298 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 299 acr = baud_std[i].acr; 300 csr = baud_std[i].csr; 301 mr0 = baud_std[i].mr0; 302 bestbaud = tmp_baud; 303 } 304 } 305 306 if (chip->flags & SCCNXP_HAVE_MR0) { 307 /* Enable FIFO, set half level for TX */ 308 mr0 |= MR0_FIFO | MR0_TXLVL; 309 /* Update MR0 */ 310 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 311 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 312 } 313 314 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 315 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 316 317 if (baud != bestbaud) 318 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 319 baud, bestbaud); 320 321 return bestbaud; 322 } 323 324 static void sccnxp_enable_irq(struct uart_port *port, int mask) 325 { 326 struct sccnxp_port *s = dev_get_drvdata(port->dev); 327 328 s->imr |= mask << (port->line * 4); 329 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 330 } 331 332 static void sccnxp_disable_irq(struct uart_port *port, int mask) 333 { 334 struct sccnxp_port *s = dev_get_drvdata(port->dev); 335 336 s->imr &= ~(mask << (port->line * 4)); 337 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 338 } 339 340 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 341 { 342 u8 bitmask; 343 struct sccnxp_port *s = dev_get_drvdata(port->dev); 344 345 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 346 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 347 if (state) 348 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 349 else 350 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 351 } 352 } 353 354 static void sccnxp_handle_rx(struct uart_port *port) 355 { 356 u8 sr; 357 unsigned int ch, flag; 358 359 for (;;) { 360 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 361 if (!(sr & SR_RXRDY)) 362 break; 363 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 364 365 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 366 367 port->icount.rx++; 368 flag = TTY_NORMAL; 369 370 if (unlikely(sr)) { 371 if (sr & SR_BRK) { 372 port->icount.brk++; 373 sccnxp_port_write(port, SCCNXP_CR_REG, 374 CR_CMD_BREAK_RESET); 375 if (uart_handle_break(port)) 376 continue; 377 } else if (sr & SR_PE) 378 port->icount.parity++; 379 else if (sr & SR_FE) 380 port->icount.frame++; 381 else if (sr & SR_OVR) { 382 port->icount.overrun++; 383 sccnxp_port_write(port, SCCNXP_CR_REG, 384 CR_CMD_STATUS_RESET); 385 } 386 387 sr &= port->read_status_mask; 388 if (sr & SR_BRK) 389 flag = TTY_BREAK; 390 else if (sr & SR_PE) 391 flag = TTY_PARITY; 392 else if (sr & SR_FE) 393 flag = TTY_FRAME; 394 else if (sr & SR_OVR) 395 flag = TTY_OVERRUN; 396 } 397 398 if (uart_handle_sysrq_char(port, ch)) 399 continue; 400 401 if (sr & port->ignore_status_mask) 402 continue; 403 404 uart_insert_char(port, sr, SR_OVR, ch, flag); 405 } 406 407 tty_flip_buffer_push(&port->state->port); 408 } 409 410 static void sccnxp_handle_tx(struct uart_port *port) 411 { 412 u8 sr; 413 struct circ_buf *xmit = &port->state->xmit; 414 struct sccnxp_port *s = dev_get_drvdata(port->dev); 415 416 if (unlikely(port->x_char)) { 417 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 418 port->icount.tx++; 419 port->x_char = 0; 420 return; 421 } 422 423 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 424 /* Disable TX if FIFO is empty */ 425 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 426 sccnxp_disable_irq(port, IMR_TXRDY); 427 428 /* Set direction to input */ 429 if (s->chip->flags & SCCNXP_HAVE_IO) 430 sccnxp_set_bit(port, DIR_OP, 0); 431 } 432 return; 433 } 434 435 while (!uart_circ_empty(xmit)) { 436 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 437 if (!(sr & SR_TXRDY)) 438 break; 439 440 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 442 port->icount.tx++; 443 } 444 445 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 446 uart_write_wakeup(port); 447 } 448 449 static void sccnxp_handle_events(struct sccnxp_port *s) 450 { 451 int i; 452 u8 isr; 453 454 do { 455 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 456 isr &= s->imr; 457 if (!isr) 458 break; 459 460 for (i = 0; i < s->uart.nr; i++) { 461 if (s->opened[i] && (isr & ISR_RXRDY(i))) 462 sccnxp_handle_rx(&s->port[i]); 463 if (s->opened[i] && (isr & ISR_TXRDY(i))) 464 sccnxp_handle_tx(&s->port[i]); 465 } 466 } while (1); 467 } 468 469 static void sccnxp_timer(unsigned long data) 470 { 471 struct sccnxp_port *s = (struct sccnxp_port *)data; 472 unsigned long flags; 473 474 spin_lock_irqsave(&s->lock, flags); 475 sccnxp_handle_events(s); 476 spin_unlock_irqrestore(&s->lock, flags); 477 478 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us)); 479 } 480 481 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 482 { 483 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 484 unsigned long flags; 485 486 spin_lock_irqsave(&s->lock, flags); 487 sccnxp_handle_events(s); 488 spin_unlock_irqrestore(&s->lock, flags); 489 490 return IRQ_HANDLED; 491 } 492 493 static void sccnxp_start_tx(struct uart_port *port) 494 { 495 struct sccnxp_port *s = dev_get_drvdata(port->dev); 496 unsigned long flags; 497 498 spin_lock_irqsave(&s->lock, flags); 499 500 /* Set direction to output */ 501 if (s->chip->flags & SCCNXP_HAVE_IO) 502 sccnxp_set_bit(port, DIR_OP, 1); 503 504 sccnxp_enable_irq(port, IMR_TXRDY); 505 506 spin_unlock_irqrestore(&s->lock, flags); 507 } 508 509 static void sccnxp_stop_tx(struct uart_port *port) 510 { 511 /* Do nothing */ 512 } 513 514 static void sccnxp_stop_rx(struct uart_port *port) 515 { 516 struct sccnxp_port *s = dev_get_drvdata(port->dev); 517 unsigned long flags; 518 519 spin_lock_irqsave(&s->lock, flags); 520 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 521 spin_unlock_irqrestore(&s->lock, flags); 522 } 523 524 static unsigned int sccnxp_tx_empty(struct uart_port *port) 525 { 526 u8 val; 527 unsigned long flags; 528 struct sccnxp_port *s = dev_get_drvdata(port->dev); 529 530 spin_lock_irqsave(&s->lock, flags); 531 val = sccnxp_port_read(port, SCCNXP_SR_REG); 532 spin_unlock_irqrestore(&s->lock, flags); 533 534 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 535 } 536 537 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 538 { 539 struct sccnxp_port *s = dev_get_drvdata(port->dev); 540 unsigned long flags; 541 542 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 543 return; 544 545 spin_lock_irqsave(&s->lock, flags); 546 547 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 548 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 549 550 spin_unlock_irqrestore(&s->lock, flags); 551 } 552 553 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 554 { 555 u8 bitmask, ipr; 556 unsigned long flags; 557 struct sccnxp_port *s = dev_get_drvdata(port->dev); 558 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 559 560 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 561 return mctrl; 562 563 spin_lock_irqsave(&s->lock, flags); 564 565 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 566 567 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 568 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 569 DSR_IP); 570 mctrl &= ~TIOCM_DSR; 571 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 572 } 573 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 574 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 575 CTS_IP); 576 mctrl &= ~TIOCM_CTS; 577 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 578 } 579 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 580 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 581 DCD_IP); 582 mctrl &= ~TIOCM_CAR; 583 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 584 } 585 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 586 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 587 RNG_IP); 588 mctrl &= ~TIOCM_RNG; 589 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 590 } 591 592 spin_unlock_irqrestore(&s->lock, flags); 593 594 return mctrl; 595 } 596 597 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 598 { 599 struct sccnxp_port *s = dev_get_drvdata(port->dev); 600 unsigned long flags; 601 602 spin_lock_irqsave(&s->lock, flags); 603 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 604 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 605 spin_unlock_irqrestore(&s->lock, flags); 606 } 607 608 static void sccnxp_set_termios(struct uart_port *port, 609 struct ktermios *termios, struct ktermios *old) 610 { 611 struct sccnxp_port *s = dev_get_drvdata(port->dev); 612 unsigned long flags; 613 u8 mr1, mr2; 614 int baud; 615 616 spin_lock_irqsave(&s->lock, flags); 617 618 /* Mask termios capabilities we don't support */ 619 termios->c_cflag &= ~CMSPAR; 620 621 /* Disable RX & TX, reset break condition, status and FIFOs */ 622 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 623 CR_RX_DISABLE | CR_TX_DISABLE); 624 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 626 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 627 628 /* Word size */ 629 switch (termios->c_cflag & CSIZE) { 630 case CS5: 631 mr1 = MR1_BITS_5; 632 break; 633 case CS6: 634 mr1 = MR1_BITS_6; 635 break; 636 case CS7: 637 mr1 = MR1_BITS_7; 638 break; 639 case CS8: 640 default: 641 mr1 = MR1_BITS_8; 642 break; 643 } 644 645 /* Parity */ 646 if (termios->c_cflag & PARENB) { 647 if (termios->c_cflag & PARODD) 648 mr1 |= MR1_PAR_ODD; 649 } else 650 mr1 |= MR1_PAR_NO; 651 652 /* Stop bits */ 653 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 654 655 /* Update desired format */ 656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 657 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 658 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 659 660 /* Set read status mask */ 661 port->read_status_mask = SR_OVR; 662 if (termios->c_iflag & INPCK) 663 port->read_status_mask |= SR_PE | SR_FE; 664 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 665 port->read_status_mask |= SR_BRK; 666 667 /* Set status ignore mask */ 668 port->ignore_status_mask = 0; 669 if (termios->c_iflag & IGNBRK) 670 port->ignore_status_mask |= SR_BRK; 671 if (termios->c_iflag & IGNPAR) 672 port->ignore_status_mask |= SR_PE; 673 if (!(termios->c_cflag & CREAD)) 674 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 675 676 /* Setup baudrate */ 677 baud = uart_get_baud_rate(port, termios, old, 50, 678 (s->chip->flags & SCCNXP_HAVE_MR0) ? 679 230400 : 38400); 680 baud = sccnxp_set_baud(port, baud); 681 682 /* Update timeout according to new baud rate */ 683 uart_update_timeout(port, termios->c_cflag, baud); 684 685 /* Report actual baudrate back to core */ 686 if (tty_termios_baud_rate(termios)) 687 tty_termios_encode_baud_rate(termios, baud, baud); 688 689 /* Enable RX & TX */ 690 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 691 692 spin_unlock_irqrestore(&s->lock, flags); 693 } 694 695 static int sccnxp_startup(struct uart_port *port) 696 { 697 struct sccnxp_port *s = dev_get_drvdata(port->dev); 698 unsigned long flags; 699 700 spin_lock_irqsave(&s->lock, flags); 701 702 if (s->chip->flags & SCCNXP_HAVE_IO) { 703 /* Outputs are controlled manually */ 704 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 705 } 706 707 /* Reset break condition, status and FIFOs */ 708 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 709 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 710 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 711 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 712 713 /* Enable RX & TX */ 714 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 715 716 /* Enable RX interrupt */ 717 sccnxp_enable_irq(port, IMR_RXRDY); 718 719 s->opened[port->line] = 1; 720 721 spin_unlock_irqrestore(&s->lock, flags); 722 723 return 0; 724 } 725 726 static void sccnxp_shutdown(struct uart_port *port) 727 { 728 struct sccnxp_port *s = dev_get_drvdata(port->dev); 729 unsigned long flags; 730 731 spin_lock_irqsave(&s->lock, flags); 732 733 s->opened[port->line] = 0; 734 735 /* Disable interrupts */ 736 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 737 738 /* Disable TX & RX */ 739 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 740 741 /* Leave direction to input */ 742 if (s->chip->flags & SCCNXP_HAVE_IO) 743 sccnxp_set_bit(port, DIR_OP, 0); 744 745 spin_unlock_irqrestore(&s->lock, flags); 746 } 747 748 static const char *sccnxp_type(struct uart_port *port) 749 { 750 struct sccnxp_port *s = dev_get_drvdata(port->dev); 751 752 return (port->type == PORT_SC26XX) ? s->chip->name : NULL; 753 } 754 755 static void sccnxp_release_port(struct uart_port *port) 756 { 757 /* Do nothing */ 758 } 759 760 static int sccnxp_request_port(struct uart_port *port) 761 { 762 /* Do nothing */ 763 return 0; 764 } 765 766 static void sccnxp_config_port(struct uart_port *port, int flags) 767 { 768 if (flags & UART_CONFIG_TYPE) 769 port->type = PORT_SC26XX; 770 } 771 772 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 773 { 774 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 775 return 0; 776 if (s->irq == port->irq) 777 return 0; 778 779 return -EINVAL; 780 } 781 782 static const struct uart_ops sccnxp_ops = { 783 .tx_empty = sccnxp_tx_empty, 784 .set_mctrl = sccnxp_set_mctrl, 785 .get_mctrl = sccnxp_get_mctrl, 786 .stop_tx = sccnxp_stop_tx, 787 .start_tx = sccnxp_start_tx, 788 .stop_rx = sccnxp_stop_rx, 789 .break_ctl = sccnxp_break_ctl, 790 .startup = sccnxp_startup, 791 .shutdown = sccnxp_shutdown, 792 .set_termios = sccnxp_set_termios, 793 .type = sccnxp_type, 794 .release_port = sccnxp_release_port, 795 .request_port = sccnxp_request_port, 796 .config_port = sccnxp_config_port, 797 .verify_port = sccnxp_verify_port, 798 }; 799 800 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 801 static void sccnxp_console_putchar(struct uart_port *port, int c) 802 { 803 int tryes = 100000; 804 805 while (tryes--) { 806 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 807 sccnxp_port_write(port, SCCNXP_THR_REG, c); 808 break; 809 } 810 barrier(); 811 } 812 } 813 814 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 815 { 816 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 817 struct uart_port *port = &s->port[co->index]; 818 unsigned long flags; 819 820 spin_lock_irqsave(&s->lock, flags); 821 uart_console_write(port, c, n, sccnxp_console_putchar); 822 spin_unlock_irqrestore(&s->lock, flags); 823 } 824 825 static int sccnxp_console_setup(struct console *co, char *options) 826 { 827 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 828 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 829 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 830 831 if (options) 832 uart_parse_options(options, &baud, &parity, &bits, &flow); 833 834 return uart_set_options(port, co, baud, parity, bits, flow); 835 } 836 #endif 837 838 static const struct platform_device_id sccnxp_id_table[] = { 839 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, }, 840 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, }, 841 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, }, 842 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, }, 843 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, }, 844 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, }, 845 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, }, 846 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, }, 847 { } 848 }; 849 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 850 851 static int sccnxp_probe(struct platform_device *pdev) 852 { 853 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 854 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 855 int i, ret, uartclk; 856 struct sccnxp_port *s; 857 void __iomem *membase; 858 struct clk *clk; 859 860 membase = devm_ioremap_resource(&pdev->dev, res); 861 if (IS_ERR(membase)) 862 return PTR_ERR(membase); 863 864 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 865 if (!s) { 866 dev_err(&pdev->dev, "Error allocating port structure\n"); 867 return -ENOMEM; 868 } 869 platform_set_drvdata(pdev, s); 870 871 spin_lock_init(&s->lock); 872 873 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data; 874 875 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 876 if (!IS_ERR(s->regulator)) { 877 ret = regulator_enable(s->regulator); 878 if (ret) { 879 dev_err(&pdev->dev, 880 "Failed to enable regulator: %i\n", ret); 881 return ret; 882 } 883 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) 884 return -EPROBE_DEFER; 885 886 clk = devm_clk_get(&pdev->dev, NULL); 887 if (IS_ERR(clk)) { 888 ret = PTR_ERR(clk); 889 if (ret == -EPROBE_DEFER) 890 goto err_out; 891 uartclk = 0; 892 } else { 893 clk_prepare_enable(clk); 894 uartclk = clk_get_rate(clk); 895 } 896 897 if (!uartclk) { 898 dev_notice(&pdev->dev, "Using default clock frequency\n"); 899 uartclk = s->chip->freq_std; 900 } 901 902 /* Check input frequency */ 903 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { 904 dev_err(&pdev->dev, "Frequency out of bounds\n"); 905 ret = -EINVAL; 906 goto err_out; 907 } 908 909 if (pdata) 910 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 911 912 if (s->pdata.poll_time_us) { 913 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 914 s->pdata.poll_time_us); 915 s->poll = 1; 916 } 917 918 if (!s->poll) { 919 s->irq = platform_get_irq(pdev, 0); 920 if (s->irq < 0) { 921 dev_err(&pdev->dev, "Missing irq resource data\n"); 922 ret = -ENXIO; 923 goto err_out; 924 } 925 } 926 927 s->uart.owner = THIS_MODULE; 928 s->uart.dev_name = "ttySC"; 929 s->uart.major = SCCNXP_MAJOR; 930 s->uart.minor = SCCNXP_MINOR; 931 s->uart.nr = s->chip->nr; 932 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 933 s->uart.cons = &s->console; 934 s->uart.cons->device = uart_console_device; 935 s->uart.cons->write = sccnxp_console_write; 936 s->uart.cons->setup = sccnxp_console_setup; 937 s->uart.cons->flags = CON_PRINTBUFFER; 938 s->uart.cons->index = -1; 939 s->uart.cons->data = s; 940 strcpy(s->uart.cons->name, "ttySC"); 941 #endif 942 ret = uart_register_driver(&s->uart); 943 if (ret) { 944 dev_err(&pdev->dev, "Registering UART driver failed\n"); 945 goto err_out; 946 } 947 948 for (i = 0; i < s->uart.nr; i++) { 949 s->port[i].line = i; 950 s->port[i].dev = &pdev->dev; 951 s->port[i].irq = s->irq; 952 s->port[i].type = PORT_SC26XX; 953 s->port[i].fifosize = s->chip->fifosize; 954 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 955 s->port[i].iotype = UPIO_MEM; 956 s->port[i].mapbase = res->start; 957 s->port[i].membase = membase; 958 s->port[i].regshift = s->pdata.reg_shift; 959 s->port[i].uartclk = uartclk; 960 s->port[i].ops = &sccnxp_ops; 961 uart_add_one_port(&s->uart, &s->port[i]); 962 /* Set direction to input */ 963 if (s->chip->flags & SCCNXP_HAVE_IO) 964 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 965 } 966 967 /* Disable interrupts */ 968 s->imr = 0; 969 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 970 971 if (!s->poll) { 972 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 973 sccnxp_ist, 974 IRQF_TRIGGER_FALLING | 975 IRQF_ONESHOT, 976 dev_name(&pdev->dev), s); 977 if (!ret) 978 return 0; 979 980 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 981 } else { 982 init_timer(&s->timer); 983 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 984 mod_timer(&s->timer, jiffies + 985 usecs_to_jiffies(s->pdata.poll_time_us)); 986 return 0; 987 } 988 989 uart_unregister_driver(&s->uart); 990 err_out: 991 if (!IS_ERR(s->regulator)) 992 return regulator_disable(s->regulator); 993 994 return ret; 995 } 996 997 static int sccnxp_remove(struct platform_device *pdev) 998 { 999 int i; 1000 struct sccnxp_port *s = platform_get_drvdata(pdev); 1001 1002 if (!s->poll) 1003 devm_free_irq(&pdev->dev, s->irq, s); 1004 else 1005 del_timer_sync(&s->timer); 1006 1007 for (i = 0; i < s->uart.nr; i++) 1008 uart_remove_one_port(&s->uart, &s->port[i]); 1009 1010 uart_unregister_driver(&s->uart); 1011 1012 if (!IS_ERR(s->regulator)) 1013 return regulator_disable(s->regulator); 1014 1015 return 0; 1016 } 1017 1018 static struct platform_driver sccnxp_uart_driver = { 1019 .driver = { 1020 .name = SCCNXP_NAME, 1021 }, 1022 .probe = sccnxp_probe, 1023 .remove = sccnxp_remove, 1024 .id_table = sccnxp_id_table, 1025 }; 1026 module_platform_driver(sccnxp_uart_driver); 1027 1028 MODULE_LICENSE("GPL v2"); 1029 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1030 MODULE_DESCRIPTION("SCCNXP serial driver"); 1031 1032 1033 1034 1035 1036 /* LDV_COMMENT_BEGIN_MAIN */ 1037 #ifdef LDV_MAIN0_sequence_infinite_withcheck_stateful 1038 1039 /*###########################################################################*/ 1040 1041 /*############## Driver Environment Generator 0.2 output ####################*/ 1042 1043 /*###########################################################################*/ 1044 1045 1046 1047 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test if all kernel resources are correctly released by driver before driver will be unloaded. */ 1048 void ldv_check_final_state(void); 1049 1050 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result. */ 1051 void ldv_check_return_value(int res); 1052 1053 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result of probe() function. */ 1054 void ldv_check_return_value_probe(int res); 1055 1056 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Initializes the model. */ 1057 void ldv_initialize(void); 1058 1059 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Reinitializes the model between distinct model function calls. */ 1060 void ldv_handler_precall(void); 1061 1062 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Returns arbitrary interger value. */ 1063 int nondet_int(void); 1064 1065 /* LDV_COMMENT_VAR_DECLARE_LDV Special variable for LDV verifier. */ 1066 int LDV_IN_INTERRUPT; 1067 1068 /* LDV_COMMENT_FUNCTION_MAIN Main function for LDV verifier. */ 1069 void ldv_main0_sequence_infinite_withcheck_stateful(void) { 1070 1071 1072 1073 /* LDV_COMMENT_BEGIN_VARIABLE_DECLARATION_PART */ 1074 /*============================= VARIABLE DECLARATION PART =============================*/ 1075 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 1076 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/ 1077 /* LDV_COMMENT_BEGIN_PREP */ 1078 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1079 #define SUPPORT_SYSRQ 1080 #endif 1081 #define SCCNXP_NAME "uart-sccnxp" 1082 #define SCCNXP_MAJOR 204 1083 #define SCCNXP_MINOR 205 1084 #define SCCNXP_MR_REG (0x00) 1085 # define MR0_BAUD_NORMAL (0 << 0) 1086 # define MR0_BAUD_EXT1 (1 << 0) 1087 # define MR0_BAUD_EXT2 (5 << 0) 1088 # define MR0_FIFO (1 << 3) 1089 # define MR0_TXLVL (1 << 4) 1090 # define MR1_BITS_5 (0 << 0) 1091 # define MR1_BITS_6 (1 << 0) 1092 # define MR1_BITS_7 (2 << 0) 1093 # define MR1_BITS_8 (3 << 0) 1094 # define MR1_PAR_EVN (0 << 2) 1095 # define MR1_PAR_ODD (1 << 2) 1096 # define MR1_PAR_NO (4 << 2) 1097 # define MR2_STOP1 (7 << 0) 1098 # define MR2_STOP2 (0xf << 0) 1099 #define SCCNXP_SR_REG (0x01) 1100 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1101 # define SR_RXRDY (1 << 0) 1102 # define SR_FULL (1 << 1) 1103 # define SR_TXRDY (1 << 2) 1104 # define SR_TXEMT (1 << 3) 1105 # define SR_OVR (1 << 4) 1106 # define SR_PE (1 << 5) 1107 # define SR_FE (1 << 6) 1108 # define SR_BRK (1 << 7) 1109 #define SCCNXP_CR_REG (0x02) 1110 # define CR_RX_ENABLE (1 << 0) 1111 # define CR_RX_DISABLE (1 << 1) 1112 # define CR_TX_ENABLE (1 << 2) 1113 # define CR_TX_DISABLE (1 << 3) 1114 # define CR_CMD_MRPTR1 (0x01 << 4) 1115 # define CR_CMD_RX_RESET (0x02 << 4) 1116 # define CR_CMD_TX_RESET (0x03 << 4) 1117 # define CR_CMD_STATUS_RESET (0x04 << 4) 1118 # define CR_CMD_BREAK_RESET (0x05 << 4) 1119 # define CR_CMD_START_BREAK (0x06 << 4) 1120 # define CR_CMD_STOP_BREAK (0x07 << 4) 1121 # define CR_CMD_MRPTR0 (0x0b << 4) 1122 #define SCCNXP_RHR_REG (0x03) 1123 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1124 #define SCCNXP_IPCR_REG (0x04) 1125 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1126 # define ACR_BAUD0 (0 << 7) 1127 # define ACR_BAUD1 (1 << 7) 1128 # define ACR_TIMER_MODE (6 << 4) 1129 #define SCCNXP_ISR_REG (0x05) 1130 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1131 # define IMR_TXRDY (1 << 0) 1132 # define IMR_RXRDY (1 << 1) 1133 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1134 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1135 #define SCCNXP_IPR_REG (0x0d) 1136 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1137 #define SCCNXP_SOP_REG (0x0e) 1138 #define SCCNXP_ROP_REG (0x0f) 1139 #define MCTRL_MASK(sig) (0xf << (sig)) 1140 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1141 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1142 #define SCCNXP_HAVE_IO 0x00000001 1143 #define SCCNXP_HAVE_MR0 0x00000002 1144 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1145 #endif 1146 /* LDV_COMMENT_END_PREP */ 1147 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_tx_empty" */ 1148 struct uart_port * var_group1; 1149 /* LDV_COMMENT_BEGIN_PREP */ 1150 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1151 #endif 1152 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1153 #endif 1154 /* LDV_COMMENT_END_PREP */ 1155 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/ 1156 /* LDV_COMMENT_BEGIN_PREP */ 1157 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1158 #define SUPPORT_SYSRQ 1159 #endif 1160 #define SCCNXP_NAME "uart-sccnxp" 1161 #define SCCNXP_MAJOR 204 1162 #define SCCNXP_MINOR 205 1163 #define SCCNXP_MR_REG (0x00) 1164 # define MR0_BAUD_NORMAL (0 << 0) 1165 # define MR0_BAUD_EXT1 (1 << 0) 1166 # define MR0_BAUD_EXT2 (5 << 0) 1167 # define MR0_FIFO (1 << 3) 1168 # define MR0_TXLVL (1 << 4) 1169 # define MR1_BITS_5 (0 << 0) 1170 # define MR1_BITS_6 (1 << 0) 1171 # define MR1_BITS_7 (2 << 0) 1172 # define MR1_BITS_8 (3 << 0) 1173 # define MR1_PAR_EVN (0 << 2) 1174 # define MR1_PAR_ODD (1 << 2) 1175 # define MR1_PAR_NO (4 << 2) 1176 # define MR2_STOP1 (7 << 0) 1177 # define MR2_STOP2 (0xf << 0) 1178 #define SCCNXP_SR_REG (0x01) 1179 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1180 # define SR_RXRDY (1 << 0) 1181 # define SR_FULL (1 << 1) 1182 # define SR_TXRDY (1 << 2) 1183 # define SR_TXEMT (1 << 3) 1184 # define SR_OVR (1 << 4) 1185 # define SR_PE (1 << 5) 1186 # define SR_FE (1 << 6) 1187 # define SR_BRK (1 << 7) 1188 #define SCCNXP_CR_REG (0x02) 1189 # define CR_RX_ENABLE (1 << 0) 1190 # define CR_RX_DISABLE (1 << 1) 1191 # define CR_TX_ENABLE (1 << 2) 1192 # define CR_TX_DISABLE (1 << 3) 1193 # define CR_CMD_MRPTR1 (0x01 << 4) 1194 # define CR_CMD_RX_RESET (0x02 << 4) 1195 # define CR_CMD_TX_RESET (0x03 << 4) 1196 # define CR_CMD_STATUS_RESET (0x04 << 4) 1197 # define CR_CMD_BREAK_RESET (0x05 << 4) 1198 # define CR_CMD_START_BREAK (0x06 << 4) 1199 # define CR_CMD_STOP_BREAK (0x07 << 4) 1200 # define CR_CMD_MRPTR0 (0x0b << 4) 1201 #define SCCNXP_RHR_REG (0x03) 1202 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1203 #define SCCNXP_IPCR_REG (0x04) 1204 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1205 # define ACR_BAUD0 (0 << 7) 1206 # define ACR_BAUD1 (1 << 7) 1207 # define ACR_TIMER_MODE (6 << 4) 1208 #define SCCNXP_ISR_REG (0x05) 1209 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1210 # define IMR_TXRDY (1 << 0) 1211 # define IMR_RXRDY (1 << 1) 1212 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1213 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1214 #define SCCNXP_IPR_REG (0x0d) 1215 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1216 #define SCCNXP_SOP_REG (0x0e) 1217 #define SCCNXP_ROP_REG (0x0f) 1218 #define MCTRL_MASK(sig) (0xf << (sig)) 1219 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1220 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1221 #define SCCNXP_HAVE_IO 0x00000001 1222 #define SCCNXP_HAVE_MR0 0x00000002 1223 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1224 #endif 1225 /* LDV_COMMENT_END_PREP */ 1226 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_mctrl" */ 1227 unsigned int var_sccnxp_set_mctrl_18_p1; 1228 /* LDV_COMMENT_BEGIN_PREP */ 1229 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1230 #endif 1231 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1232 #endif 1233 /* LDV_COMMENT_END_PREP */ 1234 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/ 1235 /* LDV_COMMENT_BEGIN_PREP */ 1236 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1237 #define SUPPORT_SYSRQ 1238 #endif 1239 #define SCCNXP_NAME "uart-sccnxp" 1240 #define SCCNXP_MAJOR 204 1241 #define SCCNXP_MINOR 205 1242 #define SCCNXP_MR_REG (0x00) 1243 # define MR0_BAUD_NORMAL (0 << 0) 1244 # define MR0_BAUD_EXT1 (1 << 0) 1245 # define MR0_BAUD_EXT2 (5 << 0) 1246 # define MR0_FIFO (1 << 3) 1247 # define MR0_TXLVL (1 << 4) 1248 # define MR1_BITS_5 (0 << 0) 1249 # define MR1_BITS_6 (1 << 0) 1250 # define MR1_BITS_7 (2 << 0) 1251 # define MR1_BITS_8 (3 << 0) 1252 # define MR1_PAR_EVN (0 << 2) 1253 # define MR1_PAR_ODD (1 << 2) 1254 # define MR1_PAR_NO (4 << 2) 1255 # define MR2_STOP1 (7 << 0) 1256 # define MR2_STOP2 (0xf << 0) 1257 #define SCCNXP_SR_REG (0x01) 1258 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1259 # define SR_RXRDY (1 << 0) 1260 # define SR_FULL (1 << 1) 1261 # define SR_TXRDY (1 << 2) 1262 # define SR_TXEMT (1 << 3) 1263 # define SR_OVR (1 << 4) 1264 # define SR_PE (1 << 5) 1265 # define SR_FE (1 << 6) 1266 # define SR_BRK (1 << 7) 1267 #define SCCNXP_CR_REG (0x02) 1268 # define CR_RX_ENABLE (1 << 0) 1269 # define CR_RX_DISABLE (1 << 1) 1270 # define CR_TX_ENABLE (1 << 2) 1271 # define CR_TX_DISABLE (1 << 3) 1272 # define CR_CMD_MRPTR1 (0x01 << 4) 1273 # define CR_CMD_RX_RESET (0x02 << 4) 1274 # define CR_CMD_TX_RESET (0x03 << 4) 1275 # define CR_CMD_STATUS_RESET (0x04 << 4) 1276 # define CR_CMD_BREAK_RESET (0x05 << 4) 1277 # define CR_CMD_START_BREAK (0x06 << 4) 1278 # define CR_CMD_STOP_BREAK (0x07 << 4) 1279 # define CR_CMD_MRPTR0 (0x0b << 4) 1280 #define SCCNXP_RHR_REG (0x03) 1281 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1282 #define SCCNXP_IPCR_REG (0x04) 1283 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1284 # define ACR_BAUD0 (0 << 7) 1285 # define ACR_BAUD1 (1 << 7) 1286 # define ACR_TIMER_MODE (6 << 4) 1287 #define SCCNXP_ISR_REG (0x05) 1288 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1289 # define IMR_TXRDY (1 << 0) 1290 # define IMR_RXRDY (1 << 1) 1291 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1292 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1293 #define SCCNXP_IPR_REG (0x0d) 1294 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1295 #define SCCNXP_SOP_REG (0x0e) 1296 #define SCCNXP_ROP_REG (0x0f) 1297 #define MCTRL_MASK(sig) (0xf << (sig)) 1298 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1299 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1300 #define SCCNXP_HAVE_IO 0x00000001 1301 #define SCCNXP_HAVE_MR0 0x00000002 1302 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1303 #endif 1304 /* LDV_COMMENT_END_PREP */ 1305 /* LDV_COMMENT_BEGIN_PREP */ 1306 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1307 #endif 1308 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1309 #endif 1310 /* LDV_COMMENT_END_PREP */ 1311 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/ 1312 /* LDV_COMMENT_BEGIN_PREP */ 1313 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1314 #define SUPPORT_SYSRQ 1315 #endif 1316 #define SCCNXP_NAME "uart-sccnxp" 1317 #define SCCNXP_MAJOR 204 1318 #define SCCNXP_MINOR 205 1319 #define SCCNXP_MR_REG (0x00) 1320 # define MR0_BAUD_NORMAL (0 << 0) 1321 # define MR0_BAUD_EXT1 (1 << 0) 1322 # define MR0_BAUD_EXT2 (5 << 0) 1323 # define MR0_FIFO (1 << 3) 1324 # define MR0_TXLVL (1 << 4) 1325 # define MR1_BITS_5 (0 << 0) 1326 # define MR1_BITS_6 (1 << 0) 1327 # define MR1_BITS_7 (2 << 0) 1328 # define MR1_BITS_8 (3 << 0) 1329 # define MR1_PAR_EVN (0 << 2) 1330 # define MR1_PAR_ODD (1 << 2) 1331 # define MR1_PAR_NO (4 << 2) 1332 # define MR2_STOP1 (7 << 0) 1333 # define MR2_STOP2 (0xf << 0) 1334 #define SCCNXP_SR_REG (0x01) 1335 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1336 # define SR_RXRDY (1 << 0) 1337 # define SR_FULL (1 << 1) 1338 # define SR_TXRDY (1 << 2) 1339 # define SR_TXEMT (1 << 3) 1340 # define SR_OVR (1 << 4) 1341 # define SR_PE (1 << 5) 1342 # define SR_FE (1 << 6) 1343 # define SR_BRK (1 << 7) 1344 #define SCCNXP_CR_REG (0x02) 1345 # define CR_RX_ENABLE (1 << 0) 1346 # define CR_RX_DISABLE (1 << 1) 1347 # define CR_TX_ENABLE (1 << 2) 1348 # define CR_TX_DISABLE (1 << 3) 1349 # define CR_CMD_MRPTR1 (0x01 << 4) 1350 # define CR_CMD_RX_RESET (0x02 << 4) 1351 # define CR_CMD_TX_RESET (0x03 << 4) 1352 # define CR_CMD_STATUS_RESET (0x04 << 4) 1353 # define CR_CMD_BREAK_RESET (0x05 << 4) 1354 # define CR_CMD_START_BREAK (0x06 << 4) 1355 # define CR_CMD_STOP_BREAK (0x07 << 4) 1356 # define CR_CMD_MRPTR0 (0x0b << 4) 1357 #define SCCNXP_RHR_REG (0x03) 1358 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1359 #define SCCNXP_IPCR_REG (0x04) 1360 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1361 # define ACR_BAUD0 (0 << 7) 1362 # define ACR_BAUD1 (1 << 7) 1363 # define ACR_TIMER_MODE (6 << 4) 1364 #define SCCNXP_ISR_REG (0x05) 1365 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1366 # define IMR_TXRDY (1 << 0) 1367 # define IMR_RXRDY (1 << 1) 1368 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1369 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1370 #define SCCNXP_IPR_REG (0x0d) 1371 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1372 #define SCCNXP_SOP_REG (0x0e) 1373 #define SCCNXP_ROP_REG (0x0f) 1374 #define MCTRL_MASK(sig) (0xf << (sig)) 1375 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1376 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1377 #define SCCNXP_HAVE_IO 0x00000001 1378 #define SCCNXP_HAVE_MR0 0x00000002 1379 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1380 #endif 1381 /* LDV_COMMENT_END_PREP */ 1382 /* LDV_COMMENT_BEGIN_PREP */ 1383 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1384 #endif 1385 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1386 #endif 1387 /* LDV_COMMENT_END_PREP */ 1388 /* content: static void sccnxp_start_tx(struct uart_port *port)*/ 1389 /* LDV_COMMENT_BEGIN_PREP */ 1390 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1391 #define SUPPORT_SYSRQ 1392 #endif 1393 #define SCCNXP_NAME "uart-sccnxp" 1394 #define SCCNXP_MAJOR 204 1395 #define SCCNXP_MINOR 205 1396 #define SCCNXP_MR_REG (0x00) 1397 # define MR0_BAUD_NORMAL (0 << 0) 1398 # define MR0_BAUD_EXT1 (1 << 0) 1399 # define MR0_BAUD_EXT2 (5 << 0) 1400 # define MR0_FIFO (1 << 3) 1401 # define MR0_TXLVL (1 << 4) 1402 # define MR1_BITS_5 (0 << 0) 1403 # define MR1_BITS_6 (1 << 0) 1404 # define MR1_BITS_7 (2 << 0) 1405 # define MR1_BITS_8 (3 << 0) 1406 # define MR1_PAR_EVN (0 << 2) 1407 # define MR1_PAR_ODD (1 << 2) 1408 # define MR1_PAR_NO (4 << 2) 1409 # define MR2_STOP1 (7 << 0) 1410 # define MR2_STOP2 (0xf << 0) 1411 #define SCCNXP_SR_REG (0x01) 1412 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1413 # define SR_RXRDY (1 << 0) 1414 # define SR_FULL (1 << 1) 1415 # define SR_TXRDY (1 << 2) 1416 # define SR_TXEMT (1 << 3) 1417 # define SR_OVR (1 << 4) 1418 # define SR_PE (1 << 5) 1419 # define SR_FE (1 << 6) 1420 # define SR_BRK (1 << 7) 1421 #define SCCNXP_CR_REG (0x02) 1422 # define CR_RX_ENABLE (1 << 0) 1423 # define CR_RX_DISABLE (1 << 1) 1424 # define CR_TX_ENABLE (1 << 2) 1425 # define CR_TX_DISABLE (1 << 3) 1426 # define CR_CMD_MRPTR1 (0x01 << 4) 1427 # define CR_CMD_RX_RESET (0x02 << 4) 1428 # define CR_CMD_TX_RESET (0x03 << 4) 1429 # define CR_CMD_STATUS_RESET (0x04 << 4) 1430 # define CR_CMD_BREAK_RESET (0x05 << 4) 1431 # define CR_CMD_START_BREAK (0x06 << 4) 1432 # define CR_CMD_STOP_BREAK (0x07 << 4) 1433 # define CR_CMD_MRPTR0 (0x0b << 4) 1434 #define SCCNXP_RHR_REG (0x03) 1435 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1436 #define SCCNXP_IPCR_REG (0x04) 1437 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1438 # define ACR_BAUD0 (0 << 7) 1439 # define ACR_BAUD1 (1 << 7) 1440 # define ACR_TIMER_MODE (6 << 4) 1441 #define SCCNXP_ISR_REG (0x05) 1442 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1443 # define IMR_TXRDY (1 << 0) 1444 # define IMR_RXRDY (1 << 1) 1445 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1446 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1447 #define SCCNXP_IPR_REG (0x0d) 1448 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1449 #define SCCNXP_SOP_REG (0x0e) 1450 #define SCCNXP_ROP_REG (0x0f) 1451 #define MCTRL_MASK(sig) (0xf << (sig)) 1452 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1453 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1454 #define SCCNXP_HAVE_IO 0x00000001 1455 #define SCCNXP_HAVE_MR0 0x00000002 1456 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1457 #endif 1458 /* LDV_COMMENT_END_PREP */ 1459 /* LDV_COMMENT_BEGIN_PREP */ 1460 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1461 #endif 1462 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1463 #endif 1464 /* LDV_COMMENT_END_PREP */ 1465 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/ 1466 /* LDV_COMMENT_BEGIN_PREP */ 1467 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1468 #define SUPPORT_SYSRQ 1469 #endif 1470 #define SCCNXP_NAME "uart-sccnxp" 1471 #define SCCNXP_MAJOR 204 1472 #define SCCNXP_MINOR 205 1473 #define SCCNXP_MR_REG (0x00) 1474 # define MR0_BAUD_NORMAL (0 << 0) 1475 # define MR0_BAUD_EXT1 (1 << 0) 1476 # define MR0_BAUD_EXT2 (5 << 0) 1477 # define MR0_FIFO (1 << 3) 1478 # define MR0_TXLVL (1 << 4) 1479 # define MR1_BITS_5 (0 << 0) 1480 # define MR1_BITS_6 (1 << 0) 1481 # define MR1_BITS_7 (2 << 0) 1482 # define MR1_BITS_8 (3 << 0) 1483 # define MR1_PAR_EVN (0 << 2) 1484 # define MR1_PAR_ODD (1 << 2) 1485 # define MR1_PAR_NO (4 << 2) 1486 # define MR2_STOP1 (7 << 0) 1487 # define MR2_STOP2 (0xf << 0) 1488 #define SCCNXP_SR_REG (0x01) 1489 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1490 # define SR_RXRDY (1 << 0) 1491 # define SR_FULL (1 << 1) 1492 # define SR_TXRDY (1 << 2) 1493 # define SR_TXEMT (1 << 3) 1494 # define SR_OVR (1 << 4) 1495 # define SR_PE (1 << 5) 1496 # define SR_FE (1 << 6) 1497 # define SR_BRK (1 << 7) 1498 #define SCCNXP_CR_REG (0x02) 1499 # define CR_RX_ENABLE (1 << 0) 1500 # define CR_RX_DISABLE (1 << 1) 1501 # define CR_TX_ENABLE (1 << 2) 1502 # define CR_TX_DISABLE (1 << 3) 1503 # define CR_CMD_MRPTR1 (0x01 << 4) 1504 # define CR_CMD_RX_RESET (0x02 << 4) 1505 # define CR_CMD_TX_RESET (0x03 << 4) 1506 # define CR_CMD_STATUS_RESET (0x04 << 4) 1507 # define CR_CMD_BREAK_RESET (0x05 << 4) 1508 # define CR_CMD_START_BREAK (0x06 << 4) 1509 # define CR_CMD_STOP_BREAK (0x07 << 4) 1510 # define CR_CMD_MRPTR0 (0x0b << 4) 1511 #define SCCNXP_RHR_REG (0x03) 1512 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1513 #define SCCNXP_IPCR_REG (0x04) 1514 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1515 # define ACR_BAUD0 (0 << 7) 1516 # define ACR_BAUD1 (1 << 7) 1517 # define ACR_TIMER_MODE (6 << 4) 1518 #define SCCNXP_ISR_REG (0x05) 1519 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1520 # define IMR_TXRDY (1 << 0) 1521 # define IMR_RXRDY (1 << 1) 1522 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1523 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1524 #define SCCNXP_IPR_REG (0x0d) 1525 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1526 #define SCCNXP_SOP_REG (0x0e) 1527 #define SCCNXP_ROP_REG (0x0f) 1528 #define MCTRL_MASK(sig) (0xf << (sig)) 1529 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1530 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1531 #define SCCNXP_HAVE_IO 0x00000001 1532 #define SCCNXP_HAVE_MR0 0x00000002 1533 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1534 #endif 1535 /* LDV_COMMENT_END_PREP */ 1536 /* LDV_COMMENT_BEGIN_PREP */ 1537 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1538 #endif 1539 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1540 #endif 1541 /* LDV_COMMENT_END_PREP */ 1542 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/ 1543 /* LDV_COMMENT_BEGIN_PREP */ 1544 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1545 #define SUPPORT_SYSRQ 1546 #endif 1547 #define SCCNXP_NAME "uart-sccnxp" 1548 #define SCCNXP_MAJOR 204 1549 #define SCCNXP_MINOR 205 1550 #define SCCNXP_MR_REG (0x00) 1551 # define MR0_BAUD_NORMAL (0 << 0) 1552 # define MR0_BAUD_EXT1 (1 << 0) 1553 # define MR0_BAUD_EXT2 (5 << 0) 1554 # define MR0_FIFO (1 << 3) 1555 # define MR0_TXLVL (1 << 4) 1556 # define MR1_BITS_5 (0 << 0) 1557 # define MR1_BITS_6 (1 << 0) 1558 # define MR1_BITS_7 (2 << 0) 1559 # define MR1_BITS_8 (3 << 0) 1560 # define MR1_PAR_EVN (0 << 2) 1561 # define MR1_PAR_ODD (1 << 2) 1562 # define MR1_PAR_NO (4 << 2) 1563 # define MR2_STOP1 (7 << 0) 1564 # define MR2_STOP2 (0xf << 0) 1565 #define SCCNXP_SR_REG (0x01) 1566 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1567 # define SR_RXRDY (1 << 0) 1568 # define SR_FULL (1 << 1) 1569 # define SR_TXRDY (1 << 2) 1570 # define SR_TXEMT (1 << 3) 1571 # define SR_OVR (1 << 4) 1572 # define SR_PE (1 << 5) 1573 # define SR_FE (1 << 6) 1574 # define SR_BRK (1 << 7) 1575 #define SCCNXP_CR_REG (0x02) 1576 # define CR_RX_ENABLE (1 << 0) 1577 # define CR_RX_DISABLE (1 << 1) 1578 # define CR_TX_ENABLE (1 << 2) 1579 # define CR_TX_DISABLE (1 << 3) 1580 # define CR_CMD_MRPTR1 (0x01 << 4) 1581 # define CR_CMD_RX_RESET (0x02 << 4) 1582 # define CR_CMD_TX_RESET (0x03 << 4) 1583 # define CR_CMD_STATUS_RESET (0x04 << 4) 1584 # define CR_CMD_BREAK_RESET (0x05 << 4) 1585 # define CR_CMD_START_BREAK (0x06 << 4) 1586 # define CR_CMD_STOP_BREAK (0x07 << 4) 1587 # define CR_CMD_MRPTR0 (0x0b << 4) 1588 #define SCCNXP_RHR_REG (0x03) 1589 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1590 #define SCCNXP_IPCR_REG (0x04) 1591 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1592 # define ACR_BAUD0 (0 << 7) 1593 # define ACR_BAUD1 (1 << 7) 1594 # define ACR_TIMER_MODE (6 << 4) 1595 #define SCCNXP_ISR_REG (0x05) 1596 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1597 # define IMR_TXRDY (1 << 0) 1598 # define IMR_RXRDY (1 << 1) 1599 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1600 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1601 #define SCCNXP_IPR_REG (0x0d) 1602 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1603 #define SCCNXP_SOP_REG (0x0e) 1604 #define SCCNXP_ROP_REG (0x0f) 1605 #define MCTRL_MASK(sig) (0xf << (sig)) 1606 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1607 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1608 #define SCCNXP_HAVE_IO 0x00000001 1609 #define SCCNXP_HAVE_MR0 0x00000002 1610 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1611 #endif 1612 /* LDV_COMMENT_END_PREP */ 1613 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_break_ctl" */ 1614 int var_sccnxp_break_ctl_20_p1; 1615 /* LDV_COMMENT_BEGIN_PREP */ 1616 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1617 #endif 1618 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1619 #endif 1620 /* LDV_COMMENT_END_PREP */ 1621 /* content: static int sccnxp_startup(struct uart_port *port)*/ 1622 /* LDV_COMMENT_BEGIN_PREP */ 1623 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1624 #define SUPPORT_SYSRQ 1625 #endif 1626 #define SCCNXP_NAME "uart-sccnxp" 1627 #define SCCNXP_MAJOR 204 1628 #define SCCNXP_MINOR 205 1629 #define SCCNXP_MR_REG (0x00) 1630 # define MR0_BAUD_NORMAL (0 << 0) 1631 # define MR0_BAUD_EXT1 (1 << 0) 1632 # define MR0_BAUD_EXT2 (5 << 0) 1633 # define MR0_FIFO (1 << 3) 1634 # define MR0_TXLVL (1 << 4) 1635 # define MR1_BITS_5 (0 << 0) 1636 # define MR1_BITS_6 (1 << 0) 1637 # define MR1_BITS_7 (2 << 0) 1638 # define MR1_BITS_8 (3 << 0) 1639 # define MR1_PAR_EVN (0 << 2) 1640 # define MR1_PAR_ODD (1 << 2) 1641 # define MR1_PAR_NO (4 << 2) 1642 # define MR2_STOP1 (7 << 0) 1643 # define MR2_STOP2 (0xf << 0) 1644 #define SCCNXP_SR_REG (0x01) 1645 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1646 # define SR_RXRDY (1 << 0) 1647 # define SR_FULL (1 << 1) 1648 # define SR_TXRDY (1 << 2) 1649 # define SR_TXEMT (1 << 3) 1650 # define SR_OVR (1 << 4) 1651 # define SR_PE (1 << 5) 1652 # define SR_FE (1 << 6) 1653 # define SR_BRK (1 << 7) 1654 #define SCCNXP_CR_REG (0x02) 1655 # define CR_RX_ENABLE (1 << 0) 1656 # define CR_RX_DISABLE (1 << 1) 1657 # define CR_TX_ENABLE (1 << 2) 1658 # define CR_TX_DISABLE (1 << 3) 1659 # define CR_CMD_MRPTR1 (0x01 << 4) 1660 # define CR_CMD_RX_RESET (0x02 << 4) 1661 # define CR_CMD_TX_RESET (0x03 << 4) 1662 # define CR_CMD_STATUS_RESET (0x04 << 4) 1663 # define CR_CMD_BREAK_RESET (0x05 << 4) 1664 # define CR_CMD_START_BREAK (0x06 << 4) 1665 # define CR_CMD_STOP_BREAK (0x07 << 4) 1666 # define CR_CMD_MRPTR0 (0x0b << 4) 1667 #define SCCNXP_RHR_REG (0x03) 1668 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1669 #define SCCNXP_IPCR_REG (0x04) 1670 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1671 # define ACR_BAUD0 (0 << 7) 1672 # define ACR_BAUD1 (1 << 7) 1673 # define ACR_TIMER_MODE (6 << 4) 1674 #define SCCNXP_ISR_REG (0x05) 1675 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1676 # define IMR_TXRDY (1 << 0) 1677 # define IMR_RXRDY (1 << 1) 1678 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1679 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1680 #define SCCNXP_IPR_REG (0x0d) 1681 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1682 #define SCCNXP_SOP_REG (0x0e) 1683 #define SCCNXP_ROP_REG (0x0f) 1684 #define MCTRL_MASK(sig) (0xf << (sig)) 1685 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1686 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1687 #define SCCNXP_HAVE_IO 0x00000001 1688 #define SCCNXP_HAVE_MR0 0x00000002 1689 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1690 #endif 1691 /* LDV_COMMENT_END_PREP */ 1692 /* LDV_COMMENT_BEGIN_PREP */ 1693 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1694 #endif 1695 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1696 #endif 1697 /* LDV_COMMENT_END_PREP */ 1698 /* content: static void sccnxp_shutdown(struct uart_port *port)*/ 1699 /* LDV_COMMENT_BEGIN_PREP */ 1700 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1701 #define SUPPORT_SYSRQ 1702 #endif 1703 #define SCCNXP_NAME "uart-sccnxp" 1704 #define SCCNXP_MAJOR 204 1705 #define SCCNXP_MINOR 205 1706 #define SCCNXP_MR_REG (0x00) 1707 # define MR0_BAUD_NORMAL (0 << 0) 1708 # define MR0_BAUD_EXT1 (1 << 0) 1709 # define MR0_BAUD_EXT2 (5 << 0) 1710 # define MR0_FIFO (1 << 3) 1711 # define MR0_TXLVL (1 << 4) 1712 # define MR1_BITS_5 (0 << 0) 1713 # define MR1_BITS_6 (1 << 0) 1714 # define MR1_BITS_7 (2 << 0) 1715 # define MR1_BITS_8 (3 << 0) 1716 # define MR1_PAR_EVN (0 << 2) 1717 # define MR1_PAR_ODD (1 << 2) 1718 # define MR1_PAR_NO (4 << 2) 1719 # define MR2_STOP1 (7 << 0) 1720 # define MR2_STOP2 (0xf << 0) 1721 #define SCCNXP_SR_REG (0x01) 1722 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1723 # define SR_RXRDY (1 << 0) 1724 # define SR_FULL (1 << 1) 1725 # define SR_TXRDY (1 << 2) 1726 # define SR_TXEMT (1 << 3) 1727 # define SR_OVR (1 << 4) 1728 # define SR_PE (1 << 5) 1729 # define SR_FE (1 << 6) 1730 # define SR_BRK (1 << 7) 1731 #define SCCNXP_CR_REG (0x02) 1732 # define CR_RX_ENABLE (1 << 0) 1733 # define CR_RX_DISABLE (1 << 1) 1734 # define CR_TX_ENABLE (1 << 2) 1735 # define CR_TX_DISABLE (1 << 3) 1736 # define CR_CMD_MRPTR1 (0x01 << 4) 1737 # define CR_CMD_RX_RESET (0x02 << 4) 1738 # define CR_CMD_TX_RESET (0x03 << 4) 1739 # define CR_CMD_STATUS_RESET (0x04 << 4) 1740 # define CR_CMD_BREAK_RESET (0x05 << 4) 1741 # define CR_CMD_START_BREAK (0x06 << 4) 1742 # define CR_CMD_STOP_BREAK (0x07 << 4) 1743 # define CR_CMD_MRPTR0 (0x0b << 4) 1744 #define SCCNXP_RHR_REG (0x03) 1745 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1746 #define SCCNXP_IPCR_REG (0x04) 1747 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1748 # define ACR_BAUD0 (0 << 7) 1749 # define ACR_BAUD1 (1 << 7) 1750 # define ACR_TIMER_MODE (6 << 4) 1751 #define SCCNXP_ISR_REG (0x05) 1752 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1753 # define IMR_TXRDY (1 << 0) 1754 # define IMR_RXRDY (1 << 1) 1755 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1756 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1757 #define SCCNXP_IPR_REG (0x0d) 1758 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1759 #define SCCNXP_SOP_REG (0x0e) 1760 #define SCCNXP_ROP_REG (0x0f) 1761 #define MCTRL_MASK(sig) (0xf << (sig)) 1762 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1763 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1764 #define SCCNXP_HAVE_IO 0x00000001 1765 #define SCCNXP_HAVE_MR0 0x00000002 1766 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1767 #endif 1768 /* LDV_COMMENT_END_PREP */ 1769 /* LDV_COMMENT_BEGIN_PREP */ 1770 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1771 #endif 1772 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1773 #endif 1774 /* LDV_COMMENT_END_PREP */ 1775 /* content: static void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)*/ 1776 /* LDV_COMMENT_BEGIN_PREP */ 1777 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1778 #define SUPPORT_SYSRQ 1779 #endif 1780 #define SCCNXP_NAME "uart-sccnxp" 1781 #define SCCNXP_MAJOR 204 1782 #define SCCNXP_MINOR 205 1783 #define SCCNXP_MR_REG (0x00) 1784 # define MR0_BAUD_NORMAL (0 << 0) 1785 # define MR0_BAUD_EXT1 (1 << 0) 1786 # define MR0_BAUD_EXT2 (5 << 0) 1787 # define MR0_FIFO (1 << 3) 1788 # define MR0_TXLVL (1 << 4) 1789 # define MR1_BITS_5 (0 << 0) 1790 # define MR1_BITS_6 (1 << 0) 1791 # define MR1_BITS_7 (2 << 0) 1792 # define MR1_BITS_8 (3 << 0) 1793 # define MR1_PAR_EVN (0 << 2) 1794 # define MR1_PAR_ODD (1 << 2) 1795 # define MR1_PAR_NO (4 << 2) 1796 # define MR2_STOP1 (7 << 0) 1797 # define MR2_STOP2 (0xf << 0) 1798 #define SCCNXP_SR_REG (0x01) 1799 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1800 # define SR_RXRDY (1 << 0) 1801 # define SR_FULL (1 << 1) 1802 # define SR_TXRDY (1 << 2) 1803 # define SR_TXEMT (1 << 3) 1804 # define SR_OVR (1 << 4) 1805 # define SR_PE (1 << 5) 1806 # define SR_FE (1 << 6) 1807 # define SR_BRK (1 << 7) 1808 #define SCCNXP_CR_REG (0x02) 1809 # define CR_RX_ENABLE (1 << 0) 1810 # define CR_RX_DISABLE (1 << 1) 1811 # define CR_TX_ENABLE (1 << 2) 1812 # define CR_TX_DISABLE (1 << 3) 1813 # define CR_CMD_MRPTR1 (0x01 << 4) 1814 # define CR_CMD_RX_RESET (0x02 << 4) 1815 # define CR_CMD_TX_RESET (0x03 << 4) 1816 # define CR_CMD_STATUS_RESET (0x04 << 4) 1817 # define CR_CMD_BREAK_RESET (0x05 << 4) 1818 # define CR_CMD_START_BREAK (0x06 << 4) 1819 # define CR_CMD_STOP_BREAK (0x07 << 4) 1820 # define CR_CMD_MRPTR0 (0x0b << 4) 1821 #define SCCNXP_RHR_REG (0x03) 1822 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1823 #define SCCNXP_IPCR_REG (0x04) 1824 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1825 # define ACR_BAUD0 (0 << 7) 1826 # define ACR_BAUD1 (1 << 7) 1827 # define ACR_TIMER_MODE (6 << 4) 1828 #define SCCNXP_ISR_REG (0x05) 1829 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1830 # define IMR_TXRDY (1 << 0) 1831 # define IMR_RXRDY (1 << 1) 1832 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1833 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1834 #define SCCNXP_IPR_REG (0x0d) 1835 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1836 #define SCCNXP_SOP_REG (0x0e) 1837 #define SCCNXP_ROP_REG (0x0f) 1838 #define MCTRL_MASK(sig) (0xf << (sig)) 1839 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1840 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1841 #define SCCNXP_HAVE_IO 0x00000001 1842 #define SCCNXP_HAVE_MR0 0x00000002 1843 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1844 #endif 1845 /* LDV_COMMENT_END_PREP */ 1846 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_termios" */ 1847 struct ktermios * var_group2; 1848 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_termios" */ 1849 struct ktermios * var_sccnxp_set_termios_21_p2; 1850 /* LDV_COMMENT_BEGIN_PREP */ 1851 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1852 #endif 1853 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1854 #endif 1855 /* LDV_COMMENT_END_PREP */ 1856 /* content: static const char *sccnxp_type(struct uart_port *port)*/ 1857 /* LDV_COMMENT_BEGIN_PREP */ 1858 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1859 #define SUPPORT_SYSRQ 1860 #endif 1861 #define SCCNXP_NAME "uart-sccnxp" 1862 #define SCCNXP_MAJOR 204 1863 #define SCCNXP_MINOR 205 1864 #define SCCNXP_MR_REG (0x00) 1865 # define MR0_BAUD_NORMAL (0 << 0) 1866 # define MR0_BAUD_EXT1 (1 << 0) 1867 # define MR0_BAUD_EXT2 (5 << 0) 1868 # define MR0_FIFO (1 << 3) 1869 # define MR0_TXLVL (1 << 4) 1870 # define MR1_BITS_5 (0 << 0) 1871 # define MR1_BITS_6 (1 << 0) 1872 # define MR1_BITS_7 (2 << 0) 1873 # define MR1_BITS_8 (3 << 0) 1874 # define MR1_PAR_EVN (0 << 2) 1875 # define MR1_PAR_ODD (1 << 2) 1876 # define MR1_PAR_NO (4 << 2) 1877 # define MR2_STOP1 (7 << 0) 1878 # define MR2_STOP2 (0xf << 0) 1879 #define SCCNXP_SR_REG (0x01) 1880 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1881 # define SR_RXRDY (1 << 0) 1882 # define SR_FULL (1 << 1) 1883 # define SR_TXRDY (1 << 2) 1884 # define SR_TXEMT (1 << 3) 1885 # define SR_OVR (1 << 4) 1886 # define SR_PE (1 << 5) 1887 # define SR_FE (1 << 6) 1888 # define SR_BRK (1 << 7) 1889 #define SCCNXP_CR_REG (0x02) 1890 # define CR_RX_ENABLE (1 << 0) 1891 # define CR_RX_DISABLE (1 << 1) 1892 # define CR_TX_ENABLE (1 << 2) 1893 # define CR_TX_DISABLE (1 << 3) 1894 # define CR_CMD_MRPTR1 (0x01 << 4) 1895 # define CR_CMD_RX_RESET (0x02 << 4) 1896 # define CR_CMD_TX_RESET (0x03 << 4) 1897 # define CR_CMD_STATUS_RESET (0x04 << 4) 1898 # define CR_CMD_BREAK_RESET (0x05 << 4) 1899 # define CR_CMD_START_BREAK (0x06 << 4) 1900 # define CR_CMD_STOP_BREAK (0x07 << 4) 1901 # define CR_CMD_MRPTR0 (0x0b << 4) 1902 #define SCCNXP_RHR_REG (0x03) 1903 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1904 #define SCCNXP_IPCR_REG (0x04) 1905 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1906 # define ACR_BAUD0 (0 << 7) 1907 # define ACR_BAUD1 (1 << 7) 1908 # define ACR_TIMER_MODE (6 << 4) 1909 #define SCCNXP_ISR_REG (0x05) 1910 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1911 # define IMR_TXRDY (1 << 0) 1912 # define IMR_RXRDY (1 << 1) 1913 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1914 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1915 #define SCCNXP_IPR_REG (0x0d) 1916 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1917 #define SCCNXP_SOP_REG (0x0e) 1918 #define SCCNXP_ROP_REG (0x0f) 1919 #define MCTRL_MASK(sig) (0xf << (sig)) 1920 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1921 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1922 #define SCCNXP_HAVE_IO 0x00000001 1923 #define SCCNXP_HAVE_MR0 0x00000002 1924 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1925 #endif 1926 /* LDV_COMMENT_END_PREP */ 1927 /* LDV_COMMENT_BEGIN_PREP */ 1928 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1929 #endif 1930 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1931 #endif 1932 /* LDV_COMMENT_END_PREP */ 1933 /* content: static void sccnxp_release_port(struct uart_port *port)*/ 1934 /* LDV_COMMENT_BEGIN_PREP */ 1935 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1936 #define SUPPORT_SYSRQ 1937 #endif 1938 #define SCCNXP_NAME "uart-sccnxp" 1939 #define SCCNXP_MAJOR 204 1940 #define SCCNXP_MINOR 205 1941 #define SCCNXP_MR_REG (0x00) 1942 # define MR0_BAUD_NORMAL (0 << 0) 1943 # define MR0_BAUD_EXT1 (1 << 0) 1944 # define MR0_BAUD_EXT2 (5 << 0) 1945 # define MR0_FIFO (1 << 3) 1946 # define MR0_TXLVL (1 << 4) 1947 # define MR1_BITS_5 (0 << 0) 1948 # define MR1_BITS_6 (1 << 0) 1949 # define MR1_BITS_7 (2 << 0) 1950 # define MR1_BITS_8 (3 << 0) 1951 # define MR1_PAR_EVN (0 << 2) 1952 # define MR1_PAR_ODD (1 << 2) 1953 # define MR1_PAR_NO (4 << 2) 1954 # define MR2_STOP1 (7 << 0) 1955 # define MR2_STOP2 (0xf << 0) 1956 #define SCCNXP_SR_REG (0x01) 1957 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1958 # define SR_RXRDY (1 << 0) 1959 # define SR_FULL (1 << 1) 1960 # define SR_TXRDY (1 << 2) 1961 # define SR_TXEMT (1 << 3) 1962 # define SR_OVR (1 << 4) 1963 # define SR_PE (1 << 5) 1964 # define SR_FE (1 << 6) 1965 # define SR_BRK (1 << 7) 1966 #define SCCNXP_CR_REG (0x02) 1967 # define CR_RX_ENABLE (1 << 0) 1968 # define CR_RX_DISABLE (1 << 1) 1969 # define CR_TX_ENABLE (1 << 2) 1970 # define CR_TX_DISABLE (1 << 3) 1971 # define CR_CMD_MRPTR1 (0x01 << 4) 1972 # define CR_CMD_RX_RESET (0x02 << 4) 1973 # define CR_CMD_TX_RESET (0x03 << 4) 1974 # define CR_CMD_STATUS_RESET (0x04 << 4) 1975 # define CR_CMD_BREAK_RESET (0x05 << 4) 1976 # define CR_CMD_START_BREAK (0x06 << 4) 1977 # define CR_CMD_STOP_BREAK (0x07 << 4) 1978 # define CR_CMD_MRPTR0 (0x0b << 4) 1979 #define SCCNXP_RHR_REG (0x03) 1980 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1981 #define SCCNXP_IPCR_REG (0x04) 1982 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1983 # define ACR_BAUD0 (0 << 7) 1984 # define ACR_BAUD1 (1 << 7) 1985 # define ACR_TIMER_MODE (6 << 4) 1986 #define SCCNXP_ISR_REG (0x05) 1987 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1988 # define IMR_TXRDY (1 << 0) 1989 # define IMR_RXRDY (1 << 1) 1990 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1991 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1992 #define SCCNXP_IPR_REG (0x0d) 1993 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1994 #define SCCNXP_SOP_REG (0x0e) 1995 #define SCCNXP_ROP_REG (0x0f) 1996 #define MCTRL_MASK(sig) (0xf << (sig)) 1997 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1998 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1999 #define SCCNXP_HAVE_IO 0x00000001 2000 #define SCCNXP_HAVE_MR0 0x00000002 2001 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2002 #endif 2003 /* LDV_COMMENT_END_PREP */ 2004 /* LDV_COMMENT_BEGIN_PREP */ 2005 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2006 #endif 2007 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2008 #endif 2009 /* LDV_COMMENT_END_PREP */ 2010 /* content: static int sccnxp_request_port(struct uart_port *port)*/ 2011 /* LDV_COMMENT_BEGIN_PREP */ 2012 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2013 #define SUPPORT_SYSRQ 2014 #endif 2015 #define SCCNXP_NAME "uart-sccnxp" 2016 #define SCCNXP_MAJOR 204 2017 #define SCCNXP_MINOR 205 2018 #define SCCNXP_MR_REG (0x00) 2019 # define MR0_BAUD_NORMAL (0 << 0) 2020 # define MR0_BAUD_EXT1 (1 << 0) 2021 # define MR0_BAUD_EXT2 (5 << 0) 2022 # define MR0_FIFO (1 << 3) 2023 # define MR0_TXLVL (1 << 4) 2024 # define MR1_BITS_5 (0 << 0) 2025 # define MR1_BITS_6 (1 << 0) 2026 # define MR1_BITS_7 (2 << 0) 2027 # define MR1_BITS_8 (3 << 0) 2028 # define MR1_PAR_EVN (0 << 2) 2029 # define MR1_PAR_ODD (1 << 2) 2030 # define MR1_PAR_NO (4 << 2) 2031 # define MR2_STOP1 (7 << 0) 2032 # define MR2_STOP2 (0xf << 0) 2033 #define SCCNXP_SR_REG (0x01) 2034 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2035 # define SR_RXRDY (1 << 0) 2036 # define SR_FULL (1 << 1) 2037 # define SR_TXRDY (1 << 2) 2038 # define SR_TXEMT (1 << 3) 2039 # define SR_OVR (1 << 4) 2040 # define SR_PE (1 << 5) 2041 # define SR_FE (1 << 6) 2042 # define SR_BRK (1 << 7) 2043 #define SCCNXP_CR_REG (0x02) 2044 # define CR_RX_ENABLE (1 << 0) 2045 # define CR_RX_DISABLE (1 << 1) 2046 # define CR_TX_ENABLE (1 << 2) 2047 # define CR_TX_DISABLE (1 << 3) 2048 # define CR_CMD_MRPTR1 (0x01 << 4) 2049 # define CR_CMD_RX_RESET (0x02 << 4) 2050 # define CR_CMD_TX_RESET (0x03 << 4) 2051 # define CR_CMD_STATUS_RESET (0x04 << 4) 2052 # define CR_CMD_BREAK_RESET (0x05 << 4) 2053 # define CR_CMD_START_BREAK (0x06 << 4) 2054 # define CR_CMD_STOP_BREAK (0x07 << 4) 2055 # define CR_CMD_MRPTR0 (0x0b << 4) 2056 #define SCCNXP_RHR_REG (0x03) 2057 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2058 #define SCCNXP_IPCR_REG (0x04) 2059 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2060 # define ACR_BAUD0 (0 << 7) 2061 # define ACR_BAUD1 (1 << 7) 2062 # define ACR_TIMER_MODE (6 << 4) 2063 #define SCCNXP_ISR_REG (0x05) 2064 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2065 # define IMR_TXRDY (1 << 0) 2066 # define IMR_RXRDY (1 << 1) 2067 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2068 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2069 #define SCCNXP_IPR_REG (0x0d) 2070 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2071 #define SCCNXP_SOP_REG (0x0e) 2072 #define SCCNXP_ROP_REG (0x0f) 2073 #define MCTRL_MASK(sig) (0xf << (sig)) 2074 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2075 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2076 #define SCCNXP_HAVE_IO 0x00000001 2077 #define SCCNXP_HAVE_MR0 0x00000002 2078 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2079 #endif 2080 /* LDV_COMMENT_END_PREP */ 2081 /* LDV_COMMENT_BEGIN_PREP */ 2082 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2083 #endif 2084 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2085 #endif 2086 /* LDV_COMMENT_END_PREP */ 2087 /* content: static void sccnxp_config_port(struct uart_port *port, int flags)*/ 2088 /* LDV_COMMENT_BEGIN_PREP */ 2089 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2090 #define SUPPORT_SYSRQ 2091 #endif 2092 #define SCCNXP_NAME "uart-sccnxp" 2093 #define SCCNXP_MAJOR 204 2094 #define SCCNXP_MINOR 205 2095 #define SCCNXP_MR_REG (0x00) 2096 # define MR0_BAUD_NORMAL (0 << 0) 2097 # define MR0_BAUD_EXT1 (1 << 0) 2098 # define MR0_BAUD_EXT2 (5 << 0) 2099 # define MR0_FIFO (1 << 3) 2100 # define MR0_TXLVL (1 << 4) 2101 # define MR1_BITS_5 (0 << 0) 2102 # define MR1_BITS_6 (1 << 0) 2103 # define MR1_BITS_7 (2 << 0) 2104 # define MR1_BITS_8 (3 << 0) 2105 # define MR1_PAR_EVN (0 << 2) 2106 # define MR1_PAR_ODD (1 << 2) 2107 # define MR1_PAR_NO (4 << 2) 2108 # define MR2_STOP1 (7 << 0) 2109 # define MR2_STOP2 (0xf << 0) 2110 #define SCCNXP_SR_REG (0x01) 2111 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2112 # define SR_RXRDY (1 << 0) 2113 # define SR_FULL (1 << 1) 2114 # define SR_TXRDY (1 << 2) 2115 # define SR_TXEMT (1 << 3) 2116 # define SR_OVR (1 << 4) 2117 # define SR_PE (1 << 5) 2118 # define SR_FE (1 << 6) 2119 # define SR_BRK (1 << 7) 2120 #define SCCNXP_CR_REG (0x02) 2121 # define CR_RX_ENABLE (1 << 0) 2122 # define CR_RX_DISABLE (1 << 1) 2123 # define CR_TX_ENABLE (1 << 2) 2124 # define CR_TX_DISABLE (1 << 3) 2125 # define CR_CMD_MRPTR1 (0x01 << 4) 2126 # define CR_CMD_RX_RESET (0x02 << 4) 2127 # define CR_CMD_TX_RESET (0x03 << 4) 2128 # define CR_CMD_STATUS_RESET (0x04 << 4) 2129 # define CR_CMD_BREAK_RESET (0x05 << 4) 2130 # define CR_CMD_START_BREAK (0x06 << 4) 2131 # define CR_CMD_STOP_BREAK (0x07 << 4) 2132 # define CR_CMD_MRPTR0 (0x0b << 4) 2133 #define SCCNXP_RHR_REG (0x03) 2134 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2135 #define SCCNXP_IPCR_REG (0x04) 2136 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2137 # define ACR_BAUD0 (0 << 7) 2138 # define ACR_BAUD1 (1 << 7) 2139 # define ACR_TIMER_MODE (6 << 4) 2140 #define SCCNXP_ISR_REG (0x05) 2141 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2142 # define IMR_TXRDY (1 << 0) 2143 # define IMR_RXRDY (1 << 1) 2144 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2145 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2146 #define SCCNXP_IPR_REG (0x0d) 2147 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2148 #define SCCNXP_SOP_REG (0x0e) 2149 #define SCCNXP_ROP_REG (0x0f) 2150 #define MCTRL_MASK(sig) (0xf << (sig)) 2151 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2152 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2153 #define SCCNXP_HAVE_IO 0x00000001 2154 #define SCCNXP_HAVE_MR0 0x00000002 2155 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2156 #endif 2157 /* LDV_COMMENT_END_PREP */ 2158 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_config_port" */ 2159 int var_sccnxp_config_port_27_p1; 2160 /* LDV_COMMENT_BEGIN_PREP */ 2161 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2162 #endif 2163 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2164 #endif 2165 /* LDV_COMMENT_END_PREP */ 2166 /* content: static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)*/ 2167 /* LDV_COMMENT_BEGIN_PREP */ 2168 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2169 #define SUPPORT_SYSRQ 2170 #endif 2171 #define SCCNXP_NAME "uart-sccnxp" 2172 #define SCCNXP_MAJOR 204 2173 #define SCCNXP_MINOR 205 2174 #define SCCNXP_MR_REG (0x00) 2175 # define MR0_BAUD_NORMAL (0 << 0) 2176 # define MR0_BAUD_EXT1 (1 << 0) 2177 # define MR0_BAUD_EXT2 (5 << 0) 2178 # define MR0_FIFO (1 << 3) 2179 # define MR0_TXLVL (1 << 4) 2180 # define MR1_BITS_5 (0 << 0) 2181 # define MR1_BITS_6 (1 << 0) 2182 # define MR1_BITS_7 (2 << 0) 2183 # define MR1_BITS_8 (3 << 0) 2184 # define MR1_PAR_EVN (0 << 2) 2185 # define MR1_PAR_ODD (1 << 2) 2186 # define MR1_PAR_NO (4 << 2) 2187 # define MR2_STOP1 (7 << 0) 2188 # define MR2_STOP2 (0xf << 0) 2189 #define SCCNXP_SR_REG (0x01) 2190 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2191 # define SR_RXRDY (1 << 0) 2192 # define SR_FULL (1 << 1) 2193 # define SR_TXRDY (1 << 2) 2194 # define SR_TXEMT (1 << 3) 2195 # define SR_OVR (1 << 4) 2196 # define SR_PE (1 << 5) 2197 # define SR_FE (1 << 6) 2198 # define SR_BRK (1 << 7) 2199 #define SCCNXP_CR_REG (0x02) 2200 # define CR_RX_ENABLE (1 << 0) 2201 # define CR_RX_DISABLE (1 << 1) 2202 # define CR_TX_ENABLE (1 << 2) 2203 # define CR_TX_DISABLE (1 << 3) 2204 # define CR_CMD_MRPTR1 (0x01 << 4) 2205 # define CR_CMD_RX_RESET (0x02 << 4) 2206 # define CR_CMD_TX_RESET (0x03 << 4) 2207 # define CR_CMD_STATUS_RESET (0x04 << 4) 2208 # define CR_CMD_BREAK_RESET (0x05 << 4) 2209 # define CR_CMD_START_BREAK (0x06 << 4) 2210 # define CR_CMD_STOP_BREAK (0x07 << 4) 2211 # define CR_CMD_MRPTR0 (0x0b << 4) 2212 #define SCCNXP_RHR_REG (0x03) 2213 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2214 #define SCCNXP_IPCR_REG (0x04) 2215 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2216 # define ACR_BAUD0 (0 << 7) 2217 # define ACR_BAUD1 (1 << 7) 2218 # define ACR_TIMER_MODE (6 << 4) 2219 #define SCCNXP_ISR_REG (0x05) 2220 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2221 # define IMR_TXRDY (1 << 0) 2222 # define IMR_RXRDY (1 << 1) 2223 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2224 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2225 #define SCCNXP_IPR_REG (0x0d) 2226 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2227 #define SCCNXP_SOP_REG (0x0e) 2228 #define SCCNXP_ROP_REG (0x0f) 2229 #define MCTRL_MASK(sig) (0xf << (sig)) 2230 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2231 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2232 #define SCCNXP_HAVE_IO 0x00000001 2233 #define SCCNXP_HAVE_MR0 0x00000002 2234 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2235 #endif 2236 /* LDV_COMMENT_END_PREP */ 2237 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_verify_port" */ 2238 struct serial_struct * var_group3; 2239 /* LDV_COMMENT_BEGIN_PREP */ 2240 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2241 #endif 2242 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2243 #endif 2244 /* LDV_COMMENT_END_PREP */ 2245 2246 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/ 2247 /* content: static int sccnxp_probe(struct platform_device *pdev)*/ 2248 /* LDV_COMMENT_BEGIN_PREP */ 2249 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2250 #define SUPPORT_SYSRQ 2251 #endif 2252 #define SCCNXP_NAME "uart-sccnxp" 2253 #define SCCNXP_MAJOR 204 2254 #define SCCNXP_MINOR 205 2255 #define SCCNXP_MR_REG (0x00) 2256 # define MR0_BAUD_NORMAL (0 << 0) 2257 # define MR0_BAUD_EXT1 (1 << 0) 2258 # define MR0_BAUD_EXT2 (5 << 0) 2259 # define MR0_FIFO (1 << 3) 2260 # define MR0_TXLVL (1 << 4) 2261 # define MR1_BITS_5 (0 << 0) 2262 # define MR1_BITS_6 (1 << 0) 2263 # define MR1_BITS_7 (2 << 0) 2264 # define MR1_BITS_8 (3 << 0) 2265 # define MR1_PAR_EVN (0 << 2) 2266 # define MR1_PAR_ODD (1 << 2) 2267 # define MR1_PAR_NO (4 << 2) 2268 # define MR2_STOP1 (7 << 0) 2269 # define MR2_STOP2 (0xf << 0) 2270 #define SCCNXP_SR_REG (0x01) 2271 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2272 # define SR_RXRDY (1 << 0) 2273 # define SR_FULL (1 << 1) 2274 # define SR_TXRDY (1 << 2) 2275 # define SR_TXEMT (1 << 3) 2276 # define SR_OVR (1 << 4) 2277 # define SR_PE (1 << 5) 2278 # define SR_FE (1 << 6) 2279 # define SR_BRK (1 << 7) 2280 #define SCCNXP_CR_REG (0x02) 2281 # define CR_RX_ENABLE (1 << 0) 2282 # define CR_RX_DISABLE (1 << 1) 2283 # define CR_TX_ENABLE (1 << 2) 2284 # define CR_TX_DISABLE (1 << 3) 2285 # define CR_CMD_MRPTR1 (0x01 << 4) 2286 # define CR_CMD_RX_RESET (0x02 << 4) 2287 # define CR_CMD_TX_RESET (0x03 << 4) 2288 # define CR_CMD_STATUS_RESET (0x04 << 4) 2289 # define CR_CMD_BREAK_RESET (0x05 << 4) 2290 # define CR_CMD_START_BREAK (0x06 << 4) 2291 # define CR_CMD_STOP_BREAK (0x07 << 4) 2292 # define CR_CMD_MRPTR0 (0x0b << 4) 2293 #define SCCNXP_RHR_REG (0x03) 2294 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2295 #define SCCNXP_IPCR_REG (0x04) 2296 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2297 # define ACR_BAUD0 (0 << 7) 2298 # define ACR_BAUD1 (1 << 7) 2299 # define ACR_TIMER_MODE (6 << 4) 2300 #define SCCNXP_ISR_REG (0x05) 2301 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2302 # define IMR_TXRDY (1 << 0) 2303 # define IMR_RXRDY (1 << 1) 2304 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2305 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2306 #define SCCNXP_IPR_REG (0x0d) 2307 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2308 #define SCCNXP_SOP_REG (0x0e) 2309 #define SCCNXP_ROP_REG (0x0f) 2310 #define MCTRL_MASK(sig) (0xf << (sig)) 2311 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2312 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2313 #define SCCNXP_HAVE_IO 0x00000001 2314 #define SCCNXP_HAVE_MR0 0x00000002 2315 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2316 #endif 2317 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2318 #endif 2319 /* LDV_COMMENT_END_PREP */ 2320 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_probe" */ 2321 struct platform_device * var_group4; 2322 /* LDV_COMMENT_VAR_DECLARE Variable declaration for test return result from function call "sccnxp_probe" */ 2323 static int res_sccnxp_probe_32; 2324 /* content: static int sccnxp_remove(struct platform_device *pdev)*/ 2325 /* LDV_COMMENT_BEGIN_PREP */ 2326 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2327 #define SUPPORT_SYSRQ 2328 #endif 2329 #define SCCNXP_NAME "uart-sccnxp" 2330 #define SCCNXP_MAJOR 204 2331 #define SCCNXP_MINOR 205 2332 #define SCCNXP_MR_REG (0x00) 2333 # define MR0_BAUD_NORMAL (0 << 0) 2334 # define MR0_BAUD_EXT1 (1 << 0) 2335 # define MR0_BAUD_EXT2 (5 << 0) 2336 # define MR0_FIFO (1 << 3) 2337 # define MR0_TXLVL (1 << 4) 2338 # define MR1_BITS_5 (0 << 0) 2339 # define MR1_BITS_6 (1 << 0) 2340 # define MR1_BITS_7 (2 << 0) 2341 # define MR1_BITS_8 (3 << 0) 2342 # define MR1_PAR_EVN (0 << 2) 2343 # define MR1_PAR_ODD (1 << 2) 2344 # define MR1_PAR_NO (4 << 2) 2345 # define MR2_STOP1 (7 << 0) 2346 # define MR2_STOP2 (0xf << 0) 2347 #define SCCNXP_SR_REG (0x01) 2348 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2349 # define SR_RXRDY (1 << 0) 2350 # define SR_FULL (1 << 1) 2351 # define SR_TXRDY (1 << 2) 2352 # define SR_TXEMT (1 << 3) 2353 # define SR_OVR (1 << 4) 2354 # define SR_PE (1 << 5) 2355 # define SR_FE (1 << 6) 2356 # define SR_BRK (1 << 7) 2357 #define SCCNXP_CR_REG (0x02) 2358 # define CR_RX_ENABLE (1 << 0) 2359 # define CR_RX_DISABLE (1 << 1) 2360 # define CR_TX_ENABLE (1 << 2) 2361 # define CR_TX_DISABLE (1 << 3) 2362 # define CR_CMD_MRPTR1 (0x01 << 4) 2363 # define CR_CMD_RX_RESET (0x02 << 4) 2364 # define CR_CMD_TX_RESET (0x03 << 4) 2365 # define CR_CMD_STATUS_RESET (0x04 << 4) 2366 # define CR_CMD_BREAK_RESET (0x05 << 4) 2367 # define CR_CMD_START_BREAK (0x06 << 4) 2368 # define CR_CMD_STOP_BREAK (0x07 << 4) 2369 # define CR_CMD_MRPTR0 (0x0b << 4) 2370 #define SCCNXP_RHR_REG (0x03) 2371 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2372 #define SCCNXP_IPCR_REG (0x04) 2373 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2374 # define ACR_BAUD0 (0 << 7) 2375 # define ACR_BAUD1 (1 << 7) 2376 # define ACR_TIMER_MODE (6 << 4) 2377 #define SCCNXP_ISR_REG (0x05) 2378 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2379 # define IMR_TXRDY (1 << 0) 2380 # define IMR_RXRDY (1 << 1) 2381 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2382 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2383 #define SCCNXP_IPR_REG (0x0d) 2384 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2385 #define SCCNXP_SOP_REG (0x0e) 2386 #define SCCNXP_ROP_REG (0x0f) 2387 #define MCTRL_MASK(sig) (0xf << (sig)) 2388 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2389 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2390 #define SCCNXP_HAVE_IO 0x00000001 2391 #define SCCNXP_HAVE_MR0 0x00000002 2392 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2393 #endif 2394 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2395 #endif 2396 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2397 #endif 2398 /* LDV_COMMENT_END_PREP */ 2399 2400 /** CALLBACK SECTION request_irq **/ 2401 /* content: static irqreturn_t sccnxp_ist(int irq, void *dev_id)*/ 2402 /* LDV_COMMENT_BEGIN_PREP */ 2403 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2404 #define SUPPORT_SYSRQ 2405 #endif 2406 #define SCCNXP_NAME "uart-sccnxp" 2407 #define SCCNXP_MAJOR 204 2408 #define SCCNXP_MINOR 205 2409 #define SCCNXP_MR_REG (0x00) 2410 # define MR0_BAUD_NORMAL (0 << 0) 2411 # define MR0_BAUD_EXT1 (1 << 0) 2412 # define MR0_BAUD_EXT2 (5 << 0) 2413 # define MR0_FIFO (1 << 3) 2414 # define MR0_TXLVL (1 << 4) 2415 # define MR1_BITS_5 (0 << 0) 2416 # define MR1_BITS_6 (1 << 0) 2417 # define MR1_BITS_7 (2 << 0) 2418 # define MR1_BITS_8 (3 << 0) 2419 # define MR1_PAR_EVN (0 << 2) 2420 # define MR1_PAR_ODD (1 << 2) 2421 # define MR1_PAR_NO (4 << 2) 2422 # define MR2_STOP1 (7 << 0) 2423 # define MR2_STOP2 (0xf << 0) 2424 #define SCCNXP_SR_REG (0x01) 2425 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2426 # define SR_RXRDY (1 << 0) 2427 # define SR_FULL (1 << 1) 2428 # define SR_TXRDY (1 << 2) 2429 # define SR_TXEMT (1 << 3) 2430 # define SR_OVR (1 << 4) 2431 # define SR_PE (1 << 5) 2432 # define SR_FE (1 << 6) 2433 # define SR_BRK (1 << 7) 2434 #define SCCNXP_CR_REG (0x02) 2435 # define CR_RX_ENABLE (1 << 0) 2436 # define CR_RX_DISABLE (1 << 1) 2437 # define CR_TX_ENABLE (1 << 2) 2438 # define CR_TX_DISABLE (1 << 3) 2439 # define CR_CMD_MRPTR1 (0x01 << 4) 2440 # define CR_CMD_RX_RESET (0x02 << 4) 2441 # define CR_CMD_TX_RESET (0x03 << 4) 2442 # define CR_CMD_STATUS_RESET (0x04 << 4) 2443 # define CR_CMD_BREAK_RESET (0x05 << 4) 2444 # define CR_CMD_START_BREAK (0x06 << 4) 2445 # define CR_CMD_STOP_BREAK (0x07 << 4) 2446 # define CR_CMD_MRPTR0 (0x0b << 4) 2447 #define SCCNXP_RHR_REG (0x03) 2448 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2449 #define SCCNXP_IPCR_REG (0x04) 2450 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2451 # define ACR_BAUD0 (0 << 7) 2452 # define ACR_BAUD1 (1 << 7) 2453 # define ACR_TIMER_MODE (6 << 4) 2454 #define SCCNXP_ISR_REG (0x05) 2455 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2456 # define IMR_TXRDY (1 << 0) 2457 # define IMR_RXRDY (1 << 1) 2458 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2459 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2460 #define SCCNXP_IPR_REG (0x0d) 2461 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2462 #define SCCNXP_SOP_REG (0x0e) 2463 #define SCCNXP_ROP_REG (0x0f) 2464 #define MCTRL_MASK(sig) (0xf << (sig)) 2465 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2466 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2467 #define SCCNXP_HAVE_IO 0x00000001 2468 #define SCCNXP_HAVE_MR0 0x00000002 2469 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2470 #endif 2471 /* LDV_COMMENT_END_PREP */ 2472 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_ist" */ 2473 int var_sccnxp_ist_13_p0; 2474 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_ist" */ 2475 void * var_sccnxp_ist_13_p1; 2476 /* LDV_COMMENT_BEGIN_PREP */ 2477 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2478 #endif 2479 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2480 #endif 2481 /* LDV_COMMENT_END_PREP */ 2482 2483 2484 2485 2486 /* LDV_COMMENT_END_VARIABLE_DECLARATION_PART */ 2487 /* LDV_COMMENT_BEGIN_VARIABLE_INITIALIZING_PART */ 2488 /*============================= VARIABLE INITIALIZING PART =============================*/ 2489 LDV_IN_INTERRUPT=1; 2490 2491 2492 2493 2494 /* LDV_COMMENT_END_VARIABLE_INITIALIZING_PART */ 2495 /* LDV_COMMENT_BEGIN_FUNCTION_CALL_SECTION */ 2496 /*============================= FUNCTION CALL SECTION =============================*/ 2497 /* LDV_COMMENT_FUNCTION_CALL Initialize LDV model. */ 2498 ldv_initialize(); 2499 2500 2501 int ldv_s_sccnxp_uart_driver_platform_driver = 0; 2502 2503 2504 2505 2506 while( nondet_int() 2507 || !(ldv_s_sccnxp_uart_driver_platform_driver == 0) 2508 ) { 2509 2510 switch(nondet_int()) { 2511 2512 case 0: { 2513 2514 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 2515 2516 2517 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/ 2518 /* LDV_COMMENT_BEGIN_PREP */ 2519 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2520 #define SUPPORT_SYSRQ 2521 #endif 2522 #define SCCNXP_NAME "uart-sccnxp" 2523 #define SCCNXP_MAJOR 204 2524 #define SCCNXP_MINOR 205 2525 #define SCCNXP_MR_REG (0x00) 2526 # define MR0_BAUD_NORMAL (0 << 0) 2527 # define MR0_BAUD_EXT1 (1 << 0) 2528 # define MR0_BAUD_EXT2 (5 << 0) 2529 # define MR0_FIFO (1 << 3) 2530 # define MR0_TXLVL (1 << 4) 2531 # define MR1_BITS_5 (0 << 0) 2532 # define MR1_BITS_6 (1 << 0) 2533 # define MR1_BITS_7 (2 << 0) 2534 # define MR1_BITS_8 (3 << 0) 2535 # define MR1_PAR_EVN (0 << 2) 2536 # define MR1_PAR_ODD (1 << 2) 2537 # define MR1_PAR_NO (4 << 2) 2538 # define MR2_STOP1 (7 << 0) 2539 # define MR2_STOP2 (0xf << 0) 2540 #define SCCNXP_SR_REG (0x01) 2541 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2542 # define SR_RXRDY (1 << 0) 2543 # define SR_FULL (1 << 1) 2544 # define SR_TXRDY (1 << 2) 2545 # define SR_TXEMT (1 << 3) 2546 # define SR_OVR (1 << 4) 2547 # define SR_PE (1 << 5) 2548 # define SR_FE (1 << 6) 2549 # define SR_BRK (1 << 7) 2550 #define SCCNXP_CR_REG (0x02) 2551 # define CR_RX_ENABLE (1 << 0) 2552 # define CR_RX_DISABLE (1 << 1) 2553 # define CR_TX_ENABLE (1 << 2) 2554 # define CR_TX_DISABLE (1 << 3) 2555 # define CR_CMD_MRPTR1 (0x01 << 4) 2556 # define CR_CMD_RX_RESET (0x02 << 4) 2557 # define CR_CMD_TX_RESET (0x03 << 4) 2558 # define CR_CMD_STATUS_RESET (0x04 << 4) 2559 # define CR_CMD_BREAK_RESET (0x05 << 4) 2560 # define CR_CMD_START_BREAK (0x06 << 4) 2561 # define CR_CMD_STOP_BREAK (0x07 << 4) 2562 # define CR_CMD_MRPTR0 (0x0b << 4) 2563 #define SCCNXP_RHR_REG (0x03) 2564 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2565 #define SCCNXP_IPCR_REG (0x04) 2566 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2567 # define ACR_BAUD0 (0 << 7) 2568 # define ACR_BAUD1 (1 << 7) 2569 # define ACR_TIMER_MODE (6 << 4) 2570 #define SCCNXP_ISR_REG (0x05) 2571 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2572 # define IMR_TXRDY (1 << 0) 2573 # define IMR_RXRDY (1 << 1) 2574 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2575 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2576 #define SCCNXP_IPR_REG (0x0d) 2577 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2578 #define SCCNXP_SOP_REG (0x0e) 2579 #define SCCNXP_ROP_REG (0x0f) 2580 #define MCTRL_MASK(sig) (0xf << (sig)) 2581 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2582 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2583 #define SCCNXP_HAVE_IO 0x00000001 2584 #define SCCNXP_HAVE_MR0 0x00000002 2585 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2586 #endif 2587 /* LDV_COMMENT_END_PREP */ 2588 /* LDV_COMMENT_FUNCTION_CALL Function from field "tx_empty" from driver structure with callbacks "sccnxp_ops" */ 2589 ldv_handler_precall(); 2590 sccnxp_tx_empty( var_group1); 2591 /* LDV_COMMENT_BEGIN_PREP */ 2592 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2593 #endif 2594 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2595 #endif 2596 /* LDV_COMMENT_END_PREP */ 2597 2598 2599 2600 2601 } 2602 2603 break; 2604 case 1: { 2605 2606 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 2607 2608 2609 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/ 2610 /* LDV_COMMENT_BEGIN_PREP */ 2611 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2612 #define SUPPORT_SYSRQ 2613 #endif 2614 #define SCCNXP_NAME "uart-sccnxp" 2615 #define SCCNXP_MAJOR 204 2616 #define SCCNXP_MINOR 205 2617 #define SCCNXP_MR_REG (0x00) 2618 # define MR0_BAUD_NORMAL (0 << 0) 2619 # define MR0_BAUD_EXT1 (1 << 0) 2620 # define MR0_BAUD_EXT2 (5 << 0) 2621 # define MR0_FIFO (1 << 3) 2622 # define MR0_TXLVL (1 << 4) 2623 # define MR1_BITS_5 (0 << 0) 2624 # define MR1_BITS_6 (1 << 0) 2625 # define MR1_BITS_7 (2 << 0) 2626 # define MR1_BITS_8 (3 << 0) 2627 # define MR1_PAR_EVN (0 << 2) 2628 # define MR1_PAR_ODD (1 << 2) 2629 # define MR1_PAR_NO (4 << 2) 2630 # define MR2_STOP1 (7 << 0) 2631 # define MR2_STOP2 (0xf << 0) 2632 #define SCCNXP_SR_REG (0x01) 2633 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2634 # define SR_RXRDY (1 << 0) 2635 # define SR_FULL (1 << 1) 2636 # define SR_TXRDY (1 << 2) 2637 # define SR_TXEMT (1 << 3) 2638 # define SR_OVR (1 << 4) 2639 # define SR_PE (1 << 5) 2640 # define SR_FE (1 << 6) 2641 # define SR_BRK (1 << 7) 2642 #define SCCNXP_CR_REG (0x02) 2643 # define CR_RX_ENABLE (1 << 0) 2644 # define CR_RX_DISABLE (1 << 1) 2645 # define CR_TX_ENABLE (1 << 2) 2646 # define CR_TX_DISABLE (1 << 3) 2647 # define CR_CMD_MRPTR1 (0x01 << 4) 2648 # define CR_CMD_RX_RESET (0x02 << 4) 2649 # define CR_CMD_TX_RESET (0x03 << 4) 2650 # define CR_CMD_STATUS_RESET (0x04 << 4) 2651 # define CR_CMD_BREAK_RESET (0x05 << 4) 2652 # define CR_CMD_START_BREAK (0x06 << 4) 2653 # define CR_CMD_STOP_BREAK (0x07 << 4) 2654 # define CR_CMD_MRPTR0 (0x0b << 4) 2655 #define SCCNXP_RHR_REG (0x03) 2656 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2657 #define SCCNXP_IPCR_REG (0x04) 2658 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2659 # define ACR_BAUD0 (0 << 7) 2660 # define ACR_BAUD1 (1 << 7) 2661 # define ACR_TIMER_MODE (6 << 4) 2662 #define SCCNXP_ISR_REG (0x05) 2663 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2664 # define IMR_TXRDY (1 << 0) 2665 # define IMR_RXRDY (1 << 1) 2666 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2667 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2668 #define SCCNXP_IPR_REG (0x0d) 2669 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2670 #define SCCNXP_SOP_REG (0x0e) 2671 #define SCCNXP_ROP_REG (0x0f) 2672 #define MCTRL_MASK(sig) (0xf << (sig)) 2673 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2674 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2675 #define SCCNXP_HAVE_IO 0x00000001 2676 #define SCCNXP_HAVE_MR0 0x00000002 2677 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2678 #endif 2679 /* LDV_COMMENT_END_PREP */ 2680 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_mctrl" from driver structure with callbacks "sccnxp_ops" */ 2681 ldv_handler_precall(); 2682 sccnxp_set_mctrl( var_group1, var_sccnxp_set_mctrl_18_p1); 2683 /* LDV_COMMENT_BEGIN_PREP */ 2684 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2685 #endif 2686 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2687 #endif 2688 /* LDV_COMMENT_END_PREP */ 2689 2690 2691 2692 2693 } 2694 2695 break; 2696 case 2: { 2697 2698 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 2699 2700 2701 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/ 2702 /* LDV_COMMENT_BEGIN_PREP */ 2703 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2704 #define SUPPORT_SYSRQ 2705 #endif 2706 #define SCCNXP_NAME "uart-sccnxp" 2707 #define SCCNXP_MAJOR 204 2708 #define SCCNXP_MINOR 205 2709 #define SCCNXP_MR_REG (0x00) 2710 # define MR0_BAUD_NORMAL (0 << 0) 2711 # define MR0_BAUD_EXT1 (1 << 0) 2712 # define MR0_BAUD_EXT2 (5 << 0) 2713 # define MR0_FIFO (1 << 3) 2714 # define MR0_TXLVL (1 << 4) 2715 # define MR1_BITS_5 (0 << 0) 2716 # define MR1_BITS_6 (1 << 0) 2717 # define MR1_BITS_7 (2 << 0) 2718 # define MR1_BITS_8 (3 << 0) 2719 # define MR1_PAR_EVN (0 << 2) 2720 # define MR1_PAR_ODD (1 << 2) 2721 # define MR1_PAR_NO (4 << 2) 2722 # define MR2_STOP1 (7 << 0) 2723 # define MR2_STOP2 (0xf << 0) 2724 #define SCCNXP_SR_REG (0x01) 2725 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2726 # define SR_RXRDY (1 << 0) 2727 # define SR_FULL (1 << 1) 2728 # define SR_TXRDY (1 << 2) 2729 # define SR_TXEMT (1 << 3) 2730 # define SR_OVR (1 << 4) 2731 # define SR_PE (1 << 5) 2732 # define SR_FE (1 << 6) 2733 # define SR_BRK (1 << 7) 2734 #define SCCNXP_CR_REG (0x02) 2735 # define CR_RX_ENABLE (1 << 0) 2736 # define CR_RX_DISABLE (1 << 1) 2737 # define CR_TX_ENABLE (1 << 2) 2738 # define CR_TX_DISABLE (1 << 3) 2739 # define CR_CMD_MRPTR1 (0x01 << 4) 2740 # define CR_CMD_RX_RESET (0x02 << 4) 2741 # define CR_CMD_TX_RESET (0x03 << 4) 2742 # define CR_CMD_STATUS_RESET (0x04 << 4) 2743 # define CR_CMD_BREAK_RESET (0x05 << 4) 2744 # define CR_CMD_START_BREAK (0x06 << 4) 2745 # define CR_CMD_STOP_BREAK (0x07 << 4) 2746 # define CR_CMD_MRPTR0 (0x0b << 4) 2747 #define SCCNXP_RHR_REG (0x03) 2748 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2749 #define SCCNXP_IPCR_REG (0x04) 2750 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2751 # define ACR_BAUD0 (0 << 7) 2752 # define ACR_BAUD1 (1 << 7) 2753 # define ACR_TIMER_MODE (6 << 4) 2754 #define SCCNXP_ISR_REG (0x05) 2755 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2756 # define IMR_TXRDY (1 << 0) 2757 # define IMR_RXRDY (1 << 1) 2758 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2759 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2760 #define SCCNXP_IPR_REG (0x0d) 2761 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2762 #define SCCNXP_SOP_REG (0x0e) 2763 #define SCCNXP_ROP_REG (0x0f) 2764 #define MCTRL_MASK(sig) (0xf << (sig)) 2765 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2766 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2767 #define SCCNXP_HAVE_IO 0x00000001 2768 #define SCCNXP_HAVE_MR0 0x00000002 2769 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2770 #endif 2771 /* LDV_COMMENT_END_PREP */ 2772 /* LDV_COMMENT_FUNCTION_CALL Function from field "get_mctrl" from driver structure with callbacks "sccnxp_ops" */ 2773 ldv_handler_precall(); 2774 sccnxp_get_mctrl( var_group1); 2775 /* LDV_COMMENT_BEGIN_PREP */ 2776 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2777 #endif 2778 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2779 #endif 2780 /* LDV_COMMENT_END_PREP */ 2781 2782 2783 2784 2785 } 2786 2787 break; 2788 case 3: { 2789 2790 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 2791 2792 2793 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/ 2794 /* LDV_COMMENT_BEGIN_PREP */ 2795 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2796 #define SUPPORT_SYSRQ 2797 #endif 2798 #define SCCNXP_NAME "uart-sccnxp" 2799 #define SCCNXP_MAJOR 204 2800 #define SCCNXP_MINOR 205 2801 #define SCCNXP_MR_REG (0x00) 2802 # define MR0_BAUD_NORMAL (0 << 0) 2803 # define MR0_BAUD_EXT1 (1 << 0) 2804 # define MR0_BAUD_EXT2 (5 << 0) 2805 # define MR0_FIFO (1 << 3) 2806 # define MR0_TXLVL (1 << 4) 2807 # define MR1_BITS_5 (0 << 0) 2808 # define MR1_BITS_6 (1 << 0) 2809 # define MR1_BITS_7 (2 << 0) 2810 # define MR1_BITS_8 (3 << 0) 2811 # define MR1_PAR_EVN (0 << 2) 2812 # define MR1_PAR_ODD (1 << 2) 2813 # define MR1_PAR_NO (4 << 2) 2814 # define MR2_STOP1 (7 << 0) 2815 # define MR2_STOP2 (0xf << 0) 2816 #define SCCNXP_SR_REG (0x01) 2817 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2818 # define SR_RXRDY (1 << 0) 2819 # define SR_FULL (1 << 1) 2820 # define SR_TXRDY (1 << 2) 2821 # define SR_TXEMT (1 << 3) 2822 # define SR_OVR (1 << 4) 2823 # define SR_PE (1 << 5) 2824 # define SR_FE (1 << 6) 2825 # define SR_BRK (1 << 7) 2826 #define SCCNXP_CR_REG (0x02) 2827 # define CR_RX_ENABLE (1 << 0) 2828 # define CR_RX_DISABLE (1 << 1) 2829 # define CR_TX_ENABLE (1 << 2) 2830 # define CR_TX_DISABLE (1 << 3) 2831 # define CR_CMD_MRPTR1 (0x01 << 4) 2832 # define CR_CMD_RX_RESET (0x02 << 4) 2833 # define CR_CMD_TX_RESET (0x03 << 4) 2834 # define CR_CMD_STATUS_RESET (0x04 << 4) 2835 # define CR_CMD_BREAK_RESET (0x05 << 4) 2836 # define CR_CMD_START_BREAK (0x06 << 4) 2837 # define CR_CMD_STOP_BREAK (0x07 << 4) 2838 # define CR_CMD_MRPTR0 (0x0b << 4) 2839 #define SCCNXP_RHR_REG (0x03) 2840 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2841 #define SCCNXP_IPCR_REG (0x04) 2842 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2843 # define ACR_BAUD0 (0 << 7) 2844 # define ACR_BAUD1 (1 << 7) 2845 # define ACR_TIMER_MODE (6 << 4) 2846 #define SCCNXP_ISR_REG (0x05) 2847 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2848 # define IMR_TXRDY (1 << 0) 2849 # define IMR_RXRDY (1 << 1) 2850 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2851 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2852 #define SCCNXP_IPR_REG (0x0d) 2853 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2854 #define SCCNXP_SOP_REG (0x0e) 2855 #define SCCNXP_ROP_REG (0x0f) 2856 #define MCTRL_MASK(sig) (0xf << (sig)) 2857 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2858 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2859 #define SCCNXP_HAVE_IO 0x00000001 2860 #define SCCNXP_HAVE_MR0 0x00000002 2861 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2862 #endif 2863 /* LDV_COMMENT_END_PREP */ 2864 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop_tx" from driver structure with callbacks "sccnxp_ops" */ 2865 ldv_handler_precall(); 2866 sccnxp_stop_tx( var_group1); 2867 /* LDV_COMMENT_BEGIN_PREP */ 2868 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2869 #endif 2870 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2871 #endif 2872 /* LDV_COMMENT_END_PREP */ 2873 2874 2875 2876 2877 } 2878 2879 break; 2880 case 4: { 2881 2882 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 2883 2884 2885 /* content: static void sccnxp_start_tx(struct uart_port *port)*/ 2886 /* LDV_COMMENT_BEGIN_PREP */ 2887 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2888 #define SUPPORT_SYSRQ 2889 #endif 2890 #define SCCNXP_NAME "uart-sccnxp" 2891 #define SCCNXP_MAJOR 204 2892 #define SCCNXP_MINOR 205 2893 #define SCCNXP_MR_REG (0x00) 2894 # define MR0_BAUD_NORMAL (0 << 0) 2895 # define MR0_BAUD_EXT1 (1 << 0) 2896 # define MR0_BAUD_EXT2 (5 << 0) 2897 # define MR0_FIFO (1 << 3) 2898 # define MR0_TXLVL (1 << 4) 2899 # define MR1_BITS_5 (0 << 0) 2900 # define MR1_BITS_6 (1 << 0) 2901 # define MR1_BITS_7 (2 << 0) 2902 # define MR1_BITS_8 (3 << 0) 2903 # define MR1_PAR_EVN (0 << 2) 2904 # define MR1_PAR_ODD (1 << 2) 2905 # define MR1_PAR_NO (4 << 2) 2906 # define MR2_STOP1 (7 << 0) 2907 # define MR2_STOP2 (0xf << 0) 2908 #define SCCNXP_SR_REG (0x01) 2909 #define SCCNXP_CSR_REG SCCNXP_SR_REG 2910 # define SR_RXRDY (1 << 0) 2911 # define SR_FULL (1 << 1) 2912 # define SR_TXRDY (1 << 2) 2913 # define SR_TXEMT (1 << 3) 2914 # define SR_OVR (1 << 4) 2915 # define SR_PE (1 << 5) 2916 # define SR_FE (1 << 6) 2917 # define SR_BRK (1 << 7) 2918 #define SCCNXP_CR_REG (0x02) 2919 # define CR_RX_ENABLE (1 << 0) 2920 # define CR_RX_DISABLE (1 << 1) 2921 # define CR_TX_ENABLE (1 << 2) 2922 # define CR_TX_DISABLE (1 << 3) 2923 # define CR_CMD_MRPTR1 (0x01 << 4) 2924 # define CR_CMD_RX_RESET (0x02 << 4) 2925 # define CR_CMD_TX_RESET (0x03 << 4) 2926 # define CR_CMD_STATUS_RESET (0x04 << 4) 2927 # define CR_CMD_BREAK_RESET (0x05 << 4) 2928 # define CR_CMD_START_BREAK (0x06 << 4) 2929 # define CR_CMD_STOP_BREAK (0x07 << 4) 2930 # define CR_CMD_MRPTR0 (0x0b << 4) 2931 #define SCCNXP_RHR_REG (0x03) 2932 #define SCCNXP_THR_REG SCCNXP_RHR_REG 2933 #define SCCNXP_IPCR_REG (0x04) 2934 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 2935 # define ACR_BAUD0 (0 << 7) 2936 # define ACR_BAUD1 (1 << 7) 2937 # define ACR_TIMER_MODE (6 << 4) 2938 #define SCCNXP_ISR_REG (0x05) 2939 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 2940 # define IMR_TXRDY (1 << 0) 2941 # define IMR_RXRDY (1 << 1) 2942 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 2943 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 2944 #define SCCNXP_IPR_REG (0x0d) 2945 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 2946 #define SCCNXP_SOP_REG (0x0e) 2947 #define SCCNXP_ROP_REG (0x0f) 2948 #define MCTRL_MASK(sig) (0xf << (sig)) 2949 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 2950 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 2951 #define SCCNXP_HAVE_IO 0x00000001 2952 #define SCCNXP_HAVE_MR0 0x00000002 2953 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2954 #endif 2955 /* LDV_COMMENT_END_PREP */ 2956 /* LDV_COMMENT_FUNCTION_CALL Function from field "start_tx" from driver structure with callbacks "sccnxp_ops" */ 2957 ldv_handler_precall(); 2958 sccnxp_start_tx( var_group1); 2959 /* LDV_COMMENT_BEGIN_PREP */ 2960 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2961 #endif 2962 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 2963 #endif 2964 /* LDV_COMMENT_END_PREP */ 2965 2966 2967 2968 2969 } 2970 2971 break; 2972 case 5: { 2973 2974 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 2975 2976 2977 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/ 2978 /* LDV_COMMENT_BEGIN_PREP */ 2979 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 2980 #define SUPPORT_SYSRQ 2981 #endif 2982 #define SCCNXP_NAME "uart-sccnxp" 2983 #define SCCNXP_MAJOR 204 2984 #define SCCNXP_MINOR 205 2985 #define SCCNXP_MR_REG (0x00) 2986 # define MR0_BAUD_NORMAL (0 << 0) 2987 # define MR0_BAUD_EXT1 (1 << 0) 2988 # define MR0_BAUD_EXT2 (5 << 0) 2989 # define MR0_FIFO (1 << 3) 2990 # define MR0_TXLVL (1 << 4) 2991 # define MR1_BITS_5 (0 << 0) 2992 # define MR1_BITS_6 (1 << 0) 2993 # define MR1_BITS_7 (2 << 0) 2994 # define MR1_BITS_8 (3 << 0) 2995 # define MR1_PAR_EVN (0 << 2) 2996 # define MR1_PAR_ODD (1 << 2) 2997 # define MR1_PAR_NO (4 << 2) 2998 # define MR2_STOP1 (7 << 0) 2999 # define MR2_STOP2 (0xf << 0) 3000 #define SCCNXP_SR_REG (0x01) 3001 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3002 # define SR_RXRDY (1 << 0) 3003 # define SR_FULL (1 << 1) 3004 # define SR_TXRDY (1 << 2) 3005 # define SR_TXEMT (1 << 3) 3006 # define SR_OVR (1 << 4) 3007 # define SR_PE (1 << 5) 3008 # define SR_FE (1 << 6) 3009 # define SR_BRK (1 << 7) 3010 #define SCCNXP_CR_REG (0x02) 3011 # define CR_RX_ENABLE (1 << 0) 3012 # define CR_RX_DISABLE (1 << 1) 3013 # define CR_TX_ENABLE (1 << 2) 3014 # define CR_TX_DISABLE (1 << 3) 3015 # define CR_CMD_MRPTR1 (0x01 << 4) 3016 # define CR_CMD_RX_RESET (0x02 << 4) 3017 # define CR_CMD_TX_RESET (0x03 << 4) 3018 # define CR_CMD_STATUS_RESET (0x04 << 4) 3019 # define CR_CMD_BREAK_RESET (0x05 << 4) 3020 # define CR_CMD_START_BREAK (0x06 << 4) 3021 # define CR_CMD_STOP_BREAK (0x07 << 4) 3022 # define CR_CMD_MRPTR0 (0x0b << 4) 3023 #define SCCNXP_RHR_REG (0x03) 3024 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3025 #define SCCNXP_IPCR_REG (0x04) 3026 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3027 # define ACR_BAUD0 (0 << 7) 3028 # define ACR_BAUD1 (1 << 7) 3029 # define ACR_TIMER_MODE (6 << 4) 3030 #define SCCNXP_ISR_REG (0x05) 3031 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3032 # define IMR_TXRDY (1 << 0) 3033 # define IMR_RXRDY (1 << 1) 3034 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3035 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3036 #define SCCNXP_IPR_REG (0x0d) 3037 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3038 #define SCCNXP_SOP_REG (0x0e) 3039 #define SCCNXP_ROP_REG (0x0f) 3040 #define MCTRL_MASK(sig) (0xf << (sig)) 3041 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3042 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3043 #define SCCNXP_HAVE_IO 0x00000001 3044 #define SCCNXP_HAVE_MR0 0x00000002 3045 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3046 #endif 3047 /* LDV_COMMENT_END_PREP */ 3048 /* LDV_COMMENT_FUNCTION_CALL Function from field "stop_rx" from driver structure with callbacks "sccnxp_ops" */ 3049 ldv_handler_precall(); 3050 sccnxp_stop_rx( var_group1); 3051 /* LDV_COMMENT_BEGIN_PREP */ 3052 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3053 #endif 3054 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3055 #endif 3056 /* LDV_COMMENT_END_PREP */ 3057 3058 3059 3060 3061 } 3062 3063 break; 3064 case 6: { 3065 3066 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3067 3068 3069 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/ 3070 /* LDV_COMMENT_BEGIN_PREP */ 3071 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3072 #define SUPPORT_SYSRQ 3073 #endif 3074 #define SCCNXP_NAME "uart-sccnxp" 3075 #define SCCNXP_MAJOR 204 3076 #define SCCNXP_MINOR 205 3077 #define SCCNXP_MR_REG (0x00) 3078 # define MR0_BAUD_NORMAL (0 << 0) 3079 # define MR0_BAUD_EXT1 (1 << 0) 3080 # define MR0_BAUD_EXT2 (5 << 0) 3081 # define MR0_FIFO (1 << 3) 3082 # define MR0_TXLVL (1 << 4) 3083 # define MR1_BITS_5 (0 << 0) 3084 # define MR1_BITS_6 (1 << 0) 3085 # define MR1_BITS_7 (2 << 0) 3086 # define MR1_BITS_8 (3 << 0) 3087 # define MR1_PAR_EVN (0 << 2) 3088 # define MR1_PAR_ODD (1 << 2) 3089 # define MR1_PAR_NO (4 << 2) 3090 # define MR2_STOP1 (7 << 0) 3091 # define MR2_STOP2 (0xf << 0) 3092 #define SCCNXP_SR_REG (0x01) 3093 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3094 # define SR_RXRDY (1 << 0) 3095 # define SR_FULL (1 << 1) 3096 # define SR_TXRDY (1 << 2) 3097 # define SR_TXEMT (1 << 3) 3098 # define SR_OVR (1 << 4) 3099 # define SR_PE (1 << 5) 3100 # define SR_FE (1 << 6) 3101 # define SR_BRK (1 << 7) 3102 #define SCCNXP_CR_REG (0x02) 3103 # define CR_RX_ENABLE (1 << 0) 3104 # define CR_RX_DISABLE (1 << 1) 3105 # define CR_TX_ENABLE (1 << 2) 3106 # define CR_TX_DISABLE (1 << 3) 3107 # define CR_CMD_MRPTR1 (0x01 << 4) 3108 # define CR_CMD_RX_RESET (0x02 << 4) 3109 # define CR_CMD_TX_RESET (0x03 << 4) 3110 # define CR_CMD_STATUS_RESET (0x04 << 4) 3111 # define CR_CMD_BREAK_RESET (0x05 << 4) 3112 # define CR_CMD_START_BREAK (0x06 << 4) 3113 # define CR_CMD_STOP_BREAK (0x07 << 4) 3114 # define CR_CMD_MRPTR0 (0x0b << 4) 3115 #define SCCNXP_RHR_REG (0x03) 3116 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3117 #define SCCNXP_IPCR_REG (0x04) 3118 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3119 # define ACR_BAUD0 (0 << 7) 3120 # define ACR_BAUD1 (1 << 7) 3121 # define ACR_TIMER_MODE (6 << 4) 3122 #define SCCNXP_ISR_REG (0x05) 3123 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3124 # define IMR_TXRDY (1 << 0) 3125 # define IMR_RXRDY (1 << 1) 3126 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3127 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3128 #define SCCNXP_IPR_REG (0x0d) 3129 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3130 #define SCCNXP_SOP_REG (0x0e) 3131 #define SCCNXP_ROP_REG (0x0f) 3132 #define MCTRL_MASK(sig) (0xf << (sig)) 3133 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3134 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3135 #define SCCNXP_HAVE_IO 0x00000001 3136 #define SCCNXP_HAVE_MR0 0x00000002 3137 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3138 #endif 3139 /* LDV_COMMENT_END_PREP */ 3140 /* LDV_COMMENT_FUNCTION_CALL Function from field "break_ctl" from driver structure with callbacks "sccnxp_ops" */ 3141 ldv_handler_precall(); 3142 sccnxp_break_ctl( var_group1, var_sccnxp_break_ctl_20_p1); 3143 /* LDV_COMMENT_BEGIN_PREP */ 3144 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3145 #endif 3146 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3147 #endif 3148 /* LDV_COMMENT_END_PREP */ 3149 3150 3151 3152 3153 } 3154 3155 break; 3156 case 7: { 3157 3158 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3159 3160 3161 /* content: static int sccnxp_startup(struct uart_port *port)*/ 3162 /* LDV_COMMENT_BEGIN_PREP */ 3163 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3164 #define SUPPORT_SYSRQ 3165 #endif 3166 #define SCCNXP_NAME "uart-sccnxp" 3167 #define SCCNXP_MAJOR 204 3168 #define SCCNXP_MINOR 205 3169 #define SCCNXP_MR_REG (0x00) 3170 # define MR0_BAUD_NORMAL (0 << 0) 3171 # define MR0_BAUD_EXT1 (1 << 0) 3172 # define MR0_BAUD_EXT2 (5 << 0) 3173 # define MR0_FIFO (1 << 3) 3174 # define MR0_TXLVL (1 << 4) 3175 # define MR1_BITS_5 (0 << 0) 3176 # define MR1_BITS_6 (1 << 0) 3177 # define MR1_BITS_7 (2 << 0) 3178 # define MR1_BITS_8 (3 << 0) 3179 # define MR1_PAR_EVN (0 << 2) 3180 # define MR1_PAR_ODD (1 << 2) 3181 # define MR1_PAR_NO (4 << 2) 3182 # define MR2_STOP1 (7 << 0) 3183 # define MR2_STOP2 (0xf << 0) 3184 #define SCCNXP_SR_REG (0x01) 3185 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3186 # define SR_RXRDY (1 << 0) 3187 # define SR_FULL (1 << 1) 3188 # define SR_TXRDY (1 << 2) 3189 # define SR_TXEMT (1 << 3) 3190 # define SR_OVR (1 << 4) 3191 # define SR_PE (1 << 5) 3192 # define SR_FE (1 << 6) 3193 # define SR_BRK (1 << 7) 3194 #define SCCNXP_CR_REG (0x02) 3195 # define CR_RX_ENABLE (1 << 0) 3196 # define CR_RX_DISABLE (1 << 1) 3197 # define CR_TX_ENABLE (1 << 2) 3198 # define CR_TX_DISABLE (1 << 3) 3199 # define CR_CMD_MRPTR1 (0x01 << 4) 3200 # define CR_CMD_RX_RESET (0x02 << 4) 3201 # define CR_CMD_TX_RESET (0x03 << 4) 3202 # define CR_CMD_STATUS_RESET (0x04 << 4) 3203 # define CR_CMD_BREAK_RESET (0x05 << 4) 3204 # define CR_CMD_START_BREAK (0x06 << 4) 3205 # define CR_CMD_STOP_BREAK (0x07 << 4) 3206 # define CR_CMD_MRPTR0 (0x0b << 4) 3207 #define SCCNXP_RHR_REG (0x03) 3208 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3209 #define SCCNXP_IPCR_REG (0x04) 3210 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3211 # define ACR_BAUD0 (0 << 7) 3212 # define ACR_BAUD1 (1 << 7) 3213 # define ACR_TIMER_MODE (6 << 4) 3214 #define SCCNXP_ISR_REG (0x05) 3215 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3216 # define IMR_TXRDY (1 << 0) 3217 # define IMR_RXRDY (1 << 1) 3218 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3219 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3220 #define SCCNXP_IPR_REG (0x0d) 3221 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3222 #define SCCNXP_SOP_REG (0x0e) 3223 #define SCCNXP_ROP_REG (0x0f) 3224 #define MCTRL_MASK(sig) (0xf << (sig)) 3225 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3226 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3227 #define SCCNXP_HAVE_IO 0x00000001 3228 #define SCCNXP_HAVE_MR0 0x00000002 3229 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3230 #endif 3231 /* LDV_COMMENT_END_PREP */ 3232 /* LDV_COMMENT_FUNCTION_CALL Function from field "startup" from driver structure with callbacks "sccnxp_ops" */ 3233 ldv_handler_precall(); 3234 sccnxp_startup( var_group1); 3235 /* LDV_COMMENT_BEGIN_PREP */ 3236 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3237 #endif 3238 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3239 #endif 3240 /* LDV_COMMENT_END_PREP */ 3241 3242 3243 3244 3245 } 3246 3247 break; 3248 case 8: { 3249 3250 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3251 3252 3253 /* content: static void sccnxp_shutdown(struct uart_port *port)*/ 3254 /* LDV_COMMENT_BEGIN_PREP */ 3255 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3256 #define SUPPORT_SYSRQ 3257 #endif 3258 #define SCCNXP_NAME "uart-sccnxp" 3259 #define SCCNXP_MAJOR 204 3260 #define SCCNXP_MINOR 205 3261 #define SCCNXP_MR_REG (0x00) 3262 # define MR0_BAUD_NORMAL (0 << 0) 3263 # define MR0_BAUD_EXT1 (1 << 0) 3264 # define MR0_BAUD_EXT2 (5 << 0) 3265 # define MR0_FIFO (1 << 3) 3266 # define MR0_TXLVL (1 << 4) 3267 # define MR1_BITS_5 (0 << 0) 3268 # define MR1_BITS_6 (1 << 0) 3269 # define MR1_BITS_7 (2 << 0) 3270 # define MR1_BITS_8 (3 << 0) 3271 # define MR1_PAR_EVN (0 << 2) 3272 # define MR1_PAR_ODD (1 << 2) 3273 # define MR1_PAR_NO (4 << 2) 3274 # define MR2_STOP1 (7 << 0) 3275 # define MR2_STOP2 (0xf << 0) 3276 #define SCCNXP_SR_REG (0x01) 3277 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3278 # define SR_RXRDY (1 << 0) 3279 # define SR_FULL (1 << 1) 3280 # define SR_TXRDY (1 << 2) 3281 # define SR_TXEMT (1 << 3) 3282 # define SR_OVR (1 << 4) 3283 # define SR_PE (1 << 5) 3284 # define SR_FE (1 << 6) 3285 # define SR_BRK (1 << 7) 3286 #define SCCNXP_CR_REG (0x02) 3287 # define CR_RX_ENABLE (1 << 0) 3288 # define CR_RX_DISABLE (1 << 1) 3289 # define CR_TX_ENABLE (1 << 2) 3290 # define CR_TX_DISABLE (1 << 3) 3291 # define CR_CMD_MRPTR1 (0x01 << 4) 3292 # define CR_CMD_RX_RESET (0x02 << 4) 3293 # define CR_CMD_TX_RESET (0x03 << 4) 3294 # define CR_CMD_STATUS_RESET (0x04 << 4) 3295 # define CR_CMD_BREAK_RESET (0x05 << 4) 3296 # define CR_CMD_START_BREAK (0x06 << 4) 3297 # define CR_CMD_STOP_BREAK (0x07 << 4) 3298 # define CR_CMD_MRPTR0 (0x0b << 4) 3299 #define SCCNXP_RHR_REG (0x03) 3300 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3301 #define SCCNXP_IPCR_REG (0x04) 3302 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3303 # define ACR_BAUD0 (0 << 7) 3304 # define ACR_BAUD1 (1 << 7) 3305 # define ACR_TIMER_MODE (6 << 4) 3306 #define SCCNXP_ISR_REG (0x05) 3307 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3308 # define IMR_TXRDY (1 << 0) 3309 # define IMR_RXRDY (1 << 1) 3310 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3311 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3312 #define SCCNXP_IPR_REG (0x0d) 3313 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3314 #define SCCNXP_SOP_REG (0x0e) 3315 #define SCCNXP_ROP_REG (0x0f) 3316 #define MCTRL_MASK(sig) (0xf << (sig)) 3317 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3318 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3319 #define SCCNXP_HAVE_IO 0x00000001 3320 #define SCCNXP_HAVE_MR0 0x00000002 3321 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3322 #endif 3323 /* LDV_COMMENT_END_PREP */ 3324 /* LDV_COMMENT_FUNCTION_CALL Function from field "shutdown" from driver structure with callbacks "sccnxp_ops" */ 3325 ldv_handler_precall(); 3326 sccnxp_shutdown( var_group1); 3327 /* LDV_COMMENT_BEGIN_PREP */ 3328 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3329 #endif 3330 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3331 #endif 3332 /* LDV_COMMENT_END_PREP */ 3333 3334 3335 3336 3337 } 3338 3339 break; 3340 case 9: { 3341 3342 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3343 3344 3345 /* content: static void sccnxp_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old)*/ 3346 /* LDV_COMMENT_BEGIN_PREP */ 3347 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3348 #define SUPPORT_SYSRQ 3349 #endif 3350 #define SCCNXP_NAME "uart-sccnxp" 3351 #define SCCNXP_MAJOR 204 3352 #define SCCNXP_MINOR 205 3353 #define SCCNXP_MR_REG (0x00) 3354 # define MR0_BAUD_NORMAL (0 << 0) 3355 # define MR0_BAUD_EXT1 (1 << 0) 3356 # define MR0_BAUD_EXT2 (5 << 0) 3357 # define MR0_FIFO (1 << 3) 3358 # define MR0_TXLVL (1 << 4) 3359 # define MR1_BITS_5 (0 << 0) 3360 # define MR1_BITS_6 (1 << 0) 3361 # define MR1_BITS_7 (2 << 0) 3362 # define MR1_BITS_8 (3 << 0) 3363 # define MR1_PAR_EVN (0 << 2) 3364 # define MR1_PAR_ODD (1 << 2) 3365 # define MR1_PAR_NO (4 << 2) 3366 # define MR2_STOP1 (7 << 0) 3367 # define MR2_STOP2 (0xf << 0) 3368 #define SCCNXP_SR_REG (0x01) 3369 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3370 # define SR_RXRDY (1 << 0) 3371 # define SR_FULL (1 << 1) 3372 # define SR_TXRDY (1 << 2) 3373 # define SR_TXEMT (1 << 3) 3374 # define SR_OVR (1 << 4) 3375 # define SR_PE (1 << 5) 3376 # define SR_FE (1 << 6) 3377 # define SR_BRK (1 << 7) 3378 #define SCCNXP_CR_REG (0x02) 3379 # define CR_RX_ENABLE (1 << 0) 3380 # define CR_RX_DISABLE (1 << 1) 3381 # define CR_TX_ENABLE (1 << 2) 3382 # define CR_TX_DISABLE (1 << 3) 3383 # define CR_CMD_MRPTR1 (0x01 << 4) 3384 # define CR_CMD_RX_RESET (0x02 << 4) 3385 # define CR_CMD_TX_RESET (0x03 << 4) 3386 # define CR_CMD_STATUS_RESET (0x04 << 4) 3387 # define CR_CMD_BREAK_RESET (0x05 << 4) 3388 # define CR_CMD_START_BREAK (0x06 << 4) 3389 # define CR_CMD_STOP_BREAK (0x07 << 4) 3390 # define CR_CMD_MRPTR0 (0x0b << 4) 3391 #define SCCNXP_RHR_REG (0x03) 3392 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3393 #define SCCNXP_IPCR_REG (0x04) 3394 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3395 # define ACR_BAUD0 (0 << 7) 3396 # define ACR_BAUD1 (1 << 7) 3397 # define ACR_TIMER_MODE (6 << 4) 3398 #define SCCNXP_ISR_REG (0x05) 3399 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3400 # define IMR_TXRDY (1 << 0) 3401 # define IMR_RXRDY (1 << 1) 3402 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3403 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3404 #define SCCNXP_IPR_REG (0x0d) 3405 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3406 #define SCCNXP_SOP_REG (0x0e) 3407 #define SCCNXP_ROP_REG (0x0f) 3408 #define MCTRL_MASK(sig) (0xf << (sig)) 3409 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3410 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3411 #define SCCNXP_HAVE_IO 0x00000001 3412 #define SCCNXP_HAVE_MR0 0x00000002 3413 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3414 #endif 3415 /* LDV_COMMENT_END_PREP */ 3416 /* LDV_COMMENT_FUNCTION_CALL Function from field "set_termios" from driver structure with callbacks "sccnxp_ops" */ 3417 ldv_handler_precall(); 3418 sccnxp_set_termios( var_group1, var_group2, var_sccnxp_set_termios_21_p2); 3419 /* LDV_COMMENT_BEGIN_PREP */ 3420 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3421 #endif 3422 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3423 #endif 3424 /* LDV_COMMENT_END_PREP */ 3425 3426 3427 3428 3429 } 3430 3431 break; 3432 case 10: { 3433 3434 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3435 3436 3437 /* content: static const char *sccnxp_type(struct uart_port *port)*/ 3438 /* LDV_COMMENT_BEGIN_PREP */ 3439 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3440 #define SUPPORT_SYSRQ 3441 #endif 3442 #define SCCNXP_NAME "uart-sccnxp" 3443 #define SCCNXP_MAJOR 204 3444 #define SCCNXP_MINOR 205 3445 #define SCCNXP_MR_REG (0x00) 3446 # define MR0_BAUD_NORMAL (0 << 0) 3447 # define MR0_BAUD_EXT1 (1 << 0) 3448 # define MR0_BAUD_EXT2 (5 << 0) 3449 # define MR0_FIFO (1 << 3) 3450 # define MR0_TXLVL (1 << 4) 3451 # define MR1_BITS_5 (0 << 0) 3452 # define MR1_BITS_6 (1 << 0) 3453 # define MR1_BITS_7 (2 << 0) 3454 # define MR1_BITS_8 (3 << 0) 3455 # define MR1_PAR_EVN (0 << 2) 3456 # define MR1_PAR_ODD (1 << 2) 3457 # define MR1_PAR_NO (4 << 2) 3458 # define MR2_STOP1 (7 << 0) 3459 # define MR2_STOP2 (0xf << 0) 3460 #define SCCNXP_SR_REG (0x01) 3461 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3462 # define SR_RXRDY (1 << 0) 3463 # define SR_FULL (1 << 1) 3464 # define SR_TXRDY (1 << 2) 3465 # define SR_TXEMT (1 << 3) 3466 # define SR_OVR (1 << 4) 3467 # define SR_PE (1 << 5) 3468 # define SR_FE (1 << 6) 3469 # define SR_BRK (1 << 7) 3470 #define SCCNXP_CR_REG (0x02) 3471 # define CR_RX_ENABLE (1 << 0) 3472 # define CR_RX_DISABLE (1 << 1) 3473 # define CR_TX_ENABLE (1 << 2) 3474 # define CR_TX_DISABLE (1 << 3) 3475 # define CR_CMD_MRPTR1 (0x01 << 4) 3476 # define CR_CMD_RX_RESET (0x02 << 4) 3477 # define CR_CMD_TX_RESET (0x03 << 4) 3478 # define CR_CMD_STATUS_RESET (0x04 << 4) 3479 # define CR_CMD_BREAK_RESET (0x05 << 4) 3480 # define CR_CMD_START_BREAK (0x06 << 4) 3481 # define CR_CMD_STOP_BREAK (0x07 << 4) 3482 # define CR_CMD_MRPTR0 (0x0b << 4) 3483 #define SCCNXP_RHR_REG (0x03) 3484 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3485 #define SCCNXP_IPCR_REG (0x04) 3486 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3487 # define ACR_BAUD0 (0 << 7) 3488 # define ACR_BAUD1 (1 << 7) 3489 # define ACR_TIMER_MODE (6 << 4) 3490 #define SCCNXP_ISR_REG (0x05) 3491 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3492 # define IMR_TXRDY (1 << 0) 3493 # define IMR_RXRDY (1 << 1) 3494 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3495 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3496 #define SCCNXP_IPR_REG (0x0d) 3497 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3498 #define SCCNXP_SOP_REG (0x0e) 3499 #define SCCNXP_ROP_REG (0x0f) 3500 #define MCTRL_MASK(sig) (0xf << (sig)) 3501 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3502 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3503 #define SCCNXP_HAVE_IO 0x00000001 3504 #define SCCNXP_HAVE_MR0 0x00000002 3505 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3506 #endif 3507 /* LDV_COMMENT_END_PREP */ 3508 /* LDV_COMMENT_FUNCTION_CALL Function from field "type" from driver structure with callbacks "sccnxp_ops" */ 3509 ldv_handler_precall(); 3510 sccnxp_type( var_group1); 3511 /* LDV_COMMENT_BEGIN_PREP */ 3512 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3513 #endif 3514 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3515 #endif 3516 /* LDV_COMMENT_END_PREP */ 3517 3518 3519 3520 3521 } 3522 3523 break; 3524 case 11: { 3525 3526 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3527 3528 3529 /* content: static void sccnxp_release_port(struct uart_port *port)*/ 3530 /* LDV_COMMENT_BEGIN_PREP */ 3531 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3532 #define SUPPORT_SYSRQ 3533 #endif 3534 #define SCCNXP_NAME "uart-sccnxp" 3535 #define SCCNXP_MAJOR 204 3536 #define SCCNXP_MINOR 205 3537 #define SCCNXP_MR_REG (0x00) 3538 # define MR0_BAUD_NORMAL (0 << 0) 3539 # define MR0_BAUD_EXT1 (1 << 0) 3540 # define MR0_BAUD_EXT2 (5 << 0) 3541 # define MR0_FIFO (1 << 3) 3542 # define MR0_TXLVL (1 << 4) 3543 # define MR1_BITS_5 (0 << 0) 3544 # define MR1_BITS_6 (1 << 0) 3545 # define MR1_BITS_7 (2 << 0) 3546 # define MR1_BITS_8 (3 << 0) 3547 # define MR1_PAR_EVN (0 << 2) 3548 # define MR1_PAR_ODD (1 << 2) 3549 # define MR1_PAR_NO (4 << 2) 3550 # define MR2_STOP1 (7 << 0) 3551 # define MR2_STOP2 (0xf << 0) 3552 #define SCCNXP_SR_REG (0x01) 3553 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3554 # define SR_RXRDY (1 << 0) 3555 # define SR_FULL (1 << 1) 3556 # define SR_TXRDY (1 << 2) 3557 # define SR_TXEMT (1 << 3) 3558 # define SR_OVR (1 << 4) 3559 # define SR_PE (1 << 5) 3560 # define SR_FE (1 << 6) 3561 # define SR_BRK (1 << 7) 3562 #define SCCNXP_CR_REG (0x02) 3563 # define CR_RX_ENABLE (1 << 0) 3564 # define CR_RX_DISABLE (1 << 1) 3565 # define CR_TX_ENABLE (1 << 2) 3566 # define CR_TX_DISABLE (1 << 3) 3567 # define CR_CMD_MRPTR1 (0x01 << 4) 3568 # define CR_CMD_RX_RESET (0x02 << 4) 3569 # define CR_CMD_TX_RESET (0x03 << 4) 3570 # define CR_CMD_STATUS_RESET (0x04 << 4) 3571 # define CR_CMD_BREAK_RESET (0x05 << 4) 3572 # define CR_CMD_START_BREAK (0x06 << 4) 3573 # define CR_CMD_STOP_BREAK (0x07 << 4) 3574 # define CR_CMD_MRPTR0 (0x0b << 4) 3575 #define SCCNXP_RHR_REG (0x03) 3576 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3577 #define SCCNXP_IPCR_REG (0x04) 3578 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3579 # define ACR_BAUD0 (0 << 7) 3580 # define ACR_BAUD1 (1 << 7) 3581 # define ACR_TIMER_MODE (6 << 4) 3582 #define SCCNXP_ISR_REG (0x05) 3583 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3584 # define IMR_TXRDY (1 << 0) 3585 # define IMR_RXRDY (1 << 1) 3586 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3587 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3588 #define SCCNXP_IPR_REG (0x0d) 3589 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3590 #define SCCNXP_SOP_REG (0x0e) 3591 #define SCCNXP_ROP_REG (0x0f) 3592 #define MCTRL_MASK(sig) (0xf << (sig)) 3593 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3594 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3595 #define SCCNXP_HAVE_IO 0x00000001 3596 #define SCCNXP_HAVE_MR0 0x00000002 3597 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3598 #endif 3599 /* LDV_COMMENT_END_PREP */ 3600 /* LDV_COMMENT_FUNCTION_CALL Function from field "release_port" from driver structure with callbacks "sccnxp_ops" */ 3601 ldv_handler_precall(); 3602 sccnxp_release_port( var_group1); 3603 /* LDV_COMMENT_BEGIN_PREP */ 3604 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3605 #endif 3606 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3607 #endif 3608 /* LDV_COMMENT_END_PREP */ 3609 3610 3611 3612 3613 } 3614 3615 break; 3616 case 12: { 3617 3618 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3619 3620 3621 /* content: static int sccnxp_request_port(struct uart_port *port)*/ 3622 /* LDV_COMMENT_BEGIN_PREP */ 3623 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3624 #define SUPPORT_SYSRQ 3625 #endif 3626 #define SCCNXP_NAME "uart-sccnxp" 3627 #define SCCNXP_MAJOR 204 3628 #define SCCNXP_MINOR 205 3629 #define SCCNXP_MR_REG (0x00) 3630 # define MR0_BAUD_NORMAL (0 << 0) 3631 # define MR0_BAUD_EXT1 (1 << 0) 3632 # define MR0_BAUD_EXT2 (5 << 0) 3633 # define MR0_FIFO (1 << 3) 3634 # define MR0_TXLVL (1 << 4) 3635 # define MR1_BITS_5 (0 << 0) 3636 # define MR1_BITS_6 (1 << 0) 3637 # define MR1_BITS_7 (2 << 0) 3638 # define MR1_BITS_8 (3 << 0) 3639 # define MR1_PAR_EVN (0 << 2) 3640 # define MR1_PAR_ODD (1 << 2) 3641 # define MR1_PAR_NO (4 << 2) 3642 # define MR2_STOP1 (7 << 0) 3643 # define MR2_STOP2 (0xf << 0) 3644 #define SCCNXP_SR_REG (0x01) 3645 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3646 # define SR_RXRDY (1 << 0) 3647 # define SR_FULL (1 << 1) 3648 # define SR_TXRDY (1 << 2) 3649 # define SR_TXEMT (1 << 3) 3650 # define SR_OVR (1 << 4) 3651 # define SR_PE (1 << 5) 3652 # define SR_FE (1 << 6) 3653 # define SR_BRK (1 << 7) 3654 #define SCCNXP_CR_REG (0x02) 3655 # define CR_RX_ENABLE (1 << 0) 3656 # define CR_RX_DISABLE (1 << 1) 3657 # define CR_TX_ENABLE (1 << 2) 3658 # define CR_TX_DISABLE (1 << 3) 3659 # define CR_CMD_MRPTR1 (0x01 << 4) 3660 # define CR_CMD_RX_RESET (0x02 << 4) 3661 # define CR_CMD_TX_RESET (0x03 << 4) 3662 # define CR_CMD_STATUS_RESET (0x04 << 4) 3663 # define CR_CMD_BREAK_RESET (0x05 << 4) 3664 # define CR_CMD_START_BREAK (0x06 << 4) 3665 # define CR_CMD_STOP_BREAK (0x07 << 4) 3666 # define CR_CMD_MRPTR0 (0x0b << 4) 3667 #define SCCNXP_RHR_REG (0x03) 3668 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3669 #define SCCNXP_IPCR_REG (0x04) 3670 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3671 # define ACR_BAUD0 (0 << 7) 3672 # define ACR_BAUD1 (1 << 7) 3673 # define ACR_TIMER_MODE (6 << 4) 3674 #define SCCNXP_ISR_REG (0x05) 3675 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3676 # define IMR_TXRDY (1 << 0) 3677 # define IMR_RXRDY (1 << 1) 3678 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3679 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3680 #define SCCNXP_IPR_REG (0x0d) 3681 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3682 #define SCCNXP_SOP_REG (0x0e) 3683 #define SCCNXP_ROP_REG (0x0f) 3684 #define MCTRL_MASK(sig) (0xf << (sig)) 3685 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3686 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3687 #define SCCNXP_HAVE_IO 0x00000001 3688 #define SCCNXP_HAVE_MR0 0x00000002 3689 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3690 #endif 3691 /* LDV_COMMENT_END_PREP */ 3692 /* LDV_COMMENT_FUNCTION_CALL Function from field "request_port" from driver structure with callbacks "sccnxp_ops" */ 3693 ldv_handler_precall(); 3694 sccnxp_request_port( var_group1); 3695 /* LDV_COMMENT_BEGIN_PREP */ 3696 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3697 #endif 3698 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3699 #endif 3700 /* LDV_COMMENT_END_PREP */ 3701 3702 3703 3704 3705 } 3706 3707 break; 3708 case 13: { 3709 3710 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3711 3712 3713 /* content: static void sccnxp_config_port(struct uart_port *port, int flags)*/ 3714 /* LDV_COMMENT_BEGIN_PREP */ 3715 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3716 #define SUPPORT_SYSRQ 3717 #endif 3718 #define SCCNXP_NAME "uart-sccnxp" 3719 #define SCCNXP_MAJOR 204 3720 #define SCCNXP_MINOR 205 3721 #define SCCNXP_MR_REG (0x00) 3722 # define MR0_BAUD_NORMAL (0 << 0) 3723 # define MR0_BAUD_EXT1 (1 << 0) 3724 # define MR0_BAUD_EXT2 (5 << 0) 3725 # define MR0_FIFO (1 << 3) 3726 # define MR0_TXLVL (1 << 4) 3727 # define MR1_BITS_5 (0 << 0) 3728 # define MR1_BITS_6 (1 << 0) 3729 # define MR1_BITS_7 (2 << 0) 3730 # define MR1_BITS_8 (3 << 0) 3731 # define MR1_PAR_EVN (0 << 2) 3732 # define MR1_PAR_ODD (1 << 2) 3733 # define MR1_PAR_NO (4 << 2) 3734 # define MR2_STOP1 (7 << 0) 3735 # define MR2_STOP2 (0xf << 0) 3736 #define SCCNXP_SR_REG (0x01) 3737 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3738 # define SR_RXRDY (1 << 0) 3739 # define SR_FULL (1 << 1) 3740 # define SR_TXRDY (1 << 2) 3741 # define SR_TXEMT (1 << 3) 3742 # define SR_OVR (1 << 4) 3743 # define SR_PE (1 << 5) 3744 # define SR_FE (1 << 6) 3745 # define SR_BRK (1 << 7) 3746 #define SCCNXP_CR_REG (0x02) 3747 # define CR_RX_ENABLE (1 << 0) 3748 # define CR_RX_DISABLE (1 << 1) 3749 # define CR_TX_ENABLE (1 << 2) 3750 # define CR_TX_DISABLE (1 << 3) 3751 # define CR_CMD_MRPTR1 (0x01 << 4) 3752 # define CR_CMD_RX_RESET (0x02 << 4) 3753 # define CR_CMD_TX_RESET (0x03 << 4) 3754 # define CR_CMD_STATUS_RESET (0x04 << 4) 3755 # define CR_CMD_BREAK_RESET (0x05 << 4) 3756 # define CR_CMD_START_BREAK (0x06 << 4) 3757 # define CR_CMD_STOP_BREAK (0x07 << 4) 3758 # define CR_CMD_MRPTR0 (0x0b << 4) 3759 #define SCCNXP_RHR_REG (0x03) 3760 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3761 #define SCCNXP_IPCR_REG (0x04) 3762 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3763 # define ACR_BAUD0 (0 << 7) 3764 # define ACR_BAUD1 (1 << 7) 3765 # define ACR_TIMER_MODE (6 << 4) 3766 #define SCCNXP_ISR_REG (0x05) 3767 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3768 # define IMR_TXRDY (1 << 0) 3769 # define IMR_RXRDY (1 << 1) 3770 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3771 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3772 #define SCCNXP_IPR_REG (0x0d) 3773 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3774 #define SCCNXP_SOP_REG (0x0e) 3775 #define SCCNXP_ROP_REG (0x0f) 3776 #define MCTRL_MASK(sig) (0xf << (sig)) 3777 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3778 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3779 #define SCCNXP_HAVE_IO 0x00000001 3780 #define SCCNXP_HAVE_MR0 0x00000002 3781 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3782 #endif 3783 /* LDV_COMMENT_END_PREP */ 3784 /* LDV_COMMENT_FUNCTION_CALL Function from field "config_port" from driver structure with callbacks "sccnxp_ops" */ 3785 ldv_handler_precall(); 3786 sccnxp_config_port( var_group1, var_sccnxp_config_port_27_p1); 3787 /* LDV_COMMENT_BEGIN_PREP */ 3788 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3789 #endif 3790 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3791 #endif 3792 /* LDV_COMMENT_END_PREP */ 3793 3794 3795 3796 3797 } 3798 3799 break; 3800 case 14: { 3801 3802 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 3803 3804 3805 /* content: static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)*/ 3806 /* LDV_COMMENT_BEGIN_PREP */ 3807 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3808 #define SUPPORT_SYSRQ 3809 #endif 3810 #define SCCNXP_NAME "uart-sccnxp" 3811 #define SCCNXP_MAJOR 204 3812 #define SCCNXP_MINOR 205 3813 #define SCCNXP_MR_REG (0x00) 3814 # define MR0_BAUD_NORMAL (0 << 0) 3815 # define MR0_BAUD_EXT1 (1 << 0) 3816 # define MR0_BAUD_EXT2 (5 << 0) 3817 # define MR0_FIFO (1 << 3) 3818 # define MR0_TXLVL (1 << 4) 3819 # define MR1_BITS_5 (0 << 0) 3820 # define MR1_BITS_6 (1 << 0) 3821 # define MR1_BITS_7 (2 << 0) 3822 # define MR1_BITS_8 (3 << 0) 3823 # define MR1_PAR_EVN (0 << 2) 3824 # define MR1_PAR_ODD (1 << 2) 3825 # define MR1_PAR_NO (4 << 2) 3826 # define MR2_STOP1 (7 << 0) 3827 # define MR2_STOP2 (0xf << 0) 3828 #define SCCNXP_SR_REG (0x01) 3829 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3830 # define SR_RXRDY (1 << 0) 3831 # define SR_FULL (1 << 1) 3832 # define SR_TXRDY (1 << 2) 3833 # define SR_TXEMT (1 << 3) 3834 # define SR_OVR (1 << 4) 3835 # define SR_PE (1 << 5) 3836 # define SR_FE (1 << 6) 3837 # define SR_BRK (1 << 7) 3838 #define SCCNXP_CR_REG (0x02) 3839 # define CR_RX_ENABLE (1 << 0) 3840 # define CR_RX_DISABLE (1 << 1) 3841 # define CR_TX_ENABLE (1 << 2) 3842 # define CR_TX_DISABLE (1 << 3) 3843 # define CR_CMD_MRPTR1 (0x01 << 4) 3844 # define CR_CMD_RX_RESET (0x02 << 4) 3845 # define CR_CMD_TX_RESET (0x03 << 4) 3846 # define CR_CMD_STATUS_RESET (0x04 << 4) 3847 # define CR_CMD_BREAK_RESET (0x05 << 4) 3848 # define CR_CMD_START_BREAK (0x06 << 4) 3849 # define CR_CMD_STOP_BREAK (0x07 << 4) 3850 # define CR_CMD_MRPTR0 (0x0b << 4) 3851 #define SCCNXP_RHR_REG (0x03) 3852 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3853 #define SCCNXP_IPCR_REG (0x04) 3854 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3855 # define ACR_BAUD0 (0 << 7) 3856 # define ACR_BAUD1 (1 << 7) 3857 # define ACR_TIMER_MODE (6 << 4) 3858 #define SCCNXP_ISR_REG (0x05) 3859 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3860 # define IMR_TXRDY (1 << 0) 3861 # define IMR_RXRDY (1 << 1) 3862 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3863 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3864 #define SCCNXP_IPR_REG (0x0d) 3865 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3866 #define SCCNXP_SOP_REG (0x0e) 3867 #define SCCNXP_ROP_REG (0x0f) 3868 #define MCTRL_MASK(sig) (0xf << (sig)) 3869 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3870 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3871 #define SCCNXP_HAVE_IO 0x00000001 3872 #define SCCNXP_HAVE_MR0 0x00000002 3873 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3874 #endif 3875 /* LDV_COMMENT_END_PREP */ 3876 /* LDV_COMMENT_FUNCTION_CALL Function from field "verify_port" from driver structure with callbacks "sccnxp_ops" */ 3877 ldv_handler_precall(); 3878 sccnxp_verify_port( var_group1, var_group3); 3879 /* LDV_COMMENT_BEGIN_PREP */ 3880 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3881 #endif 3882 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3883 #endif 3884 /* LDV_COMMENT_END_PREP */ 3885 3886 3887 3888 3889 } 3890 3891 break; 3892 case 15: { 3893 3894 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/ 3895 if(ldv_s_sccnxp_uart_driver_platform_driver==0) { 3896 3897 /* content: static int sccnxp_probe(struct platform_device *pdev)*/ 3898 /* LDV_COMMENT_BEGIN_PREP */ 3899 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3900 #define SUPPORT_SYSRQ 3901 #endif 3902 #define SCCNXP_NAME "uart-sccnxp" 3903 #define SCCNXP_MAJOR 204 3904 #define SCCNXP_MINOR 205 3905 #define SCCNXP_MR_REG (0x00) 3906 # define MR0_BAUD_NORMAL (0 << 0) 3907 # define MR0_BAUD_EXT1 (1 << 0) 3908 # define MR0_BAUD_EXT2 (5 << 0) 3909 # define MR0_FIFO (1 << 3) 3910 # define MR0_TXLVL (1 << 4) 3911 # define MR1_BITS_5 (0 << 0) 3912 # define MR1_BITS_6 (1 << 0) 3913 # define MR1_BITS_7 (2 << 0) 3914 # define MR1_BITS_8 (3 << 0) 3915 # define MR1_PAR_EVN (0 << 2) 3916 # define MR1_PAR_ODD (1 << 2) 3917 # define MR1_PAR_NO (4 << 2) 3918 # define MR2_STOP1 (7 << 0) 3919 # define MR2_STOP2 (0xf << 0) 3920 #define SCCNXP_SR_REG (0x01) 3921 #define SCCNXP_CSR_REG SCCNXP_SR_REG 3922 # define SR_RXRDY (1 << 0) 3923 # define SR_FULL (1 << 1) 3924 # define SR_TXRDY (1 << 2) 3925 # define SR_TXEMT (1 << 3) 3926 # define SR_OVR (1 << 4) 3927 # define SR_PE (1 << 5) 3928 # define SR_FE (1 << 6) 3929 # define SR_BRK (1 << 7) 3930 #define SCCNXP_CR_REG (0x02) 3931 # define CR_RX_ENABLE (1 << 0) 3932 # define CR_RX_DISABLE (1 << 1) 3933 # define CR_TX_ENABLE (1 << 2) 3934 # define CR_TX_DISABLE (1 << 3) 3935 # define CR_CMD_MRPTR1 (0x01 << 4) 3936 # define CR_CMD_RX_RESET (0x02 << 4) 3937 # define CR_CMD_TX_RESET (0x03 << 4) 3938 # define CR_CMD_STATUS_RESET (0x04 << 4) 3939 # define CR_CMD_BREAK_RESET (0x05 << 4) 3940 # define CR_CMD_START_BREAK (0x06 << 4) 3941 # define CR_CMD_STOP_BREAK (0x07 << 4) 3942 # define CR_CMD_MRPTR0 (0x0b << 4) 3943 #define SCCNXP_RHR_REG (0x03) 3944 #define SCCNXP_THR_REG SCCNXP_RHR_REG 3945 #define SCCNXP_IPCR_REG (0x04) 3946 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 3947 # define ACR_BAUD0 (0 << 7) 3948 # define ACR_BAUD1 (1 << 7) 3949 # define ACR_TIMER_MODE (6 << 4) 3950 #define SCCNXP_ISR_REG (0x05) 3951 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 3952 # define IMR_TXRDY (1 << 0) 3953 # define IMR_RXRDY (1 << 1) 3954 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 3955 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 3956 #define SCCNXP_IPR_REG (0x0d) 3957 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 3958 #define SCCNXP_SOP_REG (0x0e) 3959 #define SCCNXP_ROP_REG (0x0f) 3960 #define MCTRL_MASK(sig) (0xf << (sig)) 3961 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 3962 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 3963 #define SCCNXP_HAVE_IO 0x00000001 3964 #define SCCNXP_HAVE_MR0 0x00000002 3965 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3966 #endif 3967 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 3968 #endif 3969 /* LDV_COMMENT_END_PREP */ 3970 /* LDV_COMMENT_FUNCTION_CALL Function from field "probe" from driver structure with callbacks "sccnxp_uart_driver". Standart function test for correct return result. */ 3971 res_sccnxp_probe_32 = sccnxp_probe( var_group4); 3972 ldv_check_return_value(res_sccnxp_probe_32); 3973 ldv_check_return_value_probe(res_sccnxp_probe_32); 3974 if(res_sccnxp_probe_32) 3975 goto ldv_module_exit; 3976 ldv_s_sccnxp_uart_driver_platform_driver++; 3977 3978 } 3979 3980 } 3981 3982 break; 3983 case 16: { 3984 3985 /** STRUCT: struct type: platform_driver, struct name: sccnxp_uart_driver **/ 3986 if(ldv_s_sccnxp_uart_driver_platform_driver==1) { 3987 3988 /* content: static int sccnxp_remove(struct platform_device *pdev)*/ 3989 /* LDV_COMMENT_BEGIN_PREP */ 3990 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 3991 #define SUPPORT_SYSRQ 3992 #endif 3993 #define SCCNXP_NAME "uart-sccnxp" 3994 #define SCCNXP_MAJOR 204 3995 #define SCCNXP_MINOR 205 3996 #define SCCNXP_MR_REG (0x00) 3997 # define MR0_BAUD_NORMAL (0 << 0) 3998 # define MR0_BAUD_EXT1 (1 << 0) 3999 # define MR0_BAUD_EXT2 (5 << 0) 4000 # define MR0_FIFO (1 << 3) 4001 # define MR0_TXLVL (1 << 4) 4002 # define MR1_BITS_5 (0 << 0) 4003 # define MR1_BITS_6 (1 << 0) 4004 # define MR1_BITS_7 (2 << 0) 4005 # define MR1_BITS_8 (3 << 0) 4006 # define MR1_PAR_EVN (0 << 2) 4007 # define MR1_PAR_ODD (1 << 2) 4008 # define MR1_PAR_NO (4 << 2) 4009 # define MR2_STOP1 (7 << 0) 4010 # define MR2_STOP2 (0xf << 0) 4011 #define SCCNXP_SR_REG (0x01) 4012 #define SCCNXP_CSR_REG SCCNXP_SR_REG 4013 # define SR_RXRDY (1 << 0) 4014 # define SR_FULL (1 << 1) 4015 # define SR_TXRDY (1 << 2) 4016 # define SR_TXEMT (1 << 3) 4017 # define SR_OVR (1 << 4) 4018 # define SR_PE (1 << 5) 4019 # define SR_FE (1 << 6) 4020 # define SR_BRK (1 << 7) 4021 #define SCCNXP_CR_REG (0x02) 4022 # define CR_RX_ENABLE (1 << 0) 4023 # define CR_RX_DISABLE (1 << 1) 4024 # define CR_TX_ENABLE (1 << 2) 4025 # define CR_TX_DISABLE (1 << 3) 4026 # define CR_CMD_MRPTR1 (0x01 << 4) 4027 # define CR_CMD_RX_RESET (0x02 << 4) 4028 # define CR_CMD_TX_RESET (0x03 << 4) 4029 # define CR_CMD_STATUS_RESET (0x04 << 4) 4030 # define CR_CMD_BREAK_RESET (0x05 << 4) 4031 # define CR_CMD_START_BREAK (0x06 << 4) 4032 # define CR_CMD_STOP_BREAK (0x07 << 4) 4033 # define CR_CMD_MRPTR0 (0x0b << 4) 4034 #define SCCNXP_RHR_REG (0x03) 4035 #define SCCNXP_THR_REG SCCNXP_RHR_REG 4036 #define SCCNXP_IPCR_REG (0x04) 4037 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 4038 # define ACR_BAUD0 (0 << 7) 4039 # define ACR_BAUD1 (1 << 7) 4040 # define ACR_TIMER_MODE (6 << 4) 4041 #define SCCNXP_ISR_REG (0x05) 4042 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 4043 # define IMR_TXRDY (1 << 0) 4044 # define IMR_RXRDY (1 << 1) 4045 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 4046 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 4047 #define SCCNXP_IPR_REG (0x0d) 4048 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 4049 #define SCCNXP_SOP_REG (0x0e) 4050 #define SCCNXP_ROP_REG (0x0f) 4051 #define MCTRL_MASK(sig) (0xf << (sig)) 4052 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 4053 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 4054 #define SCCNXP_HAVE_IO 0x00000001 4055 #define SCCNXP_HAVE_MR0 0x00000002 4056 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 4057 #endif 4058 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 4059 #endif 4060 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 4061 #endif 4062 /* LDV_COMMENT_END_PREP */ 4063 /* LDV_COMMENT_FUNCTION_CALL Function from field "remove" from driver structure with callbacks "sccnxp_uart_driver" */ 4064 ldv_handler_precall(); 4065 sccnxp_remove( var_group4); 4066 ldv_s_sccnxp_uart_driver_platform_driver=0; 4067 4068 } 4069 4070 } 4071 4072 break; 4073 case 17: { 4074 4075 /** CALLBACK SECTION request_irq **/ 4076 LDV_IN_INTERRUPT=2; 4077 4078 /* content: static irqreturn_t sccnxp_ist(int irq, void *dev_id)*/ 4079 /* LDV_COMMENT_BEGIN_PREP */ 4080 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 4081 #define SUPPORT_SYSRQ 4082 #endif 4083 #define SCCNXP_NAME "uart-sccnxp" 4084 #define SCCNXP_MAJOR 204 4085 #define SCCNXP_MINOR 205 4086 #define SCCNXP_MR_REG (0x00) 4087 # define MR0_BAUD_NORMAL (0 << 0) 4088 # define MR0_BAUD_EXT1 (1 << 0) 4089 # define MR0_BAUD_EXT2 (5 << 0) 4090 # define MR0_FIFO (1 << 3) 4091 # define MR0_TXLVL (1 << 4) 4092 # define MR1_BITS_5 (0 << 0) 4093 # define MR1_BITS_6 (1 << 0) 4094 # define MR1_BITS_7 (2 << 0) 4095 # define MR1_BITS_8 (3 << 0) 4096 # define MR1_PAR_EVN (0 << 2) 4097 # define MR1_PAR_ODD (1 << 2) 4098 # define MR1_PAR_NO (4 << 2) 4099 # define MR2_STOP1 (7 << 0) 4100 # define MR2_STOP2 (0xf << 0) 4101 #define SCCNXP_SR_REG (0x01) 4102 #define SCCNXP_CSR_REG SCCNXP_SR_REG 4103 # define SR_RXRDY (1 << 0) 4104 # define SR_FULL (1 << 1) 4105 # define SR_TXRDY (1 << 2) 4106 # define SR_TXEMT (1 << 3) 4107 # define SR_OVR (1 << 4) 4108 # define SR_PE (1 << 5) 4109 # define SR_FE (1 << 6) 4110 # define SR_BRK (1 << 7) 4111 #define SCCNXP_CR_REG (0x02) 4112 # define CR_RX_ENABLE (1 << 0) 4113 # define CR_RX_DISABLE (1 << 1) 4114 # define CR_TX_ENABLE (1 << 2) 4115 # define CR_TX_DISABLE (1 << 3) 4116 # define CR_CMD_MRPTR1 (0x01 << 4) 4117 # define CR_CMD_RX_RESET (0x02 << 4) 4118 # define CR_CMD_TX_RESET (0x03 << 4) 4119 # define CR_CMD_STATUS_RESET (0x04 << 4) 4120 # define CR_CMD_BREAK_RESET (0x05 << 4) 4121 # define CR_CMD_START_BREAK (0x06 << 4) 4122 # define CR_CMD_STOP_BREAK (0x07 << 4) 4123 # define CR_CMD_MRPTR0 (0x0b << 4) 4124 #define SCCNXP_RHR_REG (0x03) 4125 #define SCCNXP_THR_REG SCCNXP_RHR_REG 4126 #define SCCNXP_IPCR_REG (0x04) 4127 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 4128 # define ACR_BAUD0 (0 << 7) 4129 # define ACR_BAUD1 (1 << 7) 4130 # define ACR_TIMER_MODE (6 << 4) 4131 #define SCCNXP_ISR_REG (0x05) 4132 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 4133 # define IMR_TXRDY (1 << 0) 4134 # define IMR_RXRDY (1 << 1) 4135 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 4136 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 4137 #define SCCNXP_IPR_REG (0x0d) 4138 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 4139 #define SCCNXP_SOP_REG (0x0e) 4140 #define SCCNXP_ROP_REG (0x0f) 4141 #define MCTRL_MASK(sig) (0xf << (sig)) 4142 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 4143 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 4144 #define SCCNXP_HAVE_IO 0x00000001 4145 #define SCCNXP_HAVE_MR0 0x00000002 4146 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 4147 #endif 4148 /* LDV_COMMENT_END_PREP */ 4149 /* LDV_COMMENT_FUNCTION_CALL */ 4150 ldv_handler_precall(); 4151 sccnxp_ist( var_sccnxp_ist_13_p0, var_sccnxp_ist_13_p1); 4152 /* LDV_COMMENT_BEGIN_PREP */ 4153 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 4154 #endif 4155 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 4156 #endif 4157 /* LDV_COMMENT_END_PREP */ 4158 LDV_IN_INTERRUPT=1; 4159 4160 4161 4162 } 4163 4164 break; 4165 default: break; 4166 4167 } 4168 4169 } 4170 4171 ldv_module_exit: 4172 4173 /* LDV_COMMENT_FUNCTION_CALL Checks that all resources and locks are correctly released before the driver will be unloaded. */ 4174 ldv_final: ldv_check_final_state(); 4175 4176 /* LDV_COMMENT_END_FUNCTION_CALL_SECTION */ 4177 return; 4178 4179 } 4180 #endif 4181 4182 /* LDV_COMMENT_END_MAIN */
1 2 #include <linux/kernel.h> 3 bool ldv_is_err(const void *ptr); 4 bool ldv_is_err_or_null(const void *ptr); 5 void* ldv_err_ptr(long error); 6 long ldv_ptr_err(const void *ptr); 7 8 #include <linux/module.h> 9 struct clk; 10 11 extern void ldv_clk_disable_clk(struct clk *clk); 12 extern int ldv_clk_enable_clk(void); 13 #line 1 "/work/ldvuser/ref_launch/work/current--X--.--X--defaultlinux-4.13-rc1--X--320_7a--X--cpachecker/linux-4.13-rc1/csd_deg_dscv/4872/dscv_tempdir/dscv/ri/320_7a/drivers/tty/serial/sccnxp.c" 14 15 /* 16 * NXP (Philips) SCC+++(SCN+++) serial driver 17 * 18 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> 19 * 20 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) 21 * 22 * This program is free software; you can redistribute it and/or modify 23 * it under the terms of the GNU General Public License as published by 24 * the Free Software Foundation; either version 2 of the License, or 25 * (at your option) any later version. 26 */ 27 28 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 29 #define SUPPORT_SYSRQ 30 #endif 31 32 #include <linux/clk.h> 33 #include <linux/err.h> 34 #include <linux/module.h> 35 #include <linux/device.h> 36 #include <linux/console.h> 37 #include <linux/serial_core.h> 38 #include <linux/serial.h> 39 #include <linux/io.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/spinlock.h> 43 #include <linux/platform_device.h> 44 #include <linux/platform_data/serial-sccnxp.h> 45 #include <linux/regulator/consumer.h> 46 47 #define SCCNXP_NAME "uart-sccnxp" 48 #define SCCNXP_MAJOR 204 49 #define SCCNXP_MINOR 205 50 51 #define SCCNXP_MR_REG (0x00) 52 # define MR0_BAUD_NORMAL (0 << 0) 53 # define MR0_BAUD_EXT1 (1 << 0) 54 # define MR0_BAUD_EXT2 (5 << 0) 55 # define MR0_FIFO (1 << 3) 56 # define MR0_TXLVL (1 << 4) 57 # define MR1_BITS_5 (0 << 0) 58 # define MR1_BITS_6 (1 << 0) 59 # define MR1_BITS_7 (2 << 0) 60 # define MR1_BITS_8 (3 << 0) 61 # define MR1_PAR_EVN (0 << 2) 62 # define MR1_PAR_ODD (1 << 2) 63 # define MR1_PAR_NO (4 << 2) 64 # define MR2_STOP1 (7 << 0) 65 # define MR2_STOP2 (0xf << 0) 66 #define SCCNXP_SR_REG (0x01) 67 #define SCCNXP_CSR_REG SCCNXP_SR_REG 68 # define SR_RXRDY (1 << 0) 69 # define SR_FULL (1 << 1) 70 # define SR_TXRDY (1 << 2) 71 # define SR_TXEMT (1 << 3) 72 # define SR_OVR (1 << 4) 73 # define SR_PE (1 << 5) 74 # define SR_FE (1 << 6) 75 # define SR_BRK (1 << 7) 76 #define SCCNXP_CR_REG (0x02) 77 # define CR_RX_ENABLE (1 << 0) 78 # define CR_RX_DISABLE (1 << 1) 79 # define CR_TX_ENABLE (1 << 2) 80 # define CR_TX_DISABLE (1 << 3) 81 # define CR_CMD_MRPTR1 (0x01 << 4) 82 # define CR_CMD_RX_RESET (0x02 << 4) 83 # define CR_CMD_TX_RESET (0x03 << 4) 84 # define CR_CMD_STATUS_RESET (0x04 << 4) 85 # define CR_CMD_BREAK_RESET (0x05 << 4) 86 # define CR_CMD_START_BREAK (0x06 << 4) 87 # define CR_CMD_STOP_BREAK (0x07 << 4) 88 # define CR_CMD_MRPTR0 (0x0b << 4) 89 #define SCCNXP_RHR_REG (0x03) 90 #define SCCNXP_THR_REG SCCNXP_RHR_REG 91 #define SCCNXP_IPCR_REG (0x04) 92 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 93 # define ACR_BAUD0 (0 << 7) 94 # define ACR_BAUD1 (1 << 7) 95 # define ACR_TIMER_MODE (6 << 4) 96 #define SCCNXP_ISR_REG (0x05) 97 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 98 # define IMR_TXRDY (1 << 0) 99 # define IMR_RXRDY (1 << 1) 100 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 101 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 102 #define SCCNXP_IPR_REG (0x0d) 103 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 104 #define SCCNXP_SOP_REG (0x0e) 105 #define SCCNXP_ROP_REG (0x0f) 106 107 /* Route helpers */ 108 #define MCTRL_MASK(sig) (0xf << (sig)) 109 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 110 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 111 112 #define SCCNXP_HAVE_IO 0x00000001 113 #define SCCNXP_HAVE_MR0 0x00000002 114 115 struct sccnxp_chip { 116 const char *name; 117 unsigned int nr; 118 unsigned long freq_min; 119 unsigned long freq_std; 120 unsigned long freq_max; 121 unsigned int flags; 122 unsigned int fifosize; 123 }; 124 125 struct sccnxp_port { 126 struct uart_driver uart; 127 struct uart_port port[SCCNXP_MAX_UARTS]; 128 bool opened[SCCNXP_MAX_UARTS]; 129 130 int irq; 131 u8 imr; 132 133 struct sccnxp_chip *chip; 134 135 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 136 struct console console; 137 #endif 138 139 spinlock_t lock; 140 141 bool poll; 142 struct timer_list timer; 143 144 struct sccnxp_pdata pdata; 145 146 struct regulator *regulator; 147 }; 148 149 static const struct sccnxp_chip sc2681 = { 150 .name = "SC2681", 151 .nr = 2, 152 .freq_min = 1000000, 153 .freq_std = 3686400, 154 .freq_max = 4000000, 155 .flags = SCCNXP_HAVE_IO, 156 .fifosize = 3, 157 }; 158 159 static const struct sccnxp_chip sc2691 = { 160 .name = "SC2691", 161 .nr = 1, 162 .freq_min = 1000000, 163 .freq_std = 3686400, 164 .freq_max = 4000000, 165 .flags = 0, 166 .fifosize = 3, 167 }; 168 169 static const struct sccnxp_chip sc2692 = { 170 .name = "SC2692", 171 .nr = 2, 172 .freq_min = 1000000, 173 .freq_std = 3686400, 174 .freq_max = 4000000, 175 .flags = SCCNXP_HAVE_IO, 176 .fifosize = 3, 177 }; 178 179 static const struct sccnxp_chip sc2891 = { 180 .name = "SC2891", 181 .nr = 1, 182 .freq_min = 100000, 183 .freq_std = 3686400, 184 .freq_max = 8000000, 185 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 186 .fifosize = 16, 187 }; 188 189 static const struct sccnxp_chip sc2892 = { 190 .name = "SC2892", 191 .nr = 2, 192 .freq_min = 100000, 193 .freq_std = 3686400, 194 .freq_max = 8000000, 195 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 196 .fifosize = 16, 197 }; 198 199 static const struct sccnxp_chip sc28202 = { 200 .name = "SC28202", 201 .nr = 2, 202 .freq_min = 1000000, 203 .freq_std = 14745600, 204 .freq_max = 50000000, 205 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, 206 .fifosize = 256, 207 }; 208 209 static const struct sccnxp_chip sc68681 = { 210 .name = "SC68681", 211 .nr = 2, 212 .freq_min = 1000000, 213 .freq_std = 3686400, 214 .freq_max = 4000000, 215 .flags = SCCNXP_HAVE_IO, 216 .fifosize = 3, 217 }; 218 219 static const struct sccnxp_chip sc68692 = { 220 .name = "SC68692", 221 .nr = 2, 222 .freq_min = 1000000, 223 .freq_std = 3686400, 224 .freq_max = 4000000, 225 .flags = SCCNXP_HAVE_IO, 226 .fifosize = 3, 227 }; 228 229 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 230 { 231 return readb(port->membase + (reg << port->regshift)); 232 } 233 234 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 235 { 236 writeb(v, port->membase + (reg << port->regshift)); 237 } 238 239 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 240 { 241 return sccnxp_read(port, (port->line << 3) + reg); 242 } 243 244 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) 245 { 246 sccnxp_write(port, (port->line << 3) + reg, v); 247 } 248 249 static int sccnxp_update_best_err(int a, int b, int *besterr) 250 { 251 int err = abs(a - b); 252 253 if ((*besterr < 0) || (*besterr > err)) { 254 *besterr = err; 255 return 0; 256 } 257 258 return 1; 259 } 260 261 static const struct { 262 u8 csr; 263 u8 acr; 264 u8 mr0; 265 int baud; 266 } baud_std[] = { 267 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, 268 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, 269 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, 270 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, 271 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, 272 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, 273 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, 274 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, 275 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, 276 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, 277 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, 278 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, 279 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, 280 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, 281 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, 282 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, 283 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, 284 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, 285 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, 286 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, 287 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, 288 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, 289 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, 290 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, 291 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, 292 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, 293 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, 294 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, 295 { 0, 0, 0, 0 } 296 }; 297 298 static int sccnxp_set_baud(struct uart_port *port, int baud) 299 { 300 struct sccnxp_port *s = dev_get_drvdata(port->dev); 301 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 302 struct sccnxp_chip *chip = s->chip; 303 u8 i, acr = 0, csr = 0, mr0 = 0; 304 305 /* Find best baud from table */ 306 for (i = 0; baud_std[i].baud && besterr; i++) { 307 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0)) 308 continue; 309 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud); 310 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 311 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 312 acr = baud_std[i].acr; 313 csr = baud_std[i].csr; 314 mr0 = baud_std[i].mr0; 315 bestbaud = tmp_baud; 316 } 317 } 318 319 if (chip->flags & SCCNXP_HAVE_MR0) { 320 /* Enable FIFO, set half level for TX */ 321 mr0 |= MR0_FIFO | MR0_TXLVL; 322 /* Update MR0 */ 323 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); 324 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); 325 } 326 327 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); 328 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); 329 330 if (baud != bestbaud) 331 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", 332 baud, bestbaud); 333 334 return bestbaud; 335 } 336 337 static void sccnxp_enable_irq(struct uart_port *port, int mask) 338 { 339 struct sccnxp_port *s = dev_get_drvdata(port->dev); 340 341 s->imr |= mask << (port->line * 4); 342 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 343 } 344 345 static void sccnxp_disable_irq(struct uart_port *port, int mask) 346 { 347 struct sccnxp_port *s = dev_get_drvdata(port->dev); 348 349 s->imr &= ~(mask << (port->line * 4)); 350 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); 351 } 352 353 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) 354 { 355 u8 bitmask; 356 struct sccnxp_port *s = dev_get_drvdata(port->dev); 357 358 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { 359 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); 360 if (state) 361 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); 362 else 363 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); 364 } 365 } 366 367 static void sccnxp_handle_rx(struct uart_port *port) 368 { 369 u8 sr; 370 unsigned int ch, flag; 371 372 for (;;) { 373 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 374 if (!(sr & SR_RXRDY)) 375 break; 376 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; 377 378 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); 379 380 port->icount.rx++; 381 flag = TTY_NORMAL; 382 383 if (unlikely(sr)) { 384 if (sr & SR_BRK) { 385 port->icount.brk++; 386 sccnxp_port_write(port, SCCNXP_CR_REG, 387 CR_CMD_BREAK_RESET); 388 if (uart_handle_break(port)) 389 continue; 390 } else if (sr & SR_PE) 391 port->icount.parity++; 392 else if (sr & SR_FE) 393 port->icount.frame++; 394 else if (sr & SR_OVR) { 395 port->icount.overrun++; 396 sccnxp_port_write(port, SCCNXP_CR_REG, 397 CR_CMD_STATUS_RESET); 398 } 399 400 sr &= port->read_status_mask; 401 if (sr & SR_BRK) 402 flag = TTY_BREAK; 403 else if (sr & SR_PE) 404 flag = TTY_PARITY; 405 else if (sr & SR_FE) 406 flag = TTY_FRAME; 407 else if (sr & SR_OVR) 408 flag = TTY_OVERRUN; 409 } 410 411 if (uart_handle_sysrq_char(port, ch)) 412 continue; 413 414 if (sr & port->ignore_status_mask) 415 continue; 416 417 uart_insert_char(port, sr, SR_OVR, ch, flag); 418 } 419 420 tty_flip_buffer_push(&port->state->port); 421 } 422 423 static void sccnxp_handle_tx(struct uart_port *port) 424 { 425 u8 sr; 426 struct circ_buf *xmit = &port->state->xmit; 427 struct sccnxp_port *s = dev_get_drvdata(port->dev); 428 429 if (unlikely(port->x_char)) { 430 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); 431 port->icount.tx++; 432 port->x_char = 0; 433 return; 434 } 435 436 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 437 /* Disable TX if FIFO is empty */ 438 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { 439 sccnxp_disable_irq(port, IMR_TXRDY); 440 441 /* Set direction to input */ 442 if (s->chip->flags & SCCNXP_HAVE_IO) 443 sccnxp_set_bit(port, DIR_OP, 0); 444 } 445 return; 446 } 447 448 while (!uart_circ_empty(xmit)) { 449 sr = sccnxp_port_read(port, SCCNXP_SR_REG); 450 if (!(sr & SR_TXRDY)) 451 break; 452 453 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); 454 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 455 port->icount.tx++; 456 } 457 458 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 459 uart_write_wakeup(port); 460 } 461 462 static void sccnxp_handle_events(struct sccnxp_port *s) 463 { 464 int i; 465 u8 isr; 466 467 do { 468 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); 469 isr &= s->imr; 470 if (!isr) 471 break; 472 473 for (i = 0; i < s->uart.nr; i++) { 474 if (s->opened[i] && (isr & ISR_RXRDY(i))) 475 sccnxp_handle_rx(&s->port[i]); 476 if (s->opened[i] && (isr & ISR_TXRDY(i))) 477 sccnxp_handle_tx(&s->port[i]); 478 } 479 } while (1); 480 } 481 482 static void sccnxp_timer(unsigned long data) 483 { 484 struct sccnxp_port *s = (struct sccnxp_port *)data; 485 unsigned long flags; 486 487 spin_lock_irqsave(&s->lock, flags); 488 sccnxp_handle_events(s); 489 spin_unlock_irqrestore(&s->lock, flags); 490 491 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us)); 492 } 493 494 static irqreturn_t sccnxp_ist(int irq, void *dev_id) 495 { 496 struct sccnxp_port *s = (struct sccnxp_port *)dev_id; 497 unsigned long flags; 498 499 spin_lock_irqsave(&s->lock, flags); 500 sccnxp_handle_events(s); 501 spin_unlock_irqrestore(&s->lock, flags); 502 503 return IRQ_HANDLED; 504 } 505 506 static void sccnxp_start_tx(struct uart_port *port) 507 { 508 struct sccnxp_port *s = dev_get_drvdata(port->dev); 509 unsigned long flags; 510 511 spin_lock_irqsave(&s->lock, flags); 512 513 /* Set direction to output */ 514 if (s->chip->flags & SCCNXP_HAVE_IO) 515 sccnxp_set_bit(port, DIR_OP, 1); 516 517 sccnxp_enable_irq(port, IMR_TXRDY); 518 519 spin_unlock_irqrestore(&s->lock, flags); 520 } 521 522 static void sccnxp_stop_tx(struct uart_port *port) 523 { 524 /* Do nothing */ 525 } 526 527 static void sccnxp_stop_rx(struct uart_port *port) 528 { 529 struct sccnxp_port *s = dev_get_drvdata(port->dev); 530 unsigned long flags; 531 532 spin_lock_irqsave(&s->lock, flags); 533 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); 534 spin_unlock_irqrestore(&s->lock, flags); 535 } 536 537 static unsigned int sccnxp_tx_empty(struct uart_port *port) 538 { 539 u8 val; 540 unsigned long flags; 541 struct sccnxp_port *s = dev_get_drvdata(port->dev); 542 543 spin_lock_irqsave(&s->lock, flags); 544 val = sccnxp_port_read(port, SCCNXP_SR_REG); 545 spin_unlock_irqrestore(&s->lock, flags); 546 547 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; 548 } 549 550 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) 551 { 552 struct sccnxp_port *s = dev_get_drvdata(port->dev); 553 unsigned long flags; 554 555 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 556 return; 557 558 spin_lock_irqsave(&s->lock, flags); 559 560 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); 561 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); 562 563 spin_unlock_irqrestore(&s->lock, flags); 564 } 565 566 static unsigned int sccnxp_get_mctrl(struct uart_port *port) 567 { 568 u8 bitmask, ipr; 569 unsigned long flags; 570 struct sccnxp_port *s = dev_get_drvdata(port->dev); 571 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 572 573 if (!(s->chip->flags & SCCNXP_HAVE_IO)) 574 return mctrl; 575 576 spin_lock_irqsave(&s->lock, flags); 577 578 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); 579 580 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { 581 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 582 DSR_IP); 583 mctrl &= ~TIOCM_DSR; 584 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; 585 } 586 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { 587 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 588 CTS_IP); 589 mctrl &= ~TIOCM_CTS; 590 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; 591 } 592 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { 593 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 594 DCD_IP); 595 mctrl &= ~TIOCM_CAR; 596 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; 597 } 598 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { 599 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], 600 RNG_IP); 601 mctrl &= ~TIOCM_RNG; 602 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; 603 } 604 605 spin_unlock_irqrestore(&s->lock, flags); 606 607 return mctrl; 608 } 609 610 static void sccnxp_break_ctl(struct uart_port *port, int break_state) 611 { 612 struct sccnxp_port *s = dev_get_drvdata(port->dev); 613 unsigned long flags; 614 615 spin_lock_irqsave(&s->lock, flags); 616 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? 617 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); 618 spin_unlock_irqrestore(&s->lock, flags); 619 } 620 621 static void sccnxp_set_termios(struct uart_port *port, 622 struct ktermios *termios, struct ktermios *old) 623 { 624 struct sccnxp_port *s = dev_get_drvdata(port->dev); 625 unsigned long flags; 626 u8 mr1, mr2; 627 int baud; 628 629 spin_lock_irqsave(&s->lock, flags); 630 631 /* Mask termios capabilities we don't support */ 632 termios->c_cflag &= ~CMSPAR; 633 634 /* Disable RX & TX, reset break condition, status and FIFOs */ 635 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | 636 CR_RX_DISABLE | CR_TX_DISABLE); 637 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 638 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 639 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 640 641 /* Word size */ 642 switch (termios->c_cflag & CSIZE) { 643 case CS5: 644 mr1 = MR1_BITS_5; 645 break; 646 case CS6: 647 mr1 = MR1_BITS_6; 648 break; 649 case CS7: 650 mr1 = MR1_BITS_7; 651 break; 652 case CS8: 653 default: 654 mr1 = MR1_BITS_8; 655 break; 656 } 657 658 /* Parity */ 659 if (termios->c_cflag & PARENB) { 660 if (termios->c_cflag & PARODD) 661 mr1 |= MR1_PAR_ODD; 662 } else 663 mr1 |= MR1_PAR_NO; 664 665 /* Stop bits */ 666 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; 667 668 /* Update desired format */ 669 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); 670 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); 671 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); 672 673 /* Set read status mask */ 674 port->read_status_mask = SR_OVR; 675 if (termios->c_iflag & INPCK) 676 port->read_status_mask |= SR_PE | SR_FE; 677 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 678 port->read_status_mask |= SR_BRK; 679 680 /* Set status ignore mask */ 681 port->ignore_status_mask = 0; 682 if (termios->c_iflag & IGNBRK) 683 port->ignore_status_mask |= SR_BRK; 684 if (termios->c_iflag & IGNPAR) 685 port->ignore_status_mask |= SR_PE; 686 if (!(termios->c_cflag & CREAD)) 687 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; 688 689 /* Setup baudrate */ 690 baud = uart_get_baud_rate(port, termios, old, 50, 691 (s->chip->flags & SCCNXP_HAVE_MR0) ? 692 230400 : 38400); 693 baud = sccnxp_set_baud(port, baud); 694 695 /* Update timeout according to new baud rate */ 696 uart_update_timeout(port, termios->c_cflag, baud); 697 698 /* Report actual baudrate back to core */ 699 if (tty_termios_baud_rate(termios)) 700 tty_termios_encode_baud_rate(termios, baud, baud); 701 702 /* Enable RX & TX */ 703 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 704 705 spin_unlock_irqrestore(&s->lock, flags); 706 } 707 708 static int sccnxp_startup(struct uart_port *port) 709 { 710 struct sccnxp_port *s = dev_get_drvdata(port->dev); 711 unsigned long flags; 712 713 spin_lock_irqsave(&s->lock, flags); 714 715 if (s->chip->flags & SCCNXP_HAVE_IO) { 716 /* Outputs are controlled manually */ 717 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 718 } 719 720 /* Reset break condition, status and FIFOs */ 721 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); 722 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); 723 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); 724 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); 725 726 /* Enable RX & TX */ 727 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); 728 729 /* Enable RX interrupt */ 730 sccnxp_enable_irq(port, IMR_RXRDY); 731 732 s->opened[port->line] = 1; 733 734 spin_unlock_irqrestore(&s->lock, flags); 735 736 return 0; 737 } 738 739 static void sccnxp_shutdown(struct uart_port *port) 740 { 741 struct sccnxp_port *s = dev_get_drvdata(port->dev); 742 unsigned long flags; 743 744 spin_lock_irqsave(&s->lock, flags); 745 746 s->opened[port->line] = 0; 747 748 /* Disable interrupts */ 749 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); 750 751 /* Disable TX & RX */ 752 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 753 754 /* Leave direction to input */ 755 if (s->chip->flags & SCCNXP_HAVE_IO) 756 sccnxp_set_bit(port, DIR_OP, 0); 757 758 spin_unlock_irqrestore(&s->lock, flags); 759 } 760 761 static const char *sccnxp_type(struct uart_port *port) 762 { 763 struct sccnxp_port *s = dev_get_drvdata(port->dev); 764 765 return (port->type == PORT_SC26XX) ? s->chip->name : NULL; 766 } 767 768 static void sccnxp_release_port(struct uart_port *port) 769 { 770 /* Do nothing */ 771 } 772 773 static int sccnxp_request_port(struct uart_port *port) 774 { 775 /* Do nothing */ 776 return 0; 777 } 778 779 static void sccnxp_config_port(struct uart_port *port, int flags) 780 { 781 if (flags & UART_CONFIG_TYPE) 782 port->type = PORT_SC26XX; 783 } 784 785 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) 786 { 787 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) 788 return 0; 789 if (s->irq == port->irq) 790 return 0; 791 792 return -EINVAL; 793 } 794 795 static const struct uart_ops sccnxp_ops = { 796 .tx_empty = sccnxp_tx_empty, 797 .set_mctrl = sccnxp_set_mctrl, 798 .get_mctrl = sccnxp_get_mctrl, 799 .stop_tx = sccnxp_stop_tx, 800 .start_tx = sccnxp_start_tx, 801 .stop_rx = sccnxp_stop_rx, 802 .break_ctl = sccnxp_break_ctl, 803 .startup = sccnxp_startup, 804 .shutdown = sccnxp_shutdown, 805 .set_termios = sccnxp_set_termios, 806 .type = sccnxp_type, 807 .release_port = sccnxp_release_port, 808 .request_port = sccnxp_request_port, 809 .config_port = sccnxp_config_port, 810 .verify_port = sccnxp_verify_port, 811 }; 812 813 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 814 static void sccnxp_console_putchar(struct uart_port *port, int c) 815 { 816 int tryes = 100000; 817 818 while (tryes--) { 819 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { 820 sccnxp_port_write(port, SCCNXP_THR_REG, c); 821 break; 822 } 823 barrier(); 824 } 825 } 826 827 static void sccnxp_console_write(struct console *co, const char *c, unsigned n) 828 { 829 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 830 struct uart_port *port = &s->port[co->index]; 831 unsigned long flags; 832 833 spin_lock_irqsave(&s->lock, flags); 834 uart_console_write(port, c, n, sccnxp_console_putchar); 835 spin_unlock_irqrestore(&s->lock, flags); 836 } 837 838 static int sccnxp_console_setup(struct console *co, char *options) 839 { 840 struct sccnxp_port *s = (struct sccnxp_port *)co->data; 841 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 842 int baud = 9600, bits = 8, parity = 'n', flow = 'n'; 843 844 if (options) 845 uart_parse_options(options, &baud, &parity, &bits, &flow); 846 847 return uart_set_options(port, co, baud, parity, bits, flow); 848 } 849 #endif 850 851 static const struct platform_device_id sccnxp_id_table[] = { 852 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, }, 853 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, }, 854 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, }, 855 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, }, 856 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, }, 857 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, }, 858 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, }, 859 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, }, 860 { } 861 }; 862 MODULE_DEVICE_TABLE(platform, sccnxp_id_table); 863 864 static int sccnxp_probe(struct platform_device *pdev) 865 { 866 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 867 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 868 int i, ret, uartclk; 869 struct sccnxp_port *s; 870 void __iomem *membase; 871 struct clk *clk; 872 873 membase = devm_ioremap_resource(&pdev->dev, res); 874 if (IS_ERR(membase)) 875 return PTR_ERR(membase); 876 877 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); 878 if (!s) { 879 dev_err(&pdev->dev, "Error allocating port structure\n"); 880 return -ENOMEM; 881 } 882 platform_set_drvdata(pdev, s); 883 884 spin_lock_init(&s->lock); 885 886 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data; 887 888 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 889 if (!IS_ERR(s->regulator)) { 890 ret = regulator_enable(s->regulator); 891 if (ret) { 892 dev_err(&pdev->dev, 893 "Failed to enable regulator: %i\n", ret); 894 return ret; 895 } 896 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) 897 return -EPROBE_DEFER; 898 899 clk = devm_clk_get(&pdev->dev, NULL); 900 if (IS_ERR(clk)) { 901 ret = PTR_ERR(clk); 902 if (ret == -EPROBE_DEFER) 903 goto err_out; 904 uartclk = 0; 905 } else { 906 clk_prepare_enable(clk); 907 uartclk = clk_get_rate(clk); 908 } 909 910 if (!uartclk) { 911 dev_notice(&pdev->dev, "Using default clock frequency\n"); 912 uartclk = s->chip->freq_std; 913 } 914 915 /* Check input frequency */ 916 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { 917 dev_err(&pdev->dev, "Frequency out of bounds\n"); 918 ret = -EINVAL; 919 goto err_out; 920 } 921 922 if (pdata) 923 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); 924 925 if (s->pdata.poll_time_us) { 926 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", 927 s->pdata.poll_time_us); 928 s->poll = 1; 929 } 930 931 if (!s->poll) { 932 s->irq = platform_get_irq(pdev, 0); 933 if (s->irq < 0) { 934 dev_err(&pdev->dev, "Missing irq resource data\n"); 935 ret = -ENXIO; 936 goto err_out; 937 } 938 } 939 940 s->uart.owner = THIS_MODULE; 941 s->uart.dev_name = "ttySC"; 942 s->uart.major = SCCNXP_MAJOR; 943 s->uart.minor = SCCNXP_MINOR; 944 s->uart.nr = s->chip->nr; 945 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 946 s->uart.cons = &s->console; 947 s->uart.cons->device = uart_console_device; 948 s->uart.cons->write = sccnxp_console_write; 949 s->uart.cons->setup = sccnxp_console_setup; 950 s->uart.cons->flags = CON_PRINTBUFFER; 951 s->uart.cons->index = -1; 952 s->uart.cons->data = s; 953 strcpy(s->uart.cons->name, "ttySC"); 954 #endif 955 ret = uart_register_driver(&s->uart); 956 if (ret) { 957 dev_err(&pdev->dev, "Registering UART driver failed\n"); 958 goto err_out; 959 } 960 961 for (i = 0; i < s->uart.nr; i++) { 962 s->port[i].line = i; 963 s->port[i].dev = &pdev->dev; 964 s->port[i].irq = s->irq; 965 s->port[i].type = PORT_SC26XX; 966 s->port[i].fifosize = s->chip->fifosize; 967 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 968 s->port[i].iotype = UPIO_MEM; 969 s->port[i].mapbase = res->start; 970 s->port[i].membase = membase; 971 s->port[i].regshift = s->pdata.reg_shift; 972 s->port[i].uartclk = uartclk; 973 s->port[i].ops = &sccnxp_ops; 974 uart_add_one_port(&s->uart, &s->port[i]); 975 /* Set direction to input */ 976 if (s->chip->flags & SCCNXP_HAVE_IO) 977 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 978 } 979 980 /* Disable interrupts */ 981 s->imr = 0; 982 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); 983 984 if (!s->poll) { 985 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, 986 sccnxp_ist, 987 IRQF_TRIGGER_FALLING | 988 IRQF_ONESHOT, 989 dev_name(&pdev->dev), s); 990 if (!ret) 991 return 0; 992 993 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); 994 } else { 995 init_timer(&s->timer); 996 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); 997 mod_timer(&s->timer, jiffies + 998 usecs_to_jiffies(s->pdata.poll_time_us)); 999 return 0; 1000 } 1001 1002 uart_unregister_driver(&s->uart); 1003 err_out: 1004 if (!IS_ERR(s->regulator)) 1005 return regulator_disable(s->regulator); 1006 1007 return ret; 1008 } 1009 1010 static int sccnxp_remove(struct platform_device *pdev) 1011 { 1012 int i; 1013 struct sccnxp_port *s = platform_get_drvdata(pdev); 1014 1015 if (!s->poll) 1016 devm_free_irq(&pdev->dev, s->irq, s); 1017 else 1018 del_timer_sync(&s->timer); 1019 1020 for (i = 0; i < s->uart.nr; i++) 1021 uart_remove_one_port(&s->uart, &s->port[i]); 1022 1023 uart_unregister_driver(&s->uart); 1024 1025 if (!IS_ERR(s->regulator)) 1026 return regulator_disable(s->regulator); 1027 1028 return 0; 1029 } 1030 1031 static struct platform_driver sccnxp_uart_driver = { 1032 .driver = { 1033 .name = SCCNXP_NAME, 1034 }, 1035 .probe = sccnxp_probe, 1036 .remove = sccnxp_remove, 1037 .id_table = sccnxp_id_table, 1038 }; 1039 module_platform_driver(sccnxp_uart_driver); 1040 1041 MODULE_LICENSE("GPL v2"); 1042 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1043 MODULE_DESCRIPTION("SCCNXP serial driver"); 1044 1045 1046 1047 1048 1049 /* LDV_COMMENT_BEGIN_MAIN */ 1050 #ifdef LDV_MAIN0_sequence_infinite_withcheck_stateful 1051 1052 /*###########################################################################*/ 1053 1054 /*############## Driver Environment Generator 0.2 output ####################*/ 1055 1056 /*###########################################################################*/ 1057 1058 1059 1060 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test if all kernel resources are correctly released by driver before driver will be unloaded. */ 1061 void ldv_check_final_state(void); 1062 1063 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result. */ 1064 void ldv_check_return_value(int res); 1065 1066 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Test correct return result of probe() function. */ 1067 void ldv_check_return_value_probe(int res); 1068 1069 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Initializes the model. */ 1070 void ldv_initialize(void); 1071 1072 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Reinitializes the model between distinct model function calls. */ 1073 void ldv_handler_precall(void); 1074 1075 /* LDV_COMMENT_FUNCTION_DECLARE_LDV Special function for LDV verifier. Returns arbitrary interger value. */ 1076 int nondet_int(void); 1077 1078 /* LDV_COMMENT_VAR_DECLARE_LDV Special variable for LDV verifier. */ 1079 int LDV_IN_INTERRUPT; 1080 1081 /* LDV_COMMENT_FUNCTION_MAIN Main function for LDV verifier. */ 1082 void ldv_main0_sequence_infinite_withcheck_stateful(void) { 1083 1084 1085 1086 /* LDV_COMMENT_BEGIN_VARIABLE_DECLARATION_PART */ 1087 /*============================= VARIABLE DECLARATION PART =============================*/ 1088 /** STRUCT: struct type: uart_ops, struct name: sccnxp_ops **/ 1089 /* content: static unsigned int sccnxp_tx_empty(struct uart_port *port)*/ 1090 /* LDV_COMMENT_BEGIN_PREP */ 1091 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1092 #define SUPPORT_SYSRQ 1093 #endif 1094 #define SCCNXP_NAME "uart-sccnxp" 1095 #define SCCNXP_MAJOR 204 1096 #define SCCNXP_MINOR 205 1097 #define SCCNXP_MR_REG (0x00) 1098 # define MR0_BAUD_NORMAL (0 << 0) 1099 # define MR0_BAUD_EXT1 (1 << 0) 1100 # define MR0_BAUD_EXT2 (5 << 0) 1101 # define MR0_FIFO (1 << 3) 1102 # define MR0_TXLVL (1 << 4) 1103 # define MR1_BITS_5 (0 << 0) 1104 # define MR1_BITS_6 (1 << 0) 1105 # define MR1_BITS_7 (2 << 0) 1106 # define MR1_BITS_8 (3 << 0) 1107 # define MR1_PAR_EVN (0 << 2) 1108 # define MR1_PAR_ODD (1 << 2) 1109 # define MR1_PAR_NO (4 << 2) 1110 # define MR2_STOP1 (7 << 0) 1111 # define MR2_STOP2 (0xf << 0) 1112 #define SCCNXP_SR_REG (0x01) 1113 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1114 # define SR_RXRDY (1 << 0) 1115 # define SR_FULL (1 << 1) 1116 # define SR_TXRDY (1 << 2) 1117 # define SR_TXEMT (1 << 3) 1118 # define SR_OVR (1 << 4) 1119 # define SR_PE (1 << 5) 1120 # define SR_FE (1 << 6) 1121 # define SR_BRK (1 << 7) 1122 #define SCCNXP_CR_REG (0x02) 1123 # define CR_RX_ENABLE (1 << 0) 1124 # define CR_RX_DISABLE (1 << 1) 1125 # define CR_TX_ENABLE (1 << 2) 1126 # define CR_TX_DISABLE (1 << 3) 1127 # define CR_CMD_MRPTR1 (0x01 << 4) 1128 # define CR_CMD_RX_RESET (0x02 << 4) 1129 # define CR_CMD_TX_RESET (0x03 << 4) 1130 # define CR_CMD_STATUS_RESET (0x04 << 4) 1131 # define CR_CMD_BREAK_RESET (0x05 << 4) 1132 # define CR_CMD_START_BREAK (0x06 << 4) 1133 # define CR_CMD_STOP_BREAK (0x07 << 4) 1134 # define CR_CMD_MRPTR0 (0x0b << 4) 1135 #define SCCNXP_RHR_REG (0x03) 1136 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1137 #define SCCNXP_IPCR_REG (0x04) 1138 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1139 # define ACR_BAUD0 (0 << 7) 1140 # define ACR_BAUD1 (1 << 7) 1141 # define ACR_TIMER_MODE (6 << 4) 1142 #define SCCNXP_ISR_REG (0x05) 1143 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1144 # define IMR_TXRDY (1 << 0) 1145 # define IMR_RXRDY (1 << 1) 1146 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1147 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1148 #define SCCNXP_IPR_REG (0x0d) 1149 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1150 #define SCCNXP_SOP_REG (0x0e) 1151 #define SCCNXP_ROP_REG (0x0f) 1152 #define MCTRL_MASK(sig) (0xf << (sig)) 1153 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1154 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1155 #define SCCNXP_HAVE_IO 0x00000001 1156 #define SCCNXP_HAVE_MR0 0x00000002 1157 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1158 #endif 1159 /* LDV_COMMENT_END_PREP */ 1160 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_tx_empty" */ 1161 struct uart_port * var_group1; 1162 /* LDV_COMMENT_BEGIN_PREP */ 1163 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1164 #endif 1165 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1166 #endif 1167 /* LDV_COMMENT_END_PREP */ 1168 /* content: static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)*/ 1169 /* LDV_COMMENT_BEGIN_PREP */ 1170 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1171 #define SUPPORT_SYSRQ 1172 #endif 1173 #define SCCNXP_NAME "uart-sccnxp" 1174 #define SCCNXP_MAJOR 204 1175 #define SCCNXP_MINOR 205 1176 #define SCCNXP_MR_REG (0x00) 1177 # define MR0_BAUD_NORMAL (0 << 0) 1178 # define MR0_BAUD_EXT1 (1 << 0) 1179 # define MR0_BAUD_EXT2 (5 << 0) 1180 # define MR0_FIFO (1 << 3) 1181 # define MR0_TXLVL (1 << 4) 1182 # define MR1_BITS_5 (0 << 0) 1183 # define MR1_BITS_6 (1 << 0) 1184 # define MR1_BITS_7 (2 << 0) 1185 # define MR1_BITS_8 (3 << 0) 1186 # define MR1_PAR_EVN (0 << 2) 1187 # define MR1_PAR_ODD (1 << 2) 1188 # define MR1_PAR_NO (4 << 2) 1189 # define MR2_STOP1 (7 << 0) 1190 # define MR2_STOP2 (0xf << 0) 1191 #define SCCNXP_SR_REG (0x01) 1192 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1193 # define SR_RXRDY (1 << 0) 1194 # define SR_FULL (1 << 1) 1195 # define SR_TXRDY (1 << 2) 1196 # define SR_TXEMT (1 << 3) 1197 # define SR_OVR (1 << 4) 1198 # define SR_PE (1 << 5) 1199 # define SR_FE (1 << 6) 1200 # define SR_BRK (1 << 7) 1201 #define SCCNXP_CR_REG (0x02) 1202 # define CR_RX_ENABLE (1 << 0) 1203 # define CR_RX_DISABLE (1 << 1) 1204 # define CR_TX_ENABLE (1 << 2) 1205 # define CR_TX_DISABLE (1 << 3) 1206 # define CR_CMD_MRPTR1 (0x01 << 4) 1207 # define CR_CMD_RX_RESET (0x02 << 4) 1208 # define CR_CMD_TX_RESET (0x03 << 4) 1209 # define CR_CMD_STATUS_RESET (0x04 << 4) 1210 # define CR_CMD_BREAK_RESET (0x05 << 4) 1211 # define CR_CMD_START_BREAK (0x06 << 4) 1212 # define CR_CMD_STOP_BREAK (0x07 << 4) 1213 # define CR_CMD_MRPTR0 (0x0b << 4) 1214 #define SCCNXP_RHR_REG (0x03) 1215 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1216 #define SCCNXP_IPCR_REG (0x04) 1217 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1218 # define ACR_BAUD0 (0 << 7) 1219 # define ACR_BAUD1 (1 << 7) 1220 # define ACR_TIMER_MODE (6 << 4) 1221 #define SCCNXP_ISR_REG (0x05) 1222 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1223 # define IMR_TXRDY (1 << 0) 1224 # define IMR_RXRDY (1 << 1) 1225 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1226 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1227 #define SCCNXP_IPR_REG (0x0d) 1228 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1229 #define SCCNXP_SOP_REG (0x0e) 1230 #define SCCNXP_ROP_REG (0x0f) 1231 #define MCTRL_MASK(sig) (0xf << (sig)) 1232 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1233 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1234 #define SCCNXP_HAVE_IO 0x00000001 1235 #define SCCNXP_HAVE_MR0 0x00000002 1236 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1237 #endif 1238 /* LDV_COMMENT_END_PREP */ 1239 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_set_mctrl" */ 1240 unsigned int var_sccnxp_set_mctrl_18_p1; 1241 /* LDV_COMMENT_BEGIN_PREP */ 1242 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1243 #endif 1244 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1245 #endif 1246 /* LDV_COMMENT_END_PREP */ 1247 /* content: static unsigned int sccnxp_get_mctrl(struct uart_port *port)*/ 1248 /* LDV_COMMENT_BEGIN_PREP */ 1249 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1250 #define SUPPORT_SYSRQ 1251 #endif 1252 #define SCCNXP_NAME "uart-sccnxp" 1253 #define SCCNXP_MAJOR 204 1254 #define SCCNXP_MINOR 205 1255 #define SCCNXP_MR_REG (0x00) 1256 # define MR0_BAUD_NORMAL (0 << 0) 1257 # define MR0_BAUD_EXT1 (1 << 0) 1258 # define MR0_BAUD_EXT2 (5 << 0) 1259 # define MR0_FIFO (1 << 3) 1260 # define MR0_TXLVL (1 << 4) 1261 # define MR1_BITS_5 (0 << 0) 1262 # define MR1_BITS_6 (1 << 0) 1263 # define MR1_BITS_7 (2 << 0) 1264 # define MR1_BITS_8 (3 << 0) 1265 # define MR1_PAR_EVN (0 << 2) 1266 # define MR1_PAR_ODD (1 << 2) 1267 # define MR1_PAR_NO (4 << 2) 1268 # define MR2_STOP1 (7 << 0) 1269 # define MR2_STOP2 (0xf << 0) 1270 #define SCCNXP_SR_REG (0x01) 1271 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1272 # define SR_RXRDY (1 << 0) 1273 # define SR_FULL (1 << 1) 1274 # define SR_TXRDY (1 << 2) 1275 # define SR_TXEMT (1 << 3) 1276 # define SR_OVR (1 << 4) 1277 # define SR_PE (1 << 5) 1278 # define SR_FE (1 << 6) 1279 # define SR_BRK (1 << 7) 1280 #define SCCNXP_CR_REG (0x02) 1281 # define CR_RX_ENABLE (1 << 0) 1282 # define CR_RX_DISABLE (1 << 1) 1283 # define CR_TX_ENABLE (1 << 2) 1284 # define CR_TX_DISABLE (1 << 3) 1285 # define CR_CMD_MRPTR1 (0x01 << 4) 1286 # define CR_CMD_RX_RESET (0x02 << 4) 1287 # define CR_CMD_TX_RESET (0x03 << 4) 1288 # define CR_CMD_STATUS_RESET (0x04 << 4) 1289 # define CR_CMD_BREAK_RESET (0x05 << 4) 1290 # define CR_CMD_START_BREAK (0x06 << 4) 1291 # define CR_CMD_STOP_BREAK (0x07 << 4) 1292 # define CR_CMD_MRPTR0 (0x0b << 4) 1293 #define SCCNXP_RHR_REG (0x03) 1294 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1295 #define SCCNXP_IPCR_REG (0x04) 1296 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1297 # define ACR_BAUD0 (0 << 7) 1298 # define ACR_BAUD1 (1 << 7) 1299 # define ACR_TIMER_MODE (6 << 4) 1300 #define SCCNXP_ISR_REG (0x05) 1301 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1302 # define IMR_TXRDY (1 << 0) 1303 # define IMR_RXRDY (1 << 1) 1304 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1305 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1306 #define SCCNXP_IPR_REG (0x0d) 1307 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1308 #define SCCNXP_SOP_REG (0x0e) 1309 #define SCCNXP_ROP_REG (0x0f) 1310 #define MCTRL_MASK(sig) (0xf << (sig)) 1311 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1312 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1313 #define SCCNXP_HAVE_IO 0x00000001 1314 #define SCCNXP_HAVE_MR0 0x00000002 1315 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1316 #endif 1317 /* LDV_COMMENT_END_PREP */ 1318 /* LDV_COMMENT_BEGIN_PREP */ 1319 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1320 #endif 1321 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1322 #endif 1323 /* LDV_COMMENT_END_PREP */ 1324 /* content: static void sccnxp_stop_tx(struct uart_port *port)*/ 1325 /* LDV_COMMENT_BEGIN_PREP */ 1326 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1327 #define SUPPORT_SYSRQ 1328 #endif 1329 #define SCCNXP_NAME "uart-sccnxp" 1330 #define SCCNXP_MAJOR 204 1331 #define SCCNXP_MINOR 205 1332 #define SCCNXP_MR_REG (0x00) 1333 # define MR0_BAUD_NORMAL (0 << 0) 1334 # define MR0_BAUD_EXT1 (1 << 0) 1335 # define MR0_BAUD_EXT2 (5 << 0) 1336 # define MR0_FIFO (1 << 3) 1337 # define MR0_TXLVL (1 << 4) 1338 # define MR1_BITS_5 (0 << 0) 1339 # define MR1_BITS_6 (1 << 0) 1340 # define MR1_BITS_7 (2 << 0) 1341 # define MR1_BITS_8 (3 << 0) 1342 # define MR1_PAR_EVN (0 << 2) 1343 # define MR1_PAR_ODD (1 << 2) 1344 # define MR1_PAR_NO (4 << 2) 1345 # define MR2_STOP1 (7 << 0) 1346 # define MR2_STOP2 (0xf << 0) 1347 #define SCCNXP_SR_REG (0x01) 1348 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1349 # define SR_RXRDY (1 << 0) 1350 # define SR_FULL (1 << 1) 1351 # define SR_TXRDY (1 << 2) 1352 # define SR_TXEMT (1 << 3) 1353 # define SR_OVR (1 << 4) 1354 # define SR_PE (1 << 5) 1355 # define SR_FE (1 << 6) 1356 # define SR_BRK (1 << 7) 1357 #define SCCNXP_CR_REG (0x02) 1358 # define CR_RX_ENABLE (1 << 0) 1359 # define CR_RX_DISABLE (1 << 1) 1360 # define CR_TX_ENABLE (1 << 2) 1361 # define CR_TX_DISABLE (1 << 3) 1362 # define CR_CMD_MRPTR1 (0x01 << 4) 1363 # define CR_CMD_RX_RESET (0x02 << 4) 1364 # define CR_CMD_TX_RESET (0x03 << 4) 1365 # define CR_CMD_STATUS_RESET (0x04 << 4) 1366 # define CR_CMD_BREAK_RESET (0x05 << 4) 1367 # define CR_CMD_START_BREAK (0x06 << 4) 1368 # define CR_CMD_STOP_BREAK (0x07 << 4) 1369 # define CR_CMD_MRPTR0 (0x0b << 4) 1370 #define SCCNXP_RHR_REG (0x03) 1371 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1372 #define SCCNXP_IPCR_REG (0x04) 1373 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1374 # define ACR_BAUD0 (0 << 7) 1375 # define ACR_BAUD1 (1 << 7) 1376 # define ACR_TIMER_MODE (6 << 4) 1377 #define SCCNXP_ISR_REG (0x05) 1378 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1379 # define IMR_TXRDY (1 << 0) 1380 # define IMR_RXRDY (1 << 1) 1381 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1382 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1383 #define SCCNXP_IPR_REG (0x0d) 1384 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1385 #define SCCNXP_SOP_REG (0x0e) 1386 #define SCCNXP_ROP_REG (0x0f) 1387 #define MCTRL_MASK(sig) (0xf << (sig)) 1388 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1389 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1390 #define SCCNXP_HAVE_IO 0x00000001 1391 #define SCCNXP_HAVE_MR0 0x00000002 1392 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1393 #endif 1394 /* LDV_COMMENT_END_PREP */ 1395 /* LDV_COMMENT_BEGIN_PREP */ 1396 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1397 #endif 1398 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1399 #endif 1400 /* LDV_COMMENT_END_PREP */ 1401 /* content: static void sccnxp_start_tx(struct uart_port *port)*/ 1402 /* LDV_COMMENT_BEGIN_PREP */ 1403 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1404 #define SUPPORT_SYSRQ 1405 #endif 1406 #define SCCNXP_NAME "uart-sccnxp" 1407 #define SCCNXP_MAJOR 204 1408 #define SCCNXP_MINOR 205 1409 #define SCCNXP_MR_REG (0x00) 1410 # define MR0_BAUD_NORMAL (0 << 0) 1411 # define MR0_BAUD_EXT1 (1 << 0) 1412 # define MR0_BAUD_EXT2 (5 << 0) 1413 # define MR0_FIFO (1 << 3) 1414 # define MR0_TXLVL (1 << 4) 1415 # define MR1_BITS_5 (0 << 0) 1416 # define MR1_BITS_6 (1 << 0) 1417 # define MR1_BITS_7 (2 << 0) 1418 # define MR1_BITS_8 (3 << 0) 1419 # define MR1_PAR_EVN (0 << 2) 1420 # define MR1_PAR_ODD (1 << 2) 1421 # define MR1_PAR_NO (4 << 2) 1422 # define MR2_STOP1 (7 << 0) 1423 # define MR2_STOP2 (0xf << 0) 1424 #define SCCNXP_SR_REG (0x01) 1425 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1426 # define SR_RXRDY (1 << 0) 1427 # define SR_FULL (1 << 1) 1428 # define SR_TXRDY (1 << 2) 1429 # define SR_TXEMT (1 << 3) 1430 # define SR_OVR (1 << 4) 1431 # define SR_PE (1 << 5) 1432 # define SR_FE (1 << 6) 1433 # define SR_BRK (1 << 7) 1434 #define SCCNXP_CR_REG (0x02) 1435 # define CR_RX_ENABLE (1 << 0) 1436 # define CR_RX_DISABLE (1 << 1) 1437 # define CR_TX_ENABLE (1 << 2) 1438 # define CR_TX_DISABLE (1 << 3) 1439 # define CR_CMD_MRPTR1 (0x01 << 4) 1440 # define CR_CMD_RX_RESET (0x02 << 4) 1441 # define CR_CMD_TX_RESET (0x03 << 4) 1442 # define CR_CMD_STATUS_RESET (0x04 << 4) 1443 # define CR_CMD_BREAK_RESET (0x05 << 4) 1444 # define CR_CMD_START_BREAK (0x06 << 4) 1445 # define CR_CMD_STOP_BREAK (0x07 << 4) 1446 # define CR_CMD_MRPTR0 (0x0b << 4) 1447 #define SCCNXP_RHR_REG (0x03) 1448 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1449 #define SCCNXP_IPCR_REG (0x04) 1450 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1451 # define ACR_BAUD0 (0 << 7) 1452 # define ACR_BAUD1 (1 << 7) 1453 # define ACR_TIMER_MODE (6 << 4) 1454 #define SCCNXP_ISR_REG (0x05) 1455 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1456 # define IMR_TXRDY (1 << 0) 1457 # define IMR_RXRDY (1 << 1) 1458 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1459 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1460 #define SCCNXP_IPR_REG (0x0d) 1461 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1462 #define SCCNXP_SOP_REG (0x0e) 1463 #define SCCNXP_ROP_REG (0x0f) 1464 #define MCTRL_MASK(sig) (0xf << (sig)) 1465 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1466 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1467 #define SCCNXP_HAVE_IO 0x00000001 1468 #define SCCNXP_HAVE_MR0 0x00000002 1469 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1470 #endif 1471 /* LDV_COMMENT_END_PREP */ 1472 /* LDV_COMMENT_BEGIN_PREP */ 1473 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1474 #endif 1475 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1476 #endif 1477 /* LDV_COMMENT_END_PREP */ 1478 /* content: static void sccnxp_stop_rx(struct uart_port *port)*/ 1479 /* LDV_COMMENT_BEGIN_PREP */ 1480 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1481 #define SUPPORT_SYSRQ 1482 #endif 1483 #define SCCNXP_NAME "uart-sccnxp" 1484 #define SCCNXP_MAJOR 204 1485 #define SCCNXP_MINOR 205 1486 #define SCCNXP_MR_REG (0x00) 1487 # define MR0_BAUD_NORMAL (0 << 0) 1488 # define MR0_BAUD_EXT1 (1 << 0) 1489 # define MR0_BAUD_EXT2 (5 << 0) 1490 # define MR0_FIFO (1 << 3) 1491 # define MR0_TXLVL (1 << 4) 1492 # define MR1_BITS_5 (0 << 0) 1493 # define MR1_BITS_6 (1 << 0) 1494 # define MR1_BITS_7 (2 << 0) 1495 # define MR1_BITS_8 (3 << 0) 1496 # define MR1_PAR_EVN (0 << 2) 1497 # define MR1_PAR_ODD (1 << 2) 1498 # define MR1_PAR_NO (4 << 2) 1499 # define MR2_STOP1 (7 << 0) 1500 # define MR2_STOP2 (0xf << 0) 1501 #define SCCNXP_SR_REG (0x01) 1502 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1503 # define SR_RXRDY (1 << 0) 1504 # define SR_FULL (1 << 1) 1505 # define SR_TXRDY (1 << 2) 1506 # define SR_TXEMT (1 << 3) 1507 # define SR_OVR (1 << 4) 1508 # define SR_PE (1 << 5) 1509 # define SR_FE (1 << 6) 1510 # define SR_BRK (1 << 7) 1511 #define SCCNXP_CR_REG (0x02) 1512 # define CR_RX_ENABLE (1 << 0) 1513 # define CR_RX_DISABLE (1 << 1) 1514 # define CR_TX_ENABLE (1 << 2) 1515 # define CR_TX_DISABLE (1 << 3) 1516 # define CR_CMD_MRPTR1 (0x01 << 4) 1517 # define CR_CMD_RX_RESET (0x02 << 4) 1518 # define CR_CMD_TX_RESET (0x03 << 4) 1519 # define CR_CMD_STATUS_RESET (0x04 << 4) 1520 # define CR_CMD_BREAK_RESET (0x05 << 4) 1521 # define CR_CMD_START_BREAK (0x06 << 4) 1522 # define CR_CMD_STOP_BREAK (0x07 << 4) 1523 # define CR_CMD_MRPTR0 (0x0b << 4) 1524 #define SCCNXP_RHR_REG (0x03) 1525 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1526 #define SCCNXP_IPCR_REG (0x04) 1527 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1528 # define ACR_BAUD0 (0 << 7) 1529 # define ACR_BAUD1 (1 << 7) 1530 # define ACR_TIMER_MODE (6 << 4) 1531 #define SCCNXP_ISR_REG (0x05) 1532 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1533 # define IMR_TXRDY (1 << 0) 1534 # define IMR_RXRDY (1 << 1) 1535 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1536 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1537 #define SCCNXP_IPR_REG (0x0d) 1538 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1539 #define SCCNXP_SOP_REG (0x0e) 1540 #define SCCNXP_ROP_REG (0x0f) 1541 #define MCTRL_MASK(sig) (0xf << (sig)) 1542 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1543 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1544 #define SCCNXP_HAVE_IO 0x00000001 1545 #define SCCNXP_HAVE_MR0 0x00000002 1546 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1547 #endif 1548 /* LDV_COMMENT_END_PREP */ 1549 /* LDV_COMMENT_BEGIN_PREP */ 1550 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1551 #endif 1552 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1553 #endif 1554 /* LDV_COMMENT_END_PREP */ 1555 /* content: static void sccnxp_break_ctl(struct uart_port *port, int break_state)*/ 1556 /* LDV_COMMENT_BEGIN_PREP */ 1557 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1558 #define SUPPORT_SYSRQ 1559 #endif 1560 #define SCCNXP_NAME "uart-sccnxp" 1561 #define SCCNXP_MAJOR 204 1562 #define SCCNXP_MINOR 205 1563 #define SCCNXP_MR_REG (0x00) 1564 # define MR0_BAUD_NORMAL (0 << 0) 1565 # define MR0_BAUD_EXT1 (1 << 0) 1566 # define MR0_BAUD_EXT2 (5 << 0) 1567 # define MR0_FIFO (1 << 3) 1568 # define MR0_TXLVL (1 << 4) 1569 # define MR1_BITS_5 (0 << 0) 1570 # define MR1_BITS_6 (1 << 0) 1571 # define MR1_BITS_7 (2 << 0) 1572 # define MR1_BITS_8 (3 << 0) 1573 # define MR1_PAR_EVN (0 << 2) 1574 # define MR1_PAR_ODD (1 << 2) 1575 # define MR1_PAR_NO (4 << 2) 1576 # define MR2_STOP1 (7 << 0) 1577 # define MR2_STOP2 (0xf << 0) 1578 #define SCCNXP_SR_REG (0x01) 1579 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1580 # define SR_RXRDY (1 << 0) 1581 # define SR_FULL (1 << 1) 1582 # define SR_TXRDY (1 << 2) 1583 # define SR_TXEMT (1 << 3) 1584 # define SR_OVR (1 << 4) 1585 # define SR_PE (1 << 5) 1586 # define SR_FE (1 << 6) 1587 # define SR_BRK (1 << 7) 1588 #define SCCNXP_CR_REG (0x02) 1589 # define CR_RX_ENABLE (1 << 0) 1590 # define CR_RX_DISABLE (1 << 1) 1591 # define CR_TX_ENABLE (1 << 2) 1592 # define CR_TX_DISABLE (1 << 3) 1593 # define CR_CMD_MRPTR1 (0x01 << 4) 1594 # define CR_CMD_RX_RESET (0x02 << 4) 1595 # define CR_CMD_TX_RESET (0x03 << 4) 1596 # define CR_CMD_STATUS_RESET (0x04 << 4) 1597 # define CR_CMD_BREAK_RESET (0x05 << 4) 1598 # define CR_CMD_START_BREAK (0x06 << 4) 1599 # define CR_CMD_STOP_BREAK (0x07 << 4) 1600 # define CR_CMD_MRPTR0 (0x0b << 4) 1601 #define SCCNXP_RHR_REG (0x03) 1602 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1603 #define SCCNXP_IPCR_REG (0x04) 1604 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1605 # define ACR_BAUD0 (0 << 7) 1606 # define ACR_BAUD1 (1 << 7) 1607 # define ACR_TIMER_MODE (6 << 4) 1608 #define SCCNXP_ISR_REG (0x05) 1609 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1610 # define IMR_TXRDY (1 << 0) 1611 # define IMR_RXRDY (1 << 1) 1612 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1613 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1614 #define SCCNXP_IPR_REG (0x0d) 1615 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1616 #define SCCNXP_SOP_REG (0x0e) 1617 #define SCCNXP_ROP_REG (0x0f) 1618 #define MCTRL_MASK(sig) (0xf << (sig)) 1619 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1620 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1621 #define SCCNXP_HAVE_IO 0x00000001 1622 #define SCCNXP_HAVE_MR0 0x00000002 1623 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1624 #endif 1625 /* LDV_COMMENT_END_PREP */ 1626 /* LDV_COMMENT_VAR_DECLARE Variable declaration for function "sccnxp_break_ctl" */ 1627 int var_sccnxp_break_ctl_20_p1; 1628 /* LDV_COMMENT_BEGIN_PREP */ 1629 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1630 #endif 1631 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1632 #endif 1633 /* LDV_COMMENT_END_PREP */ 1634 /* content: static int sccnxp_startup(struct uart_port *port)*/ 1635 /* LDV_COMMENT_BEGIN_PREP */ 1636 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1637 #define SUPPORT_SYSRQ 1638 #endif 1639 #define SCCNXP_NAME "uart-sccnxp" 1640 #define SCCNXP_MAJOR 204 1641 #define SCCNXP_MINOR 205 1642 #define SCCNXP_MR_REG (0x00) 1643 # define MR0_BAUD_NORMAL (0 << 0) 1644 # define MR0_BAUD_EXT1 (1 << 0) 1645 # define MR0_BAUD_EXT2 (5 << 0) 1646 # define MR0_FIFO (1 << 3) 1647 # define MR0_TXLVL (1 << 4) 1648 # define MR1_BITS_5 (0 << 0) 1649 # define MR1_BITS_6 (1 << 0) 1650 # define MR1_BITS_7 (2 << 0) 1651 # define MR1_BITS_8 (3 << 0) 1652 # define MR1_PAR_EVN (0 << 2) 1653 # define MR1_PAR_ODD (1 << 2) 1654 # define MR1_PAR_NO (4 << 2) 1655 # define MR2_STOP1 (7 << 0) 1656 # define MR2_STOP2 (0xf << 0) 1657 #define SCCNXP_SR_REG (0x01) 1658 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1659 # define SR_RXRDY (1 << 0) 1660 # define SR_FULL (1 << 1) 1661 # define SR_TXRDY (1 << 2) 1662 # define SR_TXEMT (1 << 3) 1663 # define SR_OVR (1 << 4) 1664 # define SR_PE (1 << 5) 1665 # define SR_FE (1 << 6) 1666 # define SR_BRK (1 << 7) 1667 #define SCCNXP_CR_REG (0x02) 1668 # define CR_RX_ENABLE (1 << 0) 1669 # define CR_RX_DISABLE (1 << 1) 1670 # define CR_TX_ENABLE (1 << 2) 1671 # define CR_TX_DISABLE (1 << 3) 1672 # define CR_CMD_MRPTR1 (0x01 << 4) 1673 # define CR_CMD_RX_RESET (0x02 << 4) 1674 # define CR_CMD_TX_RESET (0x03 << 4) 1675 # define CR_CMD_STATUS_RESET (0x04 << 4) 1676 # define CR_CMD_BREAK_RESET (0x05 << 4) 1677 # define CR_CMD_START_BREAK (0x06 << 4) 1678 # define CR_CMD_STOP_BREAK (0x07 << 4) 1679 # define CR_CMD_MRPTR0 (0x0b << 4) 1680 #define SCCNXP_RHR_REG (0x03) 1681 #define SCCNXP_THR_REG SCCNXP_RHR_REG 1682 #define SCCNXP_IPCR_REG (0x04) 1683 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG 1684 # define ACR_BAUD0 (0 << 7) 1685 # define ACR_BAUD1 (1 << 7) 1686 # define ACR_TIMER_MODE (6 << 4) 1687 #define SCCNXP_ISR_REG (0x05) 1688 #define SCCNXP_IMR_REG SCCNXP_ISR_REG 1689 # define IMR_TXRDY (1 << 0) 1690 # define IMR_RXRDY (1 << 1) 1691 # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) 1692 # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) 1693 #define SCCNXP_IPR_REG (0x0d) 1694 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG 1695 #define SCCNXP_SOP_REG (0x0e) 1696 #define SCCNXP_ROP_REG (0x0f) 1697 #define MCTRL_MASK(sig) (0xf << (sig)) 1698 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 1699 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 1700 #define SCCNXP_HAVE_IO 0x00000001 1701 #define SCCNXP_HAVE_MR0 0x00000002 1702 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1703 #endif 1704 /* LDV_COMMENT_END_PREP */ 1705 /* LDV_COMMENT_BEGIN_PREP */ 1706 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1707 #endif 1708 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 1709 #endif 1710 /* LDV_COMMENT_END_PREP */ 1711 /* content: static void sccnxp_shutdown(struct uart_port *port)*/ 1712 /* LDV_COMMENT_BEGIN_PREP */ 1713 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 1714 #define SUPPORT_SYSRQ 1715 #endif 1716 #define SCCNXP_NAME "uart-sccnxp" 1717 #define SCCNXP_MAJOR 204 1718 #define SCCNXP_MINOR 205 1719 #define SCCNXP_MR_REG (0x00) 1720 # define MR0_BAUD_NORMAL (0 << 0) 1721 # define MR0_BAUD_EXT1 (1 << 0) 1722 # define MR0_BAUD_EXT2 (5 << 0) 1723 # define MR0_FIFO (1 << 3) 1724 # define MR0_TXLVL (1 << 4) 1725 # define MR1_BITS_5 (0 << 0) 1726 # define MR1_BITS_6 (1 << 0) 1727 # define MR1_BITS_7 (2 << 0) 1728 # define MR1_BITS_8 (3 << 0) 1729 # define MR1_PAR_EVN (0 << 2) 1730 # define MR1_PAR_ODD (1 << 2) 1731 # define MR1_PAR_NO (4 << 2) 1732 # define MR2_STOP1 (7 << 0) 1733 # define MR2_STOP2 (0xf << 0) 1734 #define SCCNXP_SR_REG (0x01) 1735 #define SCCNXP_CSR_REG SCCNXP_SR_REG 1736 # define SR_RXRDY (1 << 0) 1737 # define SR_FULL (1 << 1) 1738 # define SR_TXRDY (1 << 2) 1739 # define SR_TXEMT (1 << 3) 1740 # define SR_OVR (1 << 4) 1741 # define SR_PE (1 << 5) 1742 # define SR_FE (1 << 6) 1743 # define SR_BRK (1 << 7) 1744 #define SCCNXP_CR_REG (0x02) 1745 # define CR_RX_ENABLE (1 << 0) 1746 # define CR_RX_DISABLE (1 << 1) 1747 # define CR_TX_ENABLE (1 << 2) 1748 # define CR_TX_DISABLE (1 << 3) 1749 # define CR_CMD_MRPTR1 (0x01 << 4) 1750 # define CR_CMD_RX_RESET (0x02 << 4) 1751 # define CR_CMD_TX_RESET (0x03 << 4) 1752 # define CR_CMD_STATUS_RESET