International Workshop on Verification of Embedded Systems 2013
Preliminary Programme
| 9:00-9:10 | Openning | ||
| 9:10-10:30 | Alexey Khoroshilov | invited talk | Layered Modeling and Verification of Embedded Systems |
| 10:30-11:00 | Coffee break | ||
| 11:00-11:30 | Daniil Zorin, Vladislav Podymov, Dmitry Volkanov, Vladimir Zakharov, Alevtina Glonina and Igor Konnov | regular paper | An Experience on Using Simulation Environment DYANA Augmented with UPPAAL for Verification of Embedded Systems Defined by UML Statecharts |
| 11:30-12:00 | Pavel Drobintsev, Vsevolod Kotlyarov and Igor Nikiforov | regular paper | Semantics adjustment of UCM Real Time Constructions for Implementation in Translator of UCM to Basic Protocols. |
| 12:00-12:30 | Oleg Nenashev | regular paper | PHRT: A Programmable Tool for Automated Hardware Reengineering and Verification |
| 12:30-14:00 | Lunch | ||
| 14:00-14:30 | Oleksandr Letychevskyi | regular paper | Experiments with deductive testing of Reactive systems |
| 14:30-15:00 | Yevgeny Gerlits | research in progress | MC/DC coverage measurement of C programs |
| 15:00-15:30 | Moritz Sinn and Florian Zuleger | research in progress | Automatic Amortized Complexity Analysis for C Programs |
| 15:30-16:00 | Coffee break | ||
| 16:00-16:20 | Olga V. Mamoutova | research in progress | Processor-driven Emulated Upset-like Fault Injection for Memory Validation |
| 16:20-16:40 | Alexey Belyaev | research in progress | Symbolic Algorithm for Synthesis Distributed Discrete-Event Supervisory Control from LTL Specification |
| 16:40-17:00 | Irina Shoshmina | research in progress | Symbolic Algorithm Translating LTL Formula to Buchi Automaton |